Showing posts with label small-signal modeling. Show all posts
Showing posts with label small-signal modeling. Show all posts

Apr 7, 2021

[papers] compact modeling

Rabnawaz Sarmad Uqaili, Faraz Bashir Soomro, Junaid Ahmed Uqaili, Ahsin Murtaza Bughio 
and Khalid Ali Khan
Study on Compact Equivalent Circuit Model for RF CMOS Transistor 
International Journal of Scientific & Technology Research 
Vol.10, Issue 02, February 2021 ISSN 2277-8616

Abstract: In this study, a physical-based radio-frequency (RF) compact equivalent circuit model (CECM) for complementary metal-oxidesemiconductor (CMOS) transistor and its parameter extraction is presented. The whole structure of CECM that includes a small-signal equivalent circuit model of the transistor, a MOSFET small-signal substrate model, an input and output ground-signal-ground (GSG) pad model, a pad coupling model and a metal interconnection model are briefly studied and discussed. Based on this study, a complete test structure model for RF CMOS is designed and the initial values of parameters are extracted by using the analytical method. The multi-bias scattering parameters (S-Parameters) of model correspondence to the experimentation are validated up to 66 GHz and 220 GHz respectively. A good agreement has been achieved between the simulation and experimental under multi-bias conditions.
Fig: Complete CECM for RF CMOS transistor with an entire test structure.


El Mashade, Mohamed B., and Ahmed Abdel Monem
Transient model for modern microelectronic devices applicable to EKV PMOS model 
Radioelectronics and Communications Systems 
Vol.64, no. 2 (2021): 64-79

Abstract: Massive advances in microelectronic manufacturing technology with an exponential growth of their complexity and speed are needed to ensure a continuous development of novel techniques, structures, devices, circuits and systems. This paper is intended for the introduction of a new PMOS transient model for modern microelectronic devices that provides a fast transient response. Such suggested model expresses the transient terminal currents as polynomial functions of the normalized channel charge densities at the channel bounds with the assistance of a modified version of the cubic spline collocation methodology in symmetrical telescopic fashion. Additionally, the optimum number of segments, which is suitable for the new version of the cubic spline collocation algorithm, is investigated. Moreover, the normalized channel charge density at collocation points is modeled in terms of its values at the channel bounds through the quasi-static approach. Furthermore, by means of introducing an inverse function for the normalized overdrive channel voltage, the transient terminal currents are formulated as a function of the terminal voltages. In comparison with usual cubic spline collocation structure, the novel model has much better accuracy in its application to EKV structure. The developed model has been applied to the standard 0.15 mm technology and validated by MATLAB R2014a. The obtained results demonstrate that it gives a very high degree of relative accuracy, on average of 99%, for the total time and exhibits absolute error of less than 5% of the maximum value, in its worst case.


Rakeshkumar Mahto and Reshma John 
Modeling of Photovoltaic Module 
(April 1st 2021)
DOI: 10.5772/intechopen.97082. 

Abstract: A Photovoltaic (PV) cell is a device that converts sunlight or incident light into direct current (DC) based electricity. Among other forms of renewable energy, PV-based power sources are considered a cleaner form of energy generation. Due to lower prices and increased efficiency, they have become much more popular than any other renewable energy source. In a PV module, PV cells are connected in a series and parallel configuration, depending on the voltage and current rating, respectively. Hence, PV modules tend to have a fixed topology. However, in the case of partial shading, mismatching or failure of a single PV cell can lead to many anomalies in a PV module’s functioning. If proper attention is not given, it can lead to the forward biasing of healthy PV cells in the module, causing them to consume the electricity instead of producing it, hence reducing the PV module’s overall efficiency. Hence, to further the PV module research, it is essential to have an approximate way to model them. Doing so allows for understanding the design’s pros and cons before deploying the PV module-based power system in the field. In the last decade, many mathematical models for PV cell simulation and modeling techniques have been proposed. The most popular among all the techniques are diode based PV modeling. In this book chapter, the author will present a double diode based PV cell modeling. Later, the PV module modeling will be presented using these techniques that incorporate mismatch, partial shading, and open/short fault. The partial shading and mismatch are reduced by incorporating a bypass diode along with a group of four PV cells. The mathematical model for showing the effectiveness of bypass diode with PV cells in reducing partial shading effect will also be presented. Additionally, in recent times besides fixed topology of series–parallel, Total Cross-Tied (TCT), Bridge Link (BL), and Honey-Comb (H-C) have shown a better capability in dealing with partial shading and mismatch. The book chapter will also cover PV module modeling using TCT, BL, and H-C in detail.

Available: https://www.intechopen.com/online-first/modeling-of-photovoltaic-module


Jul 17, 2020

[paper] FD-SOI CMOS RF FoM

28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K
Lucas Nyssens1 (Graduate Student Member, IEEE), Arka Halder1, Babak Kazemi Esfeh1,
Nicolas Planes2, Denis Flandre1 (Senior Member, IEEE), Valeriya Kilchytska1
and Jean-Pierre Raskin1 (Fellow, IEEE)
IEEE J-EDS, vol. 8, pp. 646-654, 2020,
DOI: 10.1109/JEDS.2020.3002201
1UCL, 1348 Louvain-la-Neuve (B) 2ST-Microelectronics, 38920 Crolles (F)

Abstract: This work presents a detailed RF characterization of 28nm FD-SOI nMOSFETs at cryogenic temperatures down to 4.2K. Two main RF Figures of Merit (FoMs), i.e., current-gain cutoff frequency (fT) and maximum oscillation frequency (fmax), as well as parasitic elements of the small-signal equivalent circuit, are extracted from the measured S-parameters. An improvement of up to ∼130GHz in fT and ∼75GHz in fmax is observed for the shortest device (25nm) at low temperature. The behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28nm FD-SOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2K and clarifies the origin and limitations of the performance.
FIG: Small-signal equivalent circuit of the RF MOSFETs

Aknowledgement: This work was supported in part by Eniac “Places2Be” and in part by Ecsel “Waytogofast” Projects. The work of Lucas Nyssens was supported by the Fonds de la Recherche Scientifique - FNRS. This paper is based on a paper entitled “28 FDSOI RF Figures of Merit Down to 4.2 K,” presented at the 2019 IEEE S3S Conference.