Recent Compact Modeling Papers

[1] Hao Su, Yunfeng Xie, Yuhuan Lin, Haihan Wu, Wenxin Li, Zhizhao Ma, Yiyuan Cai, Xu Si, Shenghua Zhou Guangchong Hu, Yu He Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu, and Kai Chen; "Characterizations and Framework Modeling of Bulk MOSFET Threshold Voltage Based on a Physical Charge-Based Model Down to 4 K." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 733-736. IEEE, 2024. doi: 10.1109/ESSERC62670.2024.10719583

[2] Tung, Chien-Ting, Sayeef Salahuddin, and Chenming Hu; "A SPICE-Compatible Neural Network Compact Model for Efficient IC Simulations." In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04. IEEE, 2024.

[3] Jana, Koustav, Shuhan Liu, Kasidit Toprasertpong, Qi Jiang, Sumaiya Wahid, Jimin Kang, Jian Chen, Eric Pop, and H-S. Philip Wong; "Modeling and Understanding Threshold Voltage and Subthreshold Swing in Ultrathin Channel Oxide Semiconductor Transistors." In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04. IEEE, 2024.

[4] Manganaro, Gabriele. "Rethinking mixed-signal IC design." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 552-556. IEEE, 2024

[5] Wager, John F., Jung Bae Kim, Daniel Severin, Zero Hung, Dong Kil Yim, Soo Young Choi, and Marcus Bender; "Dual-Layer Thin-Film Transistor Analysis and Design." IEEE Open Journal on Immersive Displays (2024).

[paper] FOSS support for CM with Verilog-A

Bűrmen, Árpád, Tadej Tuma, Iztok Fajfar, Janez Puhan, Žiga Rojec, Matevž Kunaver

and Sašo Tomažič

Free software support for compact modelling with Verilog-A

Informacije MIDEM 54, no. 4 (October 9, 2024)

<https://ojs.midem-drustvo.si/index.php/InfMIDEM/article/view/1999>

Abstract: Verilog-A is the analog subset of Verilog-AMS - a hardware description language for analog and mixed-signal systems. Verilog-A is commonly used for the distribution of compact models of semiconductor devices. For such models to be usable a Verilog-A compiler is required. The compiler converts the model equations into a form that can be used by the simulator. Such compilers have been supplied with commercial simulators for many years now. Free software alternatives are much more scarce and limited in the features they offer. The paper gives an overview of Verilog-A, Free software Verilog-A compilers, and Free software/Open source simulators that can simulate compact models defined in Verilog-A. Advantages and disadvantages of individual compilers and simulators are highlighted.

Tab: Comparison of Free software simulators

Asterisk denotes a feature under development as of Sep. 2024

Acknowledgements: This research was funded in part by the Slovenian Research Agency within the research program ICT4QoL—Information and Communications Technologies for Quality of Life, grant number P2-0246.

[paper] Compact Modeling of Hysteresis in OTFTs

Compact modeling of hysteresis in organic thin-film transistors

A. Romero^a, J.A. Jiménez-Tejada^a, R. Picos^b, D. Lara^a, J.B. Roldán^a, M.J. Deen^c

Organic Electronics 129 (2024) 107048

DOI : 10.1016/j.orgel.2024.107048

a Departamento de Electrónica y Tecnología de Computadores, CITIC-UGR, Uni Granada, Spain
b Department of Industrial Engineering and Construction, Universitat de les Illes Balears, Spain
c Department of Electrical and Computer Engineering, McMaster University, Canada

Abstract: In this work, we propose a model that describes the temporal evolution of the threshold voltage and trapped charge density in Thin-Film Transistors (TFTs) under dynamic conditions, paving the way for the characterization and modeling of memory transistors. The model is expressed as a first-order differential equation for the trapped charge density, which is controlled by a time constant and an independent term proportional to the drain current. The time-dependent threshold voltage is introduced in a previously developed compact model for TFTs with special consideration to the contact effects. The combination of both models and the use of an evolutionary parameter extraction procedure allow for reproducing the experimental dynamic behavior of TFTs. The results of the model and the evolutionary procedure have been validated with published experimental data of pentacene-based transistors. The procedure is able to simultaneously reproduce three kinds of experiments with different initialization routines and constraints in each of them: output and transfer characteristics with hysteresis and current transients characteristics

FIG: a.) Modeling the contact regions and intrinsic channel of an OTFT structure (a bottom contact configuration); b.)  Comparison of experimental transfer characteristics

Acknowledgements : The authors acknowledge support from the project PID2022 139586NB-44 funded by MCIN/AEI/10.13039/501100011033 and FEDER, EU. Funding for open access charge: Universidad de Granada / CBUA.

Appendix: Supplementary material related to this article can be found online.

[PhD] Transient Simulation of Frequency Domain Devices in Gnucap

Adding transient simulation of frequency domain devices to the Gnucap circuit simulator

Phd Thesis by Seán Higginbotham

Supervisor: Assistant Prof. Justin King

April 2024

Trinity College Dublin, The University of Dublin

College Green, Dublin 2, Ireland

Abstract: Radio frequency design constitutes a dominant element in the development of key communications technologies. Having accurate, robust, and widely accessible simulation methods is critical to ensuring continued advancements in this field, and guaranteeing the associated infrastructural and societal shifts that such technologies enable.

High frequency circuits invariably contain multiple non-linear components, which are naturally dealt with via time marching simulation of their time-domain analytic equations. However, including this alongside linear, generally dispersive, devices and effects, which are typically only characterised through a set of frequency-domain data describing the scattering response of an associated port-network, has traditionally been a problem for designers. Frequency-domain methods such as the harmonic balance technique and its successors have dominated radio frequency design for decades. However, such methods exhibit disadvantages in the context of modern circuits which are increasingly non-linear, and which operate with increasingly complicated modulated signals.

Various alternatives have been proposed, though as of yet no universally accepted method has emerged. Though harmonic balance will likely not be replaced, this project seeks to implement one such pure transient technique as an alternative. The proposed technique is based on using the vector-fitting algorithm to produce a model of the frequency response of the linear portnetwork, and then using a recursive convolution formulation to allow the time-domain response to be efficiently obtained from the port’s impulse response. An equivalent circuit companion model is developed from the resulting time-domain power-wave relation. This companion model allows the linear device to be directly included in a transient simulation alongside the analytic non-linear components, by way of providing a manner of computing the voltage and current on the network’s ports.

We implement the technique for one-port networks in a circuit driven by baseband signals. It is added to the free, open-source Gnucap circuit simulator as a ‘device plugin’. This report details how the implementation was done and provides results illustrating that it works as intended; the plugin can be installed by a user, who simply provides it with a file of frequency-domain data representing the port-network, and the plugin works naturally with the Gnucap transient solver to allow obtaining a transient solution of the overall circuit. A pure transient technique such as this does not require limiting assumptions or approximations on any components in the circuit and they are therefore preferable in certain contexts to frequency-domain methods like harmonic balance.

The project offers a significant contribution towards increasing the accessibility of radiofrequency electronics design and teaching.

 FIG: Summary of the traditional approach to simulating RF/MW circuits via HB, and the proposed pure transient approach implemented in this PhD Thesis

Acknowledgements: Seán Higginbotham would like to thank my M.A.I supervisor Dr. Justin King, whose previous work was the basis for this project. He provided invaluable insights and guidance which made the project both possible and an enjoyable experience, instilling curiosity at each discussion. Relevant academic references are included in the bibliography section. Acknowledgements of the dependancies used in the project code follow.

Gnucap is the creation of Albert Davis and is developed by him and others. It is provided under the GNU GPLv3, which is also the license that this project code is provided under on the associated GitHub repository.

See https://www.gnu.org/licenses/gpl-3.0.html. For the GNU GPLv3 license. Additionally, see the Gnucap repository here https://savannah.gnu.org/projects/ gnucap/.

LAPACK is a co-creation of The University of Tennessee and The University of Tennessee Research Foundation, The University of California Berkeley, and The University of Colorado Denver. See the user guide here https://netlib.org/lapack/.

The LAPACKE C bindings are the creation of Intel Corp.

The relevant licensing files are found within the source code and on the respective website.

Should the reader of this report have any questions or suggestions, please feel free to reach out at higginbs@tcd.ie, or via other channels such as the project GitHub located at https: //github.com/SHigginbotham/transient-sparam-gnucap. The project supervisor may also be of interest, available at justin.king@tcd.ie.

[paper] SiC Power MOSFET SPICE modelling

Akbar Ghulam

Accurate & Complete behaviourial SPICE modelling 

of commercial SiC Power MOSFET OF 1200V, 75A

25th EuroSimE, Catania, Italy, 2024, pp. 1-4,

DOI: 10.1109/EuroSimE60745.2024.10491420

* UNIPA Palermo (IT)

Abstract: Silicon Carbide (SiC) is proved to be an excellent replacement for Silicon in high voltage and high frequency applications due to its electro-thermal properties. Since SiC power MOSFETs have only recently been more widely available commercially, accurate simulation models are immediately required to forecast device behavior and facilitate circuit designs. The goal of this paper is to develop an accurate LTSPICE model based on a modified Enz-Krumenacher-Vittoz (EKV), MOSFET model for a 1200V, 30mΩ & 75ASiC power MOSFET “SCTW100N120G2AG” provided by STMicroelectronics that is currently on the market. The modified EKV model outperforms the reduced quadratic model by describing MOSFET behavior over different zones which are weak, moderate, and strong inversion zones with only a single equation. A wide range of experimental data was used to build the model's parameters. To estimate device performance in high frequency switching applications, the model has been expanded to include package parasitic components that include parasitic capacitances. The model's static and transient properties were simulated, and the results were compared with those acquired from the actual device.

FIG: The SiC MOSFET's circuit schematic utilizing a modified EKV model

Acknowledgements: We would like to thank STMicroelectronics, as for completion of this study has been greatly aided by their participation and availability of relevant data.

[paper] Symmetric BSIM-SOI

Chetan Kumar Dabhi, Dinesh Rajasekharan, Girish Pahwa, Debashish Nandi, Naveen Karumuri, Sreenidhi Turuvekere, Anupam Dutta, Balaji Swaminathan, Srikanth Srihari, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu

Symmetric BSIM-SOI: A Compact Model for Dynamically Depleted SOI MOSFETs 

 in IEEE TED (2024)

Part I DOI: 10.1109/TED.2024.3363110

Part II DOI: 10.1109/TED.2024.3363117

1 Department of Electrical Engineering and Computer Sciences, UCB, CA, USA

2 Department of Electrical Engineering, IIT Kanpur, India

3 GlobalFoundries, Bengaluru, India

Abstract: In this article, we present a symmetric surface-potential-based model for dynamic depletion (DD) device operation of silicon-on-insulator (SOI) FETs for RF and analog IC design applications. The model accurately captures the device behavior in partial depletion (PD) and full depletion (FD) modes, as well as in the transition from PD to FD, based on device geometry, doping, and bias conditions. The model also exhibits an excellent source–drain symmetry during dc and small-signal simulations, resulting in error-free higher order harmonics. The model is fully scalable with bias, temperature, and geometry and has been validated extensively with real device data from the industry. The symmetric BSIM-SOI model is developed in Verilog-A and compatible with all commercial SPICE simulators.

FIG: (a) Schematic of a typical SOI MOSFET

(b) Cgg versus Vgb for different substrate bias, with the PD-to-FD transition 

Acknowledgment: The authors thanks the members of the Compact Model Coalition (CMC), particularly Geoffrey J. Coram and Jushan Xie, for testing the model and suggesting improvements. The authors appreciate the CMC QA team’s efforts in conducting a model quality check. Caixia Han and Xiao Sun from Cadence provided a few useful test cases. They thank Ananth Sundaram and Anamika Singh Pratiyush from GlobalFoundries India for the help and discussion regarding DDSOI model intricacies and development. Model code is available at BSIM Website <https://bsim.berkeley.edu/models/bsimsoi/>

[Open PDK] IEEE EDS DL at IISc Banglare

IEEE EDS/SSCS Bangalore Chapter Presents DL Series

FOSS TCAD/EDA Tools SPICE and Verilog-A

Modeling Flow Technology - Devices - Applications

W.Grabinski, MOS-AK (EU)

DATE AND TIME	LOCATION	HOSTS
Date: 07 Mar 2024 Time: 04:00 PM to 05:00 PM All times are (UTC+05:30) Chennai Add Event to Calendar iCal Google Calendar	Auditorium, Dept. of ESE, IISc Bangalore Karnataka India 560012	Bangalore Section Jt. Chapter ED15/SSC37

[FOSSDEM 2024] Open PDK Initiative

FOSDEM 2024 was a two-day event organized by volunteers to promote the widespread use of free and open source software. Took place at the ULB Solbosch campus in the beautiful city of Brussels (Belgium), FOSDEM is widely recognized as the best FOSS conference in Europe.

There were two DevRooms to discuss the status and further FOSS CAD/EDA IC design tools developments and open PDK initiative:

• Libre-SOC, FPGA and VLSI DevRoom
• Verilog-AMS in Gnucap
• FOSS CAD/EDA tools supporting the open access PDK initiative
• Open Hardware and CAD/CAM DevRoom
• ngspice circuit simulator - stand-alone and embedded into KiCad

FOSDEM'24 Inauguration Session

[paper] Neural Compact Modeling Framework

Eom, Seungjoon, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Seunghwan Lee, Jinsu Jeong, and Rock‐Hyun Baek

Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation

Advanced Intelligent Systems (2023): 2300435

DOI: 10.1002/aisy.202300435

Department of Electrical Engineering, Pohang University of Science and Technology, Pohang 37673 (KR)

Abstract: Neural compact models are proposed to simplify device-modeling processes without requiring domain expertise. However, the existing models have certain limitations. Specifically, some models are not parameterized, while others compromise accuracy and speed, which limits their usefulness in multi-device applications and reduces the quality of circuit simulations. To address these drawbacks, a neural compact modeling framework with a flexible selection of technology-based model parameters using a two-stage neural network (NN) architecture is proposed. The proposed neural compact model comprises two NN components: one utilizes model parameters to program the other, which can then describe the current–voltage (IV) characteristics of the device. Unlike previous neural compact models, this two-stage network structure enables high accuracy and fast simulation program with integrated circuit emphasis (SPICE) simulation without any trade-off. The IV characteristics of 1000 amorphous indium–gallium–zinc-oxide thin-film transistor devices with different properties obtained through fully calibrated technology computer-aided design simulations are utilized to train and test the model and a highly precise neural compact model with an average IDS error of 0.27% and R2 DC characteristic values above 0.995 is acquired. Moreover, the proposed framework outperforms the previous neural compact modeling methods in terms of SPICE simulation speed, training speed, and accuracy.

Fig: a) The structure of a-IGZO TFT structure simulated with TCAD

b) Calibrated a-IGZO sub-gap DOS

Acknowledgements: This work was supported in part by the LG Display Company, in part by the Brain Korea 21 Fostering Outstanding Universities for Research (BK21 FOUR) program, in part by Institute of Information and Communications Technology Planning and Evaluation (IITP) grant funded by the Korea government (MSIT) (grant no. 2019-0-01906, Artificial Intelligence Graduate School Program [POSTECH]), in part by the Ministry of Trade, Industry and Energy (MOTIE) under grant no. 20020265, in part by Korea Semiconductor Research Consortium (KSRC) support program for the development of the future semiconductor device, and in part by the Technology Innovation Program (grant no. RS2023-00231985) funded by the Ministry of Trade, Industry and Energy (MOTIE, Korea) (grant no. 1415187390).

[paper] PSP RF Model

Xiaonian Liu1, 2, and Yansen Liu1, 2

Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract: An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 µm CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The PSP RF subcircuit model and its S-par s fitting

results of NMOS with Wf = 2 µm, Lf = 0.12 µm, nf = 16

Acknowledgment: This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

[paper] PSP RF Model

Xiaonian Liu^{1, 2} and Yansen Liu¹

A Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

DOI :10.2528/PIERL23081405

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China.
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract : An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The RF PSP Model Subcircuit

Acknowledgment : This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

[paper] Surface-Potential-Based Compact Modeling

M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, H. J. Mattausch, and S. Saha

Evolution of Surface-Potential-Based Compact Modeling

IEEE EDS NEWSLETTER

OCTOBER 2023 VOL. 30, NO. 4 ISSN: 1074 1879

Abstract: Conventionally, a compact model of an electronic device is developed for utilization in circuit simulation. This means that the main task of the compact model is to accurately describe the characteristics of a device as a function of the applied voltages by simple equations in order to predict the performance of circuits using this device with sufficient precision. This overview article focuses on the compact modeling of the metal-oxide-semiconductor field-effect transistor (MOSFET)-device structure, which has the largest variety of applications. However, the modeling methodology is valid for any type of transistor or electronic device. The development of the compact modeling approach, based on the potential distribution induced within a transistor, is reviewed. The purpose of a compact model is to describe the transistor characteristics in a simple but accurate way, to enable correct circuit-performance prediction. Therefore, the basic physics of observed phenomena must be modeled by simplified and yet physically correct equations. To meet such requirements, potential-based modeling is a natural fit. A compact model and TCAD are both based on the same transistor equations. The difference is that TCAD considers the distribution of all physical quantities within a device, and a compact model integrates these distributions to calculate transistor characteristics at its nodes. The shortcomings of resulting simplifications, introduced for analytical integration, can be examined using TCAD, to identify observed phenomena still missing in the compact modeling. In this way, compact modeling is performed by learning from measurements macroscopically and from TCAD microscopically.

Fig: Schematic of a HV LDMOS FET (top) 

and its potential distribution (bottom)

[book] Microelectronic Circuits

Sedra, Adel S., Smith, Kenneth Carless, Carusone, 

Tony Chan, Gaudet, Vincent. 

Microelectronic Circuits. 

United Kingdom: Oxford University Press, 2020

Circuits by Sedra and Smith has served generations of electrical and computer engineering students as the best and most widely-used text for this required course. Respected equally as a textbook and reference, "Sedra/Smith" combines a thorough presentation of fundamentals with an introduction to present-day IC technology. It remains the best text for helping students progress from circuit analysis to circuit design, developing design skills and insights that are essential to successful practice in the field. Significantly revised with the input of two new coauthors, slimmed down, and updated with the latest innovations, Microelectronic Circuits, Eighth Edition, remains the gold standard in providing the most comprehensive, flexible, accurate, and design-oriented treatment of electronic circuits available today.

Appendix

• B. SPICE Device Models and Design with Simulation Examples

Model files for representative CMOS technologies are provided below:

• 0.8 um CMOS
• 0.35 um CMOS
• 0.18 um CMOS
• 45 nm CMOS
• 7nm FinFET

 

[11k online viewers] 7th Sino MOS-AK/Nanjing

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

7th Sino MOS-AK Workshop in Nanjing (CN)

August 11-13, 2023 (online/onsite)

Recent, consecutive, 7th Sino MOS-AK/Nanjing Workshop discussing the Compact/SPICE modeling and its Verilog-A Standardization reached 11k online viewers. The MOS-AK participants and online attendees have followed one day SiC-related device modeling training on August 11 featured presentations by experts currently working at Robert Bosch GmbH and then two days workshop with 24 R&D Compact/SPICE modeling presentations:

FOSS Circuit Simulators

AN OPEN-SOURCE, FREE CIRCUIT SIMULATOR

by: Bryan Cockfield on July 30, 2023

The original circuit simulation software, called the Simulation Program with Integrated Circuit Emphasis, or SPICE as it is more commonly known, was originally developed at the University of Califorina Berkeley in the 1970s with an open-source license. That’s the reason for the vast versions of SPICE available now decades after the original was released, not all of which are as open or free as we might like [1].

Fig: The Quite Universal Circuit Simulator includes a GUI based on the Qt toolkit and handles ad and ac analysis, S-parameters, harmonic balance analysis, noise analysis, and so forth. 

We’ve [2] listed all the simulators we found - the good, the bad, and the ugly - that actually did perform circuit simulation in some fashion. They are provided alphabetically, along with the most notable benefits and drawbacks we uncovered.

REF:
[1] An Open-Source, Free Circuit Simulator by Bryan Cockfield on July 30, 2023
[2] Best free analog circuit simulators by Lee Teschler on January 26, 2022

[paper] THz FET Modeling

Adam Gleichman¹, Kindred Griffis¹, and Sergey V. Baryshev^1,2

Useful Circuit Analogies to Model THz Field Effect Transistors

arXiv:2307.07488v1 [physics.app-ph] 14 Jul 2023

1) Department of Electrical and Computer Engineering, Michigan State University, USA
2) Department of Chemical Engineering and Materials Science, Michigan State University, USA

Anstract: The electron fluid model in plasmonic field effect transistor (FET) operation is related to the behavior of a radio-frequency (RF) cavity. This new understanding led to finding the relationships between physical device parameters and equivalent circuit components in traditional parallel resistor, inductor, and capacitor (RLC) and transmission models for cavity structures. Verification of these models is performed using PSpice to simulate the frequency dependent.

FIG: RLC Lumped THz FET Model

[paper] TMD FETs

Ahmed Mounir^a, Benjamin Iñiguez^a, François Lime^a, Alexander Kloes^b

Theresia Knobloch^c, Tibor Grasser^c

Compact I-V model for back-gated and double-gated TMD FETs

Solid-State Electronics (2023): 108702

DOI: 10.1016/j.sse.2023.108702

a Rovira I Virgili University, Tarragona, Spain
b University of Applied Sciences, Giessen, Germany
c TU Wien, Vienna, Austria

Abstract: A physics-based analytical DC compact model for double and single gate TMD FETs is presented. The model is developed by calculating the charge density inside the 2D layer which is expressed in terms of the Lambert W function that recently has become the standard in SPICE simulators. The current is then calculated in terms of the charge densities at the drain and source ends of the channel. We validate our model against measurement data for different device structures. A superlinear current increase above certain gate voltage has been observed in some MoS2 FET devices, where we present a new mobility model to account for the observed phenomena. Despite the simplicity of the model, it shows very good agreement with the experimental data.

Fig : 2D schematic structure for 2D TMD FETs: (a) a double gated monolayer MoS2 FET. 

(b) a double gated monolayer WSe2 FET. (c)  single back-gated multilayer MoS2 FET. 

(d) single back-gated monolayer FET.

OpenPDK Networking Workshop

OpenPDK, OpenTooling and Open Source Design

An Initiative to Push Development

Date:
Networking Workshop FMD-QNC on 27-28 June 2023
Location:
IHP; Im Technologiepark 25; 15236 Frankfurt (Oder)
Contact:
Sergei Andreev; Phone: +49 335 5625 523

Free Registration: 

OnLine

The workshop is organised by IHP and FMD (Research Fab Microelectronics Germany) within the framework of the FMD-QNC Project.

Within the project FMD-QNC analog circuit design with open source software shall be enabled. For this purpose, both the open source design tools and a process design kit of the semiconductor technology used must support the entire design flow with sufficient quality. IHP provides its 130 nm BiCMOS technology SG13G2 for open source design. This technology is particularly suited for high frequency and mixed signal design applications. While basic tool support already exists for digital circuit design, it is still very rudimentary for analog designs and especially for high frequency designs. A considerable effort has to be put into the development of the design tools as well as into the creation of the technology specific Process Design Kit (PDK).

The 2-day workshop is intended to promote exchange and networking between tool developers, the PDK developers at IHP and designers. Tool developers are to present the capabilities of the tools as well as planned enhancements. Designers are to present ideas that can be used for training chip designers. Requirements for open source design tools for digital design, mixed signal design, and high frequency design are to be highlighted.

Discussions will identify and prioritize gaps for a complete design flow in the open source tools and PDK. The workshop will thus help to concrete the planning for the Open Design Platform and to create a roadmap for future work.

Presentation	Presenter/Institution	Timeline
Day 1
Welcome by coordinator FMD-QNC	Dr. Andreas Bruning Research Fab Microelectronics Germany	9:00-9:10
Introduction FMD-QNC project status and IHP OpenPDK Roadmap	Dr. Rene Scholz IHP	9:10-9:30
Status OpenPDK and OpenTooling for SG13G2 BiCMOS technology	Sergei Andreev IHP	9:30-10:00
An Ultra-Low-Power High-Density Wireless Biomedical Sensing System	Prof. Harald Pretl Johannes Kepler University Linz	10:00-10:30
Teaching digital design by using open-source EDA tools	Prof. Steffen Reith Rhein Main University of Applied Sciences	10:30-11:00
Coffee break		11:00-11:40
CMOS Rail-to-Rail Operational Amplifier for HPGe Radiation Detector	Prof. Herman Jalli Ng Karlsruhe University of Applied Sciences	11:40-12:10
Design-flow approaches for mmWave and sub-THz integrated transceiver circuits for radar and communication	Sasha Breun FAU Erlangen	12:10-12:40
Lunch break		12:40-13:40
TBD	Dr. Frank K. Gurkaynak ETH Zurich	13:40-14:10
TBD	Joachim Hebeler Karlsruhe Institute of Technology	14:10-14:40
Coffee break		14:40-15:10
TBD	Prof.  Dietmar Kissinger Ulm University	15:10-15:40
LibMan - an easy way to manage your open source design flow	Dr. Anton Datsuk IHP	15:40-16:10
Get together (Barbecue)		17:00-…
Day 2
ngspice - status and future developments	Prof. Holger Vogt	9:00-9:20
DMT - Python Toolkit for Device Modeling	Mario Krattenmacher SemiMod	9:20-9:40
OpenVAF - Next Generation Verilog-A Compiler with ngspice integration	Mario Krattenmacher SemiMod	9:40-10:00
Coffee break		10:00-10:40
Best practices for implementing and optimizing KLayout DRC and LVS decks	Matthias Köfferlein	10:40-11:00
Generating DRC and LVS Runsets for KLayout	Dr. Andreas Krinke TU Dresden	11:00-11:20
OpenEMS in open source EDA	Jan Taro Svejda University of Duisburg-Essen	11:20-11:40
Lunch break		11:40-12:40
Panel discussion on the roadmap – open source tools for IC design Topics: Digital design flow Analog design flow Challenges in RF design	Dr. Norbert Herfurth IHP Panelists: TBD	12:40-14:10

[paper] Extraction and Automated FEMM Creation of a Transformer SPICE Model

Denys I. Zaikin

Extraction of Transformer Parameters from FEMM Simulations 

and Automated Creation of a Transformer SPICE Model Using a Scripting Language

TechRxiv. Preprint. DOI 10.36227/techrxiv.22263358.v1

*Advent Technologies A/S Lyngvej 8, Aalborg, 9000, Denmark e-mail: denys.zaikin@advent.energy

Abstract: This study presents a method for extracting transformer parameters using simulations in the Finite Element Method Magnetics (FEMM) electromagnetic solver. The extracted parameters represent a full model of a linear transformer and can be used in Simulation Program with Integrated Circuit Emphasis (SPICE) simulations. A model of the transformer is presented in three variants, for which different approaches were used in the transformer simulation in the SPICE program, all yielding the same simulation results. A method for extracting transformer parameters from FEMM is proposed, along with an automated tool based on a scripting language built into the FEMM software [Online open souce https://www.femm.info]

FIG: An example of the simulation setup in FEMM 

and transformer equivalent circuits SPICE Pi-model

[paper] Framework for FPGA Emulation of IC Designs

S. Herbst, G. Rutsch, W. Ecker and M. Horowitz

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

vol. 41, no. 7, pp. 2223-2236, July 2022

DOI: 10.1109/TCAD.2021.3102516

Abstract: This article presents an open-source framework for emulating mixed-signal chip designs on a field-programmable gate array (FPGA). It includes a Python-based synthesizable model generator for mixed-signal blocks (msdsl), a fixed-point and floating-point synthesizable SystemVerilog library for representing real numbers (svreal), and a Python-based tool that generates emulator control infrastructure and automates the FPGA build process (anasymod). The framework includes features for efficiently modeling analog dynamics, nonlinearity, and noise, often making use of compile-time caching to reduce the required computational resources of the FPGA. We demonstrate the framework’s generality by discussing three applications: 1) a high-speed link receiver (DragonPHY); 2) a firmware-controlled flyback converter; and 3) an NFC-powered chip. Our framework makes it easy to emulate these systems, while providing runtimes 2–3 orders of magnitude faster than CPU simulations with real-number functional models. FOSS framework, depicted in Fig. 1, consists of three tools: 1) msdsl ; 2) svreal; and 3) anasymod. All three tools released as open source can be installed either from GitHub or by using the Python package manager (pip).

FIG: Overview of FOSS AMS emulation framework. Analog models are described in Python and compiled into synthesizable SystemVerilog using msdsl, leveraging svreal to implement real-number operations. anasymod then wraps emulator control infrastructure around the DUT and automates EDA tools to produce an FPGA bitstream.