#Efabless & #OpenROAD Advance Commercial #OpenSource #Chip #Design

#Efabless & #OpenROAD Advance Commercial #OpenSource #Chip #Design https://t.co/h6mSqWzJHh #semi https://t.co/u3TDibKq9I

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[special issue] on Modeling of μmWave and mmWave Electronic Devices for Wireless Systems

Guest editorial for the special issue 

on Modeling of μmWave and mmWave Electronic Devices for Wireless Systems: 

Connecting technologies to applications

Valeria Vadalà, Giovanni Crupi

First published: 27 July 2021; DOI: 10.1002/jnm.2940

The μmWave and mmWave frequencies have been historically associated with niche applications such as space and defense; however, in the last years wireless communications have caused a rapid growth of interest in mass-market applications, representing the enabling technology for the new Information Age where all “things” need to be connected. Internet of Things, Industry 4.0, and Smart Cities are portraits of this concept in different contexts, from entertainment to healthcare applications. This exciting scenario triggers the continuous increase of performance requirements such as huge bandwidth, low latency, and very high data rate of emerging wireless technologies (i.e., 5G and 6G). This special issue takes a step forward in the different branches of knowledge related to μmWave and mmWave devices, circuits, and systems, oriented to wireless applications from the device level up to the application level. From the reader's point of view, the goal is to drive to a comprehensive overview on salient aspects of these topics and to provide interesting hints to overcome the upcoming technological challenges.

REFERENCES:
[1] Cao K-J, Zhang A, Gao J-J. Sensitivity analysis and uncertainty estimation in small-signal modeling for InP HBT (invited paper). Int J Numer Model El. 2021; 34(5): 2851. DOI: 10.1002/jnm.2851
[2] Tang X, Yang T, Jia Y, Xu Y. FW-EM-based approach for scalable small-signal modeling of GaN HEMT with consideration of temperature-dependent resistances. Int J Numer Model El. 2021; 34(5):e2882. DOI: 10.1002/jnm.2882
[3] King JB. Efficient energy-conservative dispersive transistor modelling using discrete-time convolution and artificial neural networks. Int J Numer Model El. 2021; 34(5): 2894. DOI: 10.1002/jnm.2894
[4] Li Y, Mao S, Fu Y, et al. A scalable electrothermal model using a three-dimensional thermal analysis model for GaN-on-diamond high-electron-mobility transistors. Int J Numer Model El. 2021; 34(5):e2875. DOI: 10.1002/jnm.2875
[5] Alim MA, Ali MM, Crupi G. Measurement-based analysis of GaAs HEMT technologies: Multilayer D-H pseudomorphic HEMT versus conventional S-H HEMT. Int J Numer Model El. 2021; 34(5):e2873. DOI: 10.1002/jnm.2873
[6] Osmanoglu S, Ozbay E. From model to low noise amplifier monolithic microwave integrated circuit: 0.03–2.6 GHz plastic quad-flat no-leads packaged Gallium-Nitride low noise amplifier monolithic microwave integrated circuit. Int J Numer Model El. 2021; 34(5):e2859. DOI: 10.1002/jnm.2859
[7] Piacibello A, Costanzo F, Giofré R, et al. Evaluation of a stacked-FET cell for high-frequency applications (invited paper). Int J Numer Model El. 2021; 34(5):e2881. DOI: 10.1002/jnm.2881
[8] Wu M, Cai J, King J, Chen S, Su J, Cao W. Design of a multi-octave power amplifier using broadband load-pull X-parameters. Int J Numer Model El. 2021; 34(5):e2878. DOI: 10.1002/jnm.2878
[9] Abdulbari AA, Abdul Rahim SK, Soh PJ, Dahri MH, Eteng AA, Zeain MY. A review of hybrid couplers: State-of-the-art, applications, design issues and challenges. Int J Numer Model El. 2021; 34(5):e2919. DOI: 10.1002/jnm.2919
[10] Piltyay S, Bulashenko A, Sushko O, Bulashenko O, Demchenko I. Analytical modeling and optimization of new Ku-band tunable square waveguide iris-post polarizer. Int J Numer Model El. 2021; 34(5):e2890. DOI: 10.1002/jnm.2890
[11] Qas Elias BB, Soh PJ, Abdullah Al-Hadi A, Vandenbosch GAE. Design of a compact, wideband, and flexible rhombic antenna using CMA for WBAN/WLAN and 5G applications. Int J Numer Model El. 2020; 34(5):e2841. DOI: 10.1002/jnm.2841
[12] Zhang X, Cunjun R, Dai J, Ding Y, Ullah S, Kosar Fahad A. Design of a reconfigurable antenna based on graphene for terahertz communication. Int J Numer Model El. 2021; 34(5):e2911. DOI: 10.1002/jnm.2911
[13] Gatte MT, Soh PJ, Kadhim RA, Abd HJ, Ahmad RB. Modeling and performance evaluation of antennas coated using monolayer graphene in the millimeter and sub-millimeter wave bands. Int J Numer Model. 2021; 34(5):e2929. DOI: 10.1002/jnm.2929
[14] Xing C, Qi F, Liu Z, Wang Y, Guo S. Terahertz compressive imaging: understanding and improvement by a better strategy for data selection. Int J Numer Model El. 2021; 34(5):e2863. DOI: 10.1002/jnm.2863

#STM Manufactures First #200mm Silicon Carbide #SiC #Wafers

#STM Manufactures First #200mm Silicon Carbide #SiC #Wafers [ST News https://t.co/BTdQoaGlnA] #semi https://t.co/cgX8Jxqtsy

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[paper] Above Vth Model for SC DG MOSFETs

David Chuyang Hong; Yuan Taur

An Above Threshold Model for Short-Channel DG MOSFETs

in IEEE TED, vol. 68, no. 8, pp. 3734-3739, Aug. 2021

DOI: 10.1109/TED.2021.3092310.

*Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA

Abstract: An above-threshold I–V model is developed for short-channel double-gate (DG) MOSFETs. It is a non-gradual channel approximation (non-GCA) model that takes into account the contribution to carrier density from the encroachment of source–drain bands into the channel. At low-drain bias voltages, the effect appears as a gate-voltage-dependent reduction of channel resistance, with stronger effects at low gate overdrives. At high-drain biases, the intersection of source band encroachment with the gate-controlled channel potential leads to a point of virtual cathode a small distance from the source. By incorporating the depletion of carriers in the source and drain regions into the boundary conditions, the Ids-Vds and Ids-Vgs characteristics generated by the model are shown to be consistent with TCAD simulations.

Figure below shows the schematic of a DG MOSFET (undoped). The device operation is governed by 2-D Poisson’s equation

Fig: Schematic of a DG MOSFET. The parameters assumed are tsi=4nm, ti=2nm, εsi=εi=11.8ε0, with channel length L ranging from 15 to 7nm. The gate work function is 0.28eV below that of intrinsic silicon so Vt=0.247V.

[paper] VNWFET Including Tied Compact Model

Arnaud Poittevin1, Chhandak Mukherjee2, Ian O’Connor1, Cristell Maneux2, Guilhem Larrieu3,4, Marina Deng2, Sebastien Le Beux1, Francois Marc2, Aurélie Lecestre3, Cedric Marchand1, 

and Abhishek Kumar3

3D Logic Cells Design and Results Based on Vertical NWFET Technology 

Including Tied Compact Model

In: Calimera A. (eds) VLSI-SoC: Design Trends. VLSI-SoC 2020. IFIP Advances in Information and Communication Technology, vol 621. pp 301-321 Springer, Cham.

DOI: 10.1007/978-3-030-81641-4_14

1 Lyon Institute of Nanotechnology, University of Lyon, France
2 University of Bordeaux, CNRS UMR 5218, Bordeaux INP Talence, Bordeaux, France
3 Université de Toulouse, LAAS, CNRS, INP Toulouse, Toulouse, France
4 Institute of Industrial Science, LIMMS-CNRS/IIS, The University of Tokyo, Japan

Abstract. Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices, which are well suited to pursue scaling beyond lateral scaling limitations around 7 nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model, which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50 nm. We used this model to simulate the projected performance of inverter logic gates based on passive load, active load and complementary topologies and to carry out a performance exploration for the number of nanowires in transistors. In terms of compactness, through a dedicated full 3D layout design, we also demonstrate a 48% reduction in lateral dimensions for the complementary structure with respect to 7 nm FinFET-based inverters.

Fig: Perspective view of the Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET)

Acknowledgments: This work was supported by the French RENATECH network (French national nanofabrication platform) and by the LEGO project through ANR funding (Grant ANR-18-CE24-0005-01).

[paper] NCFET CMOS Logic

Reinaldo Vega, Senior Member, IEEE, Takashi Ando*, Senior Member, IEEE,  

Timothy Philip, Member, IEEE

Junction Design and Complementary Capacitance Matching 

for NCFET CMOS Logic 

IEEE J-EDS 2021

DOI 10.1109/JEDS.2021.3095923

IBM Research, Albany, NY 12203

* IBM T.J. Watson Research Center, Yorktown Heights, NY 10598

Abstract: Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device Vt menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization (Pr) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ ferroelectric/ metal/ insulator/ semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec SS over > 6 decades. In a CMOS circuit, due to CCM, low-Vt pairs provide steeper subthreshold swing (SS) than high-Vt pairs. Transient power/performance is also modeled, and it is shown that a DC optimal NCFET design, employing broad junctions, CCM, and a low-Vt NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.

Fig: Equivalent capacitance network and illustrative C-V curve showing NMOS and NC curves. CNC > CINV results in non-hysteretic switching, but low voltage gain in the off-state due to CNC >> COV. Setting CNC to CNC2, which is matched more closely to COV, results in very low SS, but also hysteretic switching as CNC2 < CINV. 

Acknowledgment: The authors would like to thank Paul Solomon and Prof. Sayeef Salahuddin for insightful discussions, as well as Synopsys for technical support.

[Final Program] 18th MOS-AK ESSDERC/ESSCIRC Workshop Grenoble; Sept. 6, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

18th MOS-AK ESSDERC/ESSCIRC Workshop

Grenoble, Sept. 6, 2021

Together with local Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we invite you to the consecutive 18th MOS-AK ESSDERC/ESSCIRC Workshop. Scheduled Virtual/Online MOS-AK event aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK Workshop Program is available online: 

https://www.mos-ak.org/grenoble_2021/

Venue: Online MOS-AK Webinar;

use the online form/link below to register.

Online Registration is open

any related enquiries can be sent to registration@mos-ak.org

Post-workshop publications, selected, the best papers will be recommended for further publication in the special compact/SPICE modeling issue of the Solid State Electronics.

-- W.Grabinski; MOS-AK (EU)

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Enabling Compact Modeling R&D Exchange

www.mos-ak.org

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WG210721

[paper] Compact Analytical Modeling of FD Dual Material DG MOSFET

Shahana Akter1, Md. Mirazur Rahman1 and Md. Arif Abdulla Samy2

Compact Analytical Modeling of Surface Potential 

of a fully depleted Dual Material Double Gate MOSFET

Materials Mechatronics and Systems Engineering 2021, 1, 1. https://citescript.com/Journals/index.php/mmsj/

1 Department of EEE, Primeasia University
2 ATLAS Experiment, CERN

Abstract: Scaling transistors to gain speed while reducing capacitance and cost, is a key topic of today’s semiconductor industry, which is widely affected by Short-Channel Effects, the phenomenon that reduces efficiency. To dominate that unwanted effect, a 2-dimensional electrostatic potential modeling of the fully depleted channel, with high-k based dual material double gate (DMDG) MOSFET, has been developed in this paper. The expression for the electrostatic potential of DMDG has beendeveloped using 2-D Poisson’s equation with appropriate device boundary conditions. The device performance has been analyzed with the variation in device parameters, such as channel length, channel thickness, oxide thickness, and other key parameters. For authenticating, results have also been compared with state-of-the-art published results. This research was successful to exhibit that the proposed model could overcome Drain-induced Barrier Lowering, enhancing mobility carrier resulting to optimize short channel effect, which can bring a revolutionary change in transistor industry as well as in low power VLSI applications.

Fig: Device structure for the 2D double gate MOSFET

Acknowledgment: Authors would like to thank Professor Dr. Quazi Deen Mohd Khosru for his guidance in every step of this research. Without his valuable and persistent help, it would not be possible to conclude this project. The project has no external funding.

[paper] 11.8 GHz Fin Resonant Body Transistor

Analysis and Modeling of an 11.8 GHz Fin Resonant Body Transistor 

in a 14nm FinFET CMOS Process 

Udit Rawat, Student Member, IEEE, Bichoy Bahr*, Member, IEEE, 

and Dana Weinstein, Senior Member, IEEE

arXiv:2107.04502v1 [physics.app-ph] 9 Jul 2021

 

Department of Electrical Engineering, Purdue University, West Lafayette USA

*Kilby Labs - Texas Instruments, Dallas, TX, USA.

Abstract: In this work, a compact model is presented for a 14 nm CMOS-based FinFET Resonant Body Transistor (fRBT) operating at a frequency of 11.8 GHz and targeting RF frequency generation/filtering for next generation radio communication, clocking, and sensing applications. Analysis of the phononic dispersion characteristics of the device, which informs the model development, shows the presence of polarization exchange due to the periodic nature of the back-end-of-line (BEOL) metal PnC. An eigenfrequency-based extraction process, applicable to resonators based on electrostatic force transduction, has been used to model the resonance cavity. Augmented forms of the BSIM-CMG (Common Multi-Gate) model for FinFETs are used to model the drive and sense transistors in the fRBT. This model framework allows easy integration with the foundry-supplied process design kits (PDKs) and circuit simulators while being flexible towards change in transduction mechanisms and device architecture. Ultimately, the behaviour is validated against RF measured data for the fabricated fRBT device under different operating conditions, leading to the demonstration of the first complete model for this class of resonant device integrated seamlessly in the CMOS stack.

Fig: Complete 3D FEM Simulation model depicting two adjoining fRBT unit cells. Mx (x=1-3) and Cy (y=4-6) represent the first 6 metal levels that form a part of the BEOL PnC.

Acknowledgement: This work was supported in part by the DARPA MIDAS Program.

 

#MEMS becoming more #human

#MEMS becoming more #human https://t.co/aPG0GWl0Yq #semi https://t.co/kkUyTs4HN7

— Wladek Grabinski (@wladek60) Jul 21, 2021

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VSD Free Webinar - Mixed-signal RISC-V based SoC on FPGA - 23rd July, 7pm IST

 

This 60-min webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to Verilog language and is a part of a mixed-signal SoC

If you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferred

This single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verification

Stay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board.

Agenda:

1. "FPGA on eSim"
   Guest Speaker - Prof. Kannan M Moudgalya, IIT Bombay
2. "chipIgnite Program"
   Guest Speaker - Mike Wishart, CEO eFabless
3. "Tapeout World Program"
   Guest Speaker - Naveed Sherwani, Chairman, OSFPGA
4. "Mixed-signal RISC-V based SoC on FPGA"
   Webinar Instructor - Shivani Shah

Webinar Curriculum:
1) Introduction
2) RVMYTH RISC-V Core
3) Why FPGAs ?
4) TL - Verilog to RTL verilog using Makerchip
5) Functional Simulation using iverilog
6) FPGA - Steps to create project
7) FPGA - Steps to generate IPs
8) FPGA - RTL simulation
9) FPGA - Synthesis
10) FPGA - Implementation and timing analysis
11) FPGA - Bit-stream generation, FPGA programming and ILA
12) Conclusion

Register here (if you don't see the form, please refresh page):
https://lnkd.in/gByg6fZ

[Announcement] ToM 2021/2 online on September 21st-23rd

ToM2021/2 course will be held online on September 21st-23rd, 2021 with the following program:

September 21 2021
    14:00 – 17:30 Jussi Jansson (Oulu University, Finland) - "Time-to-digital converters and related applications"
September 22 2021
    09:00 – 12:30 Luca Scandola (Infineon Technologies, Italy), "Introduction to DC-DC conversion suitable for automotive application: from the theory to the modelization with practical examples"
    14:00 – 17:30 Benoit Bakeroot (Ghent University, Belgium), "GaN semiconductor devices for power electronics: overview, status and future perspectives"
September 23 2021
    09.00 – 12:30 Qiang Li (UETSC, China), "Subthreshold and near-threshold ADC techniques"
    14:00 – 17:30 Andrea Mazzanti (University of Pavia, Italy) and Enrico Monaco (Inphi, Italy), "Introduction and advances in serial links"

=============================================

Registration is mandatory to attend the course:
http://www.innotechevents.com/index.php?page=ToM/RegistrationForm.html

Registered participants will receive:
- on-line attendance to all lectures
- pdf material for all lectures
- certificate of participation
- final exam with certificate (if needed)

We look forward to virtually meeting you !!!!

More information at:
http://www.innotechevents.com/index.php?page=ToM/ToM.html

Best regards
Andrea Baschirotto

#SiFive Technical Symposium // India and Bangladesh

#SiFive Technical Symposium // India and Bangladesh https://t.co/ssXogdcGYQ #RISC-V #semi #core #IP https://t.co/t1Ti0wrNnp

— Wladek Grabinski (@wladek60) Jul 15, 2021

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July 15, 2021 at 11:41AM
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Last chance for IEEE Mauritius Conference

Dear colleagues, Due to many requests, the paper submission deadline has been extended to 25th July 2021 ! This is last due date . We are pleased to invite you to participate to the IEEE - International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME) which will be held in Mauritius, the Paradise Island on 07-08 October, 2021. The ICECCME is the premier event that brings together industry professionals, academics, and engineers from the related institutions to exchange information and ideas on electrical, computer, communications and mechatronic engineering. All accepted and presented papers will be submitted to IEEE Xplore for publication. The extended versions of selected papers will be published in SCI-indexed Energies journal with IF: 2.702 Due to the Covid pandemic, ICECCME will be held both face-to-face and online. Participants can make their presentations online. You can see all the details on the conference web page: http://www.iceccme.com The conference will take place in Mauritius surrounded by the warm Indian Ocean. Mauritius is one of the best holiday destinations in the world with clear warm sea waters, attractive beaches, tropical fauna and flora. Come to Mauritius, reward yourself! If you would like to be a reviewer... You can review the papers from our conferences and journal. By acting as a reviewer, you can earn discounts on conference participation fees (from any of our conferences). In addition we will send reviewer certificate. Click here to reviewer application Important Dates: Paper Due :  25 July, 2021 Acceptance Notification :  10 August, 2021 Early Registration Deadline: 15 August, 2021 Camera Ready Due : 20 August, 2021 Conference Dates: 7-8 October 2021 Best regards, Conference Organizing Team E-mail: info@iceccme.com   Phone(Whatsapp): +90 532 6425237 Projenia R&D Co. Erciyes TGB, No:67/10 TR Follow us on social media to be informed for our events.   If you do not want to receive mail from us anymore, please unsubscribe.  When you unsubscribe from the list, definetely no e-mail will be sent to you after that.

[paper] ML based Aging-Aware FPGA Framework

Behnam Ghavami, Milad Ibrahimipour, Zhenman Fang, Lesley Shannon 

MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework

31st International Conference on Field-Programmable Logic and Applications

(FPL 2021 Short Paper),

Virtual Conference, Sept 2021

*Simon Fraser University, Burnaby, BC, Canada

Abstract: In this paper, we develop a framework called MAPLE to enable the aging-aware FPGA architecture exploration. The core idea is to efficiently model the aging-induced delay degradation at the coarse-grained FPGA basic block level using deep neural networks (DNNs). For each type of the FPGA basic block such as LUT and DSP, we first characterize its accurate delay degradation via transistor-level SPICE simulation under a versatile set of aging factors from the FPGA fabric and in-field operation. Then we train one DNN model for each block type to quickly and accurately predict the complex relation between its delay degradation and comprehensive aging factors. Moreover, we integrate our DNN models into the widely used Verilog-to-Routing toolflow (VTR 8) to support analyzing the impact of aging-induced delay degradation on the entire large scale FPGA architecture. Experimental results demonstrate that MAPLE can predict the delay degradation of FPGA blocks 104 to 107 times faster than transistor-level SPICE simulation, with a prediction error less than 0.7%. Our case study demonstrates that FPGA architects can effectively leverage MAPLE to explore better aging-aware FPGA architectures.

Fig: Overview of FPGA fabric and in-field factors affecting FPGA aging at transistor and basic block levels. We use DNNs to model FPGA delay degradation at basic block level.

Acknowledgements: We acknowledge the support from Government of Canada Technology Demonstration Program and MDA Systems Ltd; NSERC Discovery Grant RGPIN-2019-04613 and DGECR 2019-00120; Canada Foundation for Innovation John R. Evans Leaders Fund; Simon Fraser University New Faculty Start-up Grant; Xilinx, Huawei and Nvidia.

SK hynix Starts Mass Production of #1anm DRAM

SK hynix Starts Mass Production of #1anm (4th generation of the #10nm technology) DRAM Using EUV Equipment https://t.co/Rpz7USr1C3 #semi https://t.co/4ikAq8tEvi

— Wladek Grabinski (@wladek60) Jul 12, 2021

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July 12, 2021 at 11:34PM
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From Garage to Tech Giant

From Garage to Tech Giant: Bill #Hewlett and #David Packard Ignited the Tech World [by Tyler Charboneau] https://t.co/2gWMlHaReJ #semi https://t.co/AwdT3Gig6n

— Wladek Grabinski (@wladek60) Jul 12, 2021

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July 12, 2021 at 11:38PM
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[PhD] Cryogenic MOSFET Modeling

Cryogenic MOSFET Modeling for Large-Scale Quantum Computing

Arnout Lodewijk M BECKERS

Thèse n° 8365 2021

DOI: 10.5075/epfl-thesis-8365

Présentée le 28 mai 2021

Faculté des sciences et techniques de l’ingénieur Laboratoire de circuits intégrés Programme doctoral en génie électrique

pour l’obtention du grade de Docteur ès Sciences par

Arnout Lodewijk M BECKERS

Acceptée sur proposition du jury:

Prof. E. Charbon, président du jury
Prof. C. Enz, directeur de thèse
Prof. B. Parvais, rapporteur
Prof. G. Ghibaudo, rapporteur
Dr J.-M. Sallese, rapporteur 

Abstract: Promising results of state-of-the-art quantum computers fuel a world-wide effort in academic and private research laboratories to scale up the number of qubits and improve their characteristics in large arrays. To meet the scale-up challenge, innovative microelectronic architectures are envisioned hosting qubits and transistors in silicon. Integrated-circuit design for deep-cryogenic temperatures (below 10 K or -263.15°C) is a challenging optimization exercise that currently leads to costly iterations due to the lack of physics-based transistor models for these temperatures. Proposed enhancements to the industry-standard transistor models neglect the low-temperature physics and do not suffice for a large-volume application. This PhD thesis pushes the state-of-the-art of the characterization, physics, and modeling of CMOS (Complementary Metal Oxide Semiconductor) transistors down to deep-cryogenic temperatures. The most advanced commercial bulk CMOS technology (28-nm minimum gate length) is measured down to 4.2 K using dip-stick measurements and probe-station measurements. The temperature behavior of the physical parameters and the analog figures-of-merit is reported. A similar characterization study is presented for a 28-nm FDSOI CMOS technology using measurements provided by CEA-Léti through the EU H2020 MOS-Quito Project. It is shown that the design methodology based on the transconductance efficiency remains valid down to 4.2 K for both advanced CMOS processes. These results are already supporting the community: qubit controllers in 28-nm bulk and FDSOI technologies have been successfully deployed in the cryostats of quantum computers by Google and CEA-Léti, respectively. Industry-standard models have been honed over many years for near room-temperature operation. They show the largest discrepancies in the sub- and near-threshold regimes when used at deep-cryogenic temperatures. Therefore, this thesis presents an in-depth study of these regimes. Generalized Boltzmann relations are derived including band tails, which are valid in subthreshold. Using these relations, a new analytical theory is derived for the subthreshold swing that rolls off from the Boltzmann limit, showing that an ideal step-like switch cannot be obtained in the 0-K limit due to shallow band-edge states. The process quality must be improved to operate devices closer to the Boltzmann limit. Moreover, the transconductance efficiency in weak inversion (subthreshold) follows the new theoretical limit instead of the Boltzmann temperature limit. This mitigates the expected current savings from biasing in weak inversion. The new theory also explains the impossible inverse temperature dependence of the subthreshold-slope factor, which has been extracted in numerous characterizations in the literature. Furthermore, a threshold-voltage model for bulk CMOS is presented including dopant freezeout and interface traps. Process engineers can benefit from this model to customize transistors for use at 4.2 K. Finally, the discrepancy of the transfer characteristics in moderate inversion (near-threshold) is modeled with an improved representation of the localized band-edge states. As such, this PhD thesis lays the groundwork for next-generation deep-cryogenic IC design benefiting from physics-based knowledge. While this thesis is oriented toward quantum computing, the results also apply to other deep-cryogenic applications at the forefront of science and engineering.

Fig: Different explanations have been proposed for the deviation of the subthreshold swing (SS) from the Boltzmann limit at deep-cryogenic temperatures (below a critical temperature Tc). This led to the introduction of band-edge states to explain SS(T)

How to double research citations?

 

https://www.psypost.org/2021/07/the-sci-hub-effect-can-almost-double-the-citations-of-research-articles-study-suggests-61425

[RsyPost] For their study, the researchers examined 8,661 scientific articles published in three multidisciplinary journals (Nature, Science, and Proceedings of the National Academy of Sciences), three economic journals (The Quarterly Journal of Economics, Journal of Political Economy, and Econometrica), three consumer research journals (Journal of Consumer Research, Journal of Retailing and Consumer Services, and Journal of Consumer Psychology), and three neuroscience journals (Nature Reviews Neuroscience, Nature Neuroscience, and Neuron).

The articles were published between September 2015 and February 2016. About half of them had been downloaded from Sci-Hub, while the other half had never been downloaded from the website.

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PsyPost is an independently-owned psychology and neuroscience news website dedicated to reporting the latest research on human behavior, cognition, and society. The publication covers the latest discoveries in psychology, psychiatry, neuroscience, sociology, and similar fields.

#OpenPOWER Foundation | #Libre-SOC #180nm Power ISA ASIC Submitted to Imec for Fabrication https://t.co/S4K6p9gFcb #semi https://t.co/2yDUzjKJqN

#OpenPOWER Foundation | #Libre-SOC #180nm Power ISA ASIC Submitted to Imec for Fabrication https://t.co/S4K6p9gFcb #semi https://t.co/2yDUzjKJqN

— Wladek Grabinski (@wladek60) Jul 8, 2021

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July 09, 2021 at 12:22AM
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[paper] eSim: An Open Source EDA Tool

Rahul Paknikar, Saurabh Bansode, Gloria Nandihal, Madhav P. Desai, Kannan M. Moudgalya, 

and Ashutosh Jha*

eSim: An Open Source EDA Tool for Mixed-Signal and Microcontroller Simulations

4th International Conference on Circuits, Systems and Simulation

(ICCSS), 2021, pp. 212-217,

DOI: 10.1109/ICCSS51193.2021.9464198.

Indian Institute of Technology Bombay, Mumbai, Maharashtra, India
* Vellore Institute of Technology Chennai, Tamil Nadu, India

Abstract: The ability to carry out simulations before making a PCB can save a lot of time, effort and cost. This work explains the creation of an open source mixed-signal simulation software eSim that will be of great help to students, hobbyists, the SME sector and startups. Analog and digital components are respectively modelled using SPICE and a hardware descriptive language in eSim. Inclusion of AVR based microcontroller as a part of the digital circuit is demonstrated through its instructions implemented as a C code library. This methodology could be used to provide support to other microcontroller families, such as PIC, STM and also more sophisticated controllers. These concepts are demonstrated through a few examples.

Fig: Workflow of NGHDL

Acknowledgment: The authors would like to thank Prof. Pramod Murali, Department of Electrical Engineering, IIT Bombay and Mrs. Usha Viswanathan, FOSSEE, IIT Bombay for their guidance. We would also like to express our gratitude towards Powai Labs Technology Private Limited for their gratis contribution to the VHPIDIRECT package and Utility package of NGHDL. The FOSSEE project is funded by the National Mission on Education through ICT, Ministry of Education, Govt. of India.

Special Issue on the 60th anniversary of the first laser

Special Issue on the 60th anniversary of the first laser Series I: Microcavity Photonics—from fundamentals to applications https://t.co/I9pRWzuxsQ #semi https://t.co/qW7HP2vfXd

— Wladek Grabinski (@wladek60) Jul 8, 2021

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from Twitter https://twitter.com/wladek60

July 08, 2021 at 03:39PM
via IFTTT

JFETLAB: simulate Si and 4H-SiC lDG JFET

JFETLAB, has been updated to v1.2, supporting DC/CV simulations of Si and 4H-SiC lDG JFET; the mobility and intrinsic concentration doping/temperature and temperature dependence are incorporate, respectively. Gm/Id simulations are also included. https://t.co/C7RK06oWhD #semi https://t.co/hiW6NswqPP

— Wladek Grabinski (@wladek60) Jul 8, 2021

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from Twitter https://twitter.com/wladek60

July 08, 2021 at 01:50PM
via IFTTT

[paper] Anti-ferroelectric/Ferroelectric Stack NC FinFET

Shih-En Huang¹, Student Member, IEEE, Pin Su¹, Member, IEEE, 

and Chenming Hu^1,2, Life Fellow, IEEE

S-curve Engineering for ON-state Performance 

using Anti-ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

2021 - techrxiv.org

1 Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University,  Hsinchu 30010, Taiwan  

2 Department of Electrical Engineering and Computer Science, University of California at Berkeley

Abstract: This work investigates the S-curve engineering by exploiting the anti-ferroelectric (AFE)/ferroelectric (FE) stack negative-capacitance FinFET (NC-FinFET) to improve both the subthreshold swing and ON-state current (ION). The capacitance matching and ON-state performance are evaluated by using a short-channel AFE/FE stack NC-FinFET model. Our study indicates that the AFE/FE gate-stack can theoretically achieve surprising improvements to the OFF-state current (IOFF) and ION relative to IRDS projections. There is significant long-term advantage to IC power consumption and speed if materials with certain AFE and FE characteristics can be developed and introduced into IC manufacturing.

Fig: (a) Equivalent capacitance network of the AFE/FE stack NC-FinFET. The Cafe, Cfe and Cint are the anti-ferroelectric capacitance, ferroelectric capacitance and the internal capacitance, respectively. (b) Capacitance matching comparison at source end shows that the AFE/FE stack improves the high AV region toward high VGS. 

Acknowledgment: The authors would like to thank anonymous referees for critical reading of the manuscript and valuable feedback. This work was supported in part by “Center for the Semiconductor Technology Research” from The Featured Areas Research Center Program within the framework of the Higher Education Sprout Project by the Ministry of Education (MOE), Taiwan, and in part by the Ministry of Science and Technology, Taiwan, under contracts 110-2634-F-009-027 and 110-2218-E-A49-014-MBK.

[paper] A Compact Model of Gate Capacitance in Ballistic GAA-CNFET

A. Dixit, N. Gupta

A Compact Model of Gate Capacitance 

in Ballistic Gate-all-around Carbon Nanotube Field Effect Transistors 

IJE TRANSACTIONS A: Basics Vol. 34, No. 7, (July 2021) 1718-1724 

DOI: 10.5829/ije.2021.34.07a.16

* Nanomaterial Device Laboratory, Department of Electrical and Electronics Engineering,
Birla Institute of Technology and Science, Pilani, Rajasthan, India

Abstract: This paper presents a one-dimensional analytical model for calculating gate capacitance in Gate-All-Around Carbon Nanotube Field Effect Transistor (GAA-CNFET) using electrostatic approach. The proposed model is inspired by the fact that quantum capacitance appears for the Carbon Nanotube (CNT) which has a low density of states. The gate capacitance is a series combination of dielectric capacitance and quantum capacitance. The model so obtained depends on the density of states (DOS), surface potential of CNT, gate voltage and diameter of CNT. The quantum capacitance obtained using developed analytical model is 2.84 pF/cm for (19, 0) CNT, which is very close to the reported value 2.54 pF/cm. While, the gate capacitance comes out to be 24.3×10-2 pF/cm. Further, the effects of dielectric thickness and diameter of CNT on the gate capacitance are also analyzed. It was found that as we reduce the thickness of dielectric layer, the gate capacitance increases very marginally, which provides better gate control upon the channel. The close match between the calculated and simulated results confirms the validity of the proposed model.

Fig. Schematic view of CNFET for modelling gate capacitance (a) front view (b) side view

Acknowledgements: Authors acknowledge the financial support of Defence Research and Development Organisation (DRDO), Govt. of India [ERIP/ER/DGMED&OS/990416502/ M/01/1657] and Nanomaterial device laboratory, BITS Pilani for carrying research out work reported this paper.

[paper] Nanosheet FETs

Girija Nandan Ka

Nanosheet FETs

figshare: Silicon on Insulator and Advanced MOSFET based Structures, 

17-Jan-2021 DOI: 10.6084/m9.figshare.13600961.v1.

Abstract: The modern microprocessor is one of the world’s most advanced systems, but at the core of this device it is, what we believe, is a transistor. At present there are billions and billions of microprocessor, and they are all somewhat identical. So improving the performance and boosting the density of these transistors is the most straightforward way to make microprocessors, and the computers they power, work better.

Fig.1 Electrochemical lithiation process for the fabrication of 2D nanosheets 

from the layered bulk material.

Fig.1 Electrochemical lithiation process for thefabrication of 2D nanosheets from the layered bulkmaterial.

[paper] Polymer/TiO2 Nanorod Nanocomposite Optical Memristor Device

A. H. Jaafar, M. M. Al Chawa, F. Cheng, S.M. Kelly, R. Picos, R. Tetzlaff, and N. T. Kemp

Polymer/TiO2 Nanorod Nanocomposite Optical Memristor Device

J. Phys. Chem. C 2021, XXXX, XXX, XXX-XXX

Publication Date: June 30, 2021

DOI: 10.1021/acs.jpcc.1c02799

Abstract: Modulation of resistive switching memory by light opens the route to new optoelectronic devices that can be controlled both optically and electronically. Applications include integrated circuits with memory elements switchable by light and neuromorphic computing with optically reconfigurable and tunable synaptic circuits. We report on a unique nanocomposite resistive switching material and device made from a low concentration (∼0.1% by mass) of titanium dioxide nanorods (TiO2-NRs) embedded within the azobenzene polymer, poly(disperse red 1 acrylate, PDR1A). The device exhibits both reversible electronic memristor switching and reversible polarization-dependent optical switching. Optical irradiation by circularly polarized light causes a trans–cis photochemical isomerization that modifies the conformation and orientation of the photoactive azo-unit within the polymer. The resulting expansion of the composite (PDR1A/TiO2-NR) polymer film modifies the conduction pathway, facilitated by the presence of the TiO2-NRs, as a semiconductor material, through the (PDR1A/TiO2-NR) polymer film, which provides a sensitive means to control resistive switching in the device. The effect is reversible by changing the polarization state of the incident light. A charge-flux memristor model successfully reproduces the current–voltage hysteresis loops and threshold switching properties of the device, as well as the effect of the illumination on the electrical characteristics.

Fig: Polymer/TiO2 Nanorod Nanocomposite Optical Memristor Device

[mos-ak] [Final Program] 5th Sino MOS-AK Workshop Xi'an (hybrid/online) August 11-13, 2021

Together with local Xidian University Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to the 5th Sino MOS-AK Workshop Xian workshop which will be Virtual/Online event. Scheduled, MOS-AK/Xian workshop, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK Workshop Program is available online: 

https://www.mos-ak.org/xian_2021/

Venue: Hybrid event at Xidian University <xidian.edu.cn>

会议场所：西安电子科技大学北校区阶梯教学楼112报告厅, 

西安市雁塔区太白南路2号西安电子科技大学（北校区）

No.2, South Taibai Road, Xian Dianzi University, Xi'an, 710071

Online Registration is open

Workshop Secretary: Meng Zhang Mobile:13619295980

any related enquiries can be sent to registration@mos-ak.org

Post-workshop publications, selected, the best papers will be selected and recommended for further publication in the renowned journal such as Weily's International Journal of Microwave and Optical Technology Letters special issue.

-- Min Zhang; XMOD Technologies (CN) 

-- W.Grabinski; MOS-AK (EU)

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Enabling Compact Modeling R&D Exchange

www.mos-ak.org

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WG050721

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[papers] Compact/SPICE Modeling

[1] M. S. Tarkov; Two-Gate FeFET SPICE Model and Its Application to Construction of Adaptive Adder; 2021 Ural Symposium on Biomedical Engineering, Radioelectronics and Information Technology (USBEREIT), 2021, pp. 0206-0209,
DOI: 10.1109/USBEREIT51232.2021.9455091.

[2] L. Liu, Y. Tian and W. Huang, "A Bio-IA with Fast Recovery and Constant Bandwidth for Wearable Bio-Sensors," in IEEE Sensors Journal,
DOI: 10.1109/JSEN.2021.3092001.

[3] C. -T. Tung, H. -Y. Lin, S. -W. Chang and C. -H. Wu, "Analytical modeling of tunnel-junction transistor lasers," in IEEE Journal of Selected Topics in Quantum Electronics,
DOI: 10.1109/JSTQE.2021.3090527.

[4] Subir Kumar Maity, Soumya Pandit; A SPICE compatible physics-based intrinsic charge and capacitance model of InAs-OI-Si MOS transistor, Superlattices and Microstructures, Volume 156, 2021, 106975, ISSN 0749-6036,
DOI: 10.1016/j.spmi.2021.106975

Fig:  Strucutre of InAs-OI-Si MOS transistor

[paper] 20 Years of Reconfigurable Field-Effect Transistors

T. Mikolajick^1,2, G. Galderisi¹, M. Simon¹, S. Rai³, A. Heinzig², A. Kumar³, 

W.M. Weber⁴, J. Trommer¹

20 Years of Reconfigurable Field-Effect Transistors: From Concepts to Future Applications 

22th Conference on Insulating Films on Semiconductors 

INFOS2021

28 June-2 July 2021, Rende, Italy

1 NaMLab GmbH, Nöthnitzer Str. 64a, Dresden, Germany
2 Chair of Nanoelectronics, TU Dresden, Germany
3 Chair of Processor Design, TU Dresden, Dresden, Germany
4 Chair of Nanoelectronics, TU Wien, Vienna, Austria

Outline

• Introduction
• The Reconfigurable Field Effect Transistor
• Early Phase
• Device Outgrowth
• Functional Diversification
• Summary and Outlook