[paper] DC, LF noise and TID mechanisms in 16nm FinFETs

Stefano Bonaldo^ab, Teng Ma^ab, Serena Mattiazzo^bc, Andrea Baschirotto^de, Christian Enz^f, Daniel M.Fleetwood^g, Alessandro Paccagnella^ab, Simone Gerardin^ab

DC response, low-frequency noise, and TID-induced mechanisms in 16-nm FinFETs for high-energy physics experiments

J. NIMA Section A; available online 18 April 2022, 166727

DOI: j.nima.2022.166727

     
a University of Padova (I)
b INFN Padova (I)
c University of Padova (I)
d INFN Milano (I)
e University of Milano Bicocca (I)
f ICLab, EPFL, Lausanne (CH)
g Vanderbilt University, Nashville (USA)

Abstract: Total-ionizing-dose (TID) mechanisms are evaluated in 16nm Si bulk FinFETs at doses up to 1 Grad (SiO₂) for applications in high-energy physics experiments. The TID effects are evaluated through DC and low-frequency noise measurements by varying irradiation bias conditions, transistor channel lengths, and fin/finger layouts. The TID response of nFinFETs irradiated under positive gate bias at ultrahigh doses shows a rebound of threshold voltage with significant increase in the 1/f noise amplitude. The degradation is related to the generation of border and interface traps at the upper corners of STI oxides and at the gate oxide/channel interfaces. In contrast, pFinFETs have the worst degradation due to positive charge trapping in STI oxides, which severely degrades the device transconductance and total drain current, while negligible effects are visible in the threshold voltage and 1/f noise. The TID sensitivity depends strongly on the transistor layout. Short-channel devices have the best TID tolerance thanks to the influence of halo implantation, while pFinFETs designed with low number of fins have the worst degradation because of high densities of positive charge in the surrounding thick STI oxides. As a guideline for IC design, short-channel transistors with more than 4-fins may be preferred in order to facilitate circuit qualification.

Fig: Low-frequency noise measured at |Vds|=50mV and |Vgs|=0.85V at room temperature for pFinFET with Nfin=2 and L=16 nm, irradiated up to 1Grad (SiO2) in the ON condition

Acknowledgment: This work has been carried out within the FinFET16v2 experiment funded by the National Institute for Nuclear Physics - INFN, Italy.

8th EuroSOI-ULIS 2022 at University of Udine (Italy)

Organized by: University of Udine (Italy) Conference chair: Pierpaolo Palestri Local organizing Committee: Francesco Driussi David Esseni Daniel Lizzit Conference Secretariat: Centro Congressi Internazionali  Steering Committee: Francis BALESTRA (IMEP Minatec, France) Maryline BAWEDIN (IMEP-LAHC, France) Cor CLAEYS (KU-Leuven, Belgium) Bogdan CRETU (ENSICAEN, France) Sorin CRISTOLOVEANU (IMEP-LAHC, France) Francisco GAMIZ (UnivGranada, Spain) Elena GNANI (Univ. of Bologna, Italy) Benjamin INIGUEZ  (URV, Spain) Joris LACORD (CEA-Leti, France) Enrico SANGIORGI (Univ.Bologna, Italy) Luca SELMI (Univ. of Modena, Italy) Viktor SVERDLOV (TU Wien, Austria) Andrei VLADIMIRESCU (ISEP, France) Sponsors:

8th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS) 2022 May 18-20, 2022 – Udine, Italy https://eurosoiulis2022.com The Conference aims at gathering together scientists and engineers working in academia, research centers and industry in the field of SOI technology and nanoscale devices in More-Moore and More-Than-Moore scenarios. High quality contributions in the following areas are solicited: Advanced SOI materials and structures, innovative SOI-like devices. Alternative transistor architectures (FDSOI, Nanowire, FinFET, MuGFET, vertical MOSFET, FeFET and TFET, MEMS/NEMS, Beyond-CMOS). New channel materials for CMOS (strained Si/Ge, III-V, carbon nanotubes; graphene and other 2D materials). Properties of ultra-thin semiconductor films and buried oxides, defects, interface quality; thin gate dielectrics: high-κ and ferroelectric materials for switches and memory. New functionalities and innovative devices in the More than Moore domain: nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, integrated photonics (on SOI), etc. Transport phenomena, compact modeling, device simulation, front- and back-end process simulation. CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling; three-dimensional integration of devices and circuits, heterogeneous integration. Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices. Original 2-page abstracts with illustrations will be reviewed by the Scientific Committee. The accepted contributions will be published as 4-page letters in a special issue of the Elsevier journal Solid-State Electronics. Extended versions of outstanding papers will be published in a further special issue of Solid-State Electronics. A best poster award will be attributed by ELSEVIER.  The “Androula Nassiopoulou Best Paper Award" will be attributed by the SINANO institute. Important dates: abstract submission deadline: March 1, 2022 notification of acceptance: March 15, 2022

[paper] Systematic approach for IG-FinFET amplifier design using gm/Id method

Alireza Hassanzadeh and Sajad Hadidi

Systematic approach for IG-FinFET amplifier design using gm/Id method

Analog Integrated Circuits and Signal Processing (2021)

https://doi.org/10.1007/s10470-021-01917-9

EE Department, Shahid Beheshti University, Tehran, Iran

Abstract: In this paper, a systematic approach has been used to apply gm/Id method for the design of Independent Gate (IG) FinFET amplifiers. The design of high-performance amplifiers using gm/Id method has been successfully applied to nanometer devices. IG-FinFETs have been widely used in digital circuit implementations. However, the application of IG-FinFETs in analog circuits is limited and brings many advantages including low power, low voltage operation of transistors. Independent gates of FinFET can receive different voltages that facilitate low voltage operation of the circuit. Simulation-based gm/Id method has been applied to IG-FinFET transistors and a systematic methodology has been developed for the design of IG-FinFET amplifiers. The Berkeley BSIM-IMG 55 nm technology parameters have been used for HSPICE simulations. The designed amplifier has a DC gain of about 45 dB while consuming 6.5 µW from a single 1 V power supply.

Fig: gm/Id vs. normalized Id(Vbg)

[paper] 11.8 GHz Fin Resonant Body Transistor

Analysis and Modeling of an 11.8 GHz Fin Resonant Body Transistor 

in a 14nm FinFET CMOS Process 

Udit Rawat, Student Member, IEEE, Bichoy Bahr*, Member, IEEE, 

and Dana Weinstein, Senior Member, IEEE

arXiv:2107.04502v1 [physics.app-ph] 9 Jul 2021

 

Department of Electrical Engineering, Purdue University, West Lafayette USA

*Kilby Labs - Texas Instruments, Dallas, TX, USA.

Abstract: In this work, a compact model is presented for a 14 nm CMOS-based FinFET Resonant Body Transistor (fRBT) operating at a frequency of 11.8 GHz and targeting RF frequency generation/filtering for next generation radio communication, clocking, and sensing applications. Analysis of the phononic dispersion characteristics of the device, which informs the model development, shows the presence of polarization exchange due to the periodic nature of the back-end-of-line (BEOL) metal PnC. An eigenfrequency-based extraction process, applicable to resonators based on electrostatic force transduction, has been used to model the resonance cavity. Augmented forms of the BSIM-CMG (Common Multi-Gate) model for FinFETs are used to model the drive and sense transistors in the fRBT. This model framework allows easy integration with the foundry-supplied process design kits (PDKs) and circuit simulators while being flexible towards change in transduction mechanisms and device architecture. Ultimately, the behaviour is validated against RF measured data for the fabricated fRBT device under different operating conditions, leading to the demonstration of the first complete model for this class of resonant device integrated seamlessly in the CMOS stack.

Fig: Complete 3D FEM Simulation model depicting two adjoining fRBT unit cells. Mx (x=1-3) and Cy (y=4-6) represent the first 6 metal levels that form a part of the BEOL PnC.

Acknowledgement: This work was supported in part by the DARPA MIDAS Program.

 

[paper] Anti-ferroelectric/Ferroelectric Stack NC FinFET

Shih-En Huang¹, Student Member, IEEE, Pin Su¹, Member, IEEE, 

and Chenming Hu^1,2, Life Fellow, IEEE

S-curve Engineering for ON-state Performance 

using Anti-ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

2021 - techrxiv.org

1 Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University,  Hsinchu 30010, Taiwan  

2 Department of Electrical Engineering and Computer Science, University of California at Berkeley

Abstract: This work investigates the S-curve engineering by exploiting the anti-ferroelectric (AFE)/ferroelectric (FE) stack negative-capacitance FinFET (NC-FinFET) to improve both the subthreshold swing and ON-state current (ION). The capacitance matching and ON-state performance are evaluated by using a short-channel AFE/FE stack NC-FinFET model. Our study indicates that the AFE/FE gate-stack can theoretically achieve surprising improvements to the OFF-state current (IOFF) and ION relative to IRDS projections. There is significant long-term advantage to IC power consumption and speed if materials with certain AFE and FE characteristics can be developed and introduced into IC manufacturing.

Fig: (a) Equivalent capacitance network of the AFE/FE stack NC-FinFET. The Cafe, Cfe and Cint are the anti-ferroelectric capacitance, ferroelectric capacitance and the internal capacitance, respectively. (b) Capacitance matching comparison at source end shows that the AFE/FE stack improves the high AV region toward high VGS. 

Acknowledgment: The authors would like to thank anonymous referees for critical reading of the manuscript and valuable feedback. This work was supported in part by “Center for the Semiconductor Technology Research” from The Featured Areas Research Center Program within the framework of the Higher Education Sprout Project by the Ministry of Education (MOE), Taiwan, and in part by the Ministry of Science and Technology, Taiwan, under contracts 110-2634-F-009-027 and 110-2218-E-A49-014-MBK.

[paper] Nanosheet field effect transistors

J. Ajayan^a, D. Nirmal^b, Shubham Tayal^a, Sandip Bhattacharya^a, L. Arivazhagan^c, A.S. Augustine Fletcher^b, P. Murugapandiyan^d, D. Ajitha^e

Nanosheet field effect transistors - A next generation device to keep Moore’s law alive:
An intensive study

Microelectronics Journal 114 (2021) 105141

DOI: 10.1016/j.mejo.2021.105141

a SR University, Warangal, Telangana, India
b Karunya Institute of Technology and Sciences, Coimbatore, Tamilnadu, India
c Sri Ramakrishna Engineering College, Coimbatore, Tamilnadu, India
d Anil Neerukonda Institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India
e Sreenidhi Institute of Science and Technology, Hyderabad, Telangana, India

Abstract: Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects (SCEs) and self-heating effects (SHEs) which limits their performance and causes reliability issues. FinFET technology has resulted in a remarkable performance up to a feature size of 7nm. The research community is expecting that GAA NW-FETs will take over FinFET technology from 7nm to 5nm. However, further shrinking of feature size to 3nm will impose severe challenges to the performance of these aforesaid multi-gate devices. Subsequently, the electron device designer community needs to look for alternative device designs like nanosheet FETs (NS-FETs) to overcome the limitations of the FinFET and GAA NW-FETs technologies. The driving force behind the emergence of these NS-FETs is their ability to scale down even below a feature size of 5nm with negligible short channel effects. Therefore, in this review article we have intensively investigated the NS-FETs in terms of impact of geometrical scaling, substrate material effects, parasitic channel effects, thermal effects, compatibility with different metal gates, and source/drain (S/D) metal depth effect. Consequently, it can be concluded that vertically stacked NS-FET is the most promising solution for future digital/analog integrated circuit applications due to their outstanding capability to keep Moore’s Law alive.

Fig: 3-D views of (a) FinFET (b) stacked NW-FET (c) vertically stacked NSFET.

[Review] Nanosheet Transistors Technology

Firas N. A. Hassan Agha¹, Yasir H. Naif², Mohammed N. Shakib³

Review of Nanosheet Transistors Technology

Tikrit Journal of Engineering Sciences (2021) 28 (1): 40-48

ISSN: 1813-162X (Print) ; 2312-7589 (Online)

DOI: http://doi.org/10.25 30/tjes.28.1.05

available online at: http://www.tj-es.com

1Electrical Department/ Engineering College; Mosul University; Mosul, Iraq
2Department of Computer Engineering; Faculty of Engineering, Tishk; International University; Erbil, Iraq
3Faculty of Electrical and Electronics; Engineering Technology, University; Malaysia Pahang; Pekan, Malaysia

Abstract: Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nano-dimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).

Fig: Development of Field Effect Transistor from FinFET to MBCFET [Credit: Samsung]

Acknowledgment: The authors would like to thank University of Mosul for their support.

[webinar] "More Moore Roadmap" by IRDS and SINANO

IEEE EDS France, IRDS and the SINANO Institute will organize a Webinar 

"More Moore Roadmap"

by Mustafa Badaroglu 

IRDS-IFT More Moore Leader

The webinar will be held on 8th April 2021 at 16:00 Paris time. Interest participants please register via IEEE vTools by the following link: https://events.vtools.ieee.org/event/register/267103

Other Webinars of the IRDS Chapters will be announced in the EDS Newsletters

[paper] Process Induced Vt Variability

Mandar S. Bhoir, Member, IEEE, Thomas Chiarella, Jerome Mitard, Naoto Horiguchi, Member, IEEE, and Nihar Ranjan Mohapatra, Senior Member, IEEE

Vt Extraction Methodologies Influence Process Induced Vt Variability:

Does This Fact Still Hold for Advanced Technology Nodes? 

IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4691-4695, Nov. 2020

DOI: 10.1109/TED.2020.3025750.

Abstract: In this work, we have investigated the influence of Vt extraction procedure on overall Vt variability of sub-10 nm Wfin FinFETs. Using six different Vt extraction techniques (These are 1) constant current (CC) technique, 2) extrapolation in linear regime [ELR, also known as maximum trans-conductance (gm)] technique, 3) trans-conductance extrapolation (TCE) technique, 4) second-derivative (SD) technique, 5) ratio method (RM); and 6) transition method (TM) [1]) we have experimentally demonstrated that the Vt variability is independent of Vt extraction procedure (unlike reported earlier). Furthermore, through systematic evaluation on commonly used Vt extraction techniques, the physics behind this anomalous behavior is investigated. It is shown that the significant variation in metal gate work-function and gate dielectric charges in advanced CMOS nodes is mainly responsible for this behavior. This claim is further validated for FinFETs with deeply scaled fin-width and effective oxide thickness (EOT).

Fig: (a) Schematic illustration of different process-variability sources in FinFET; 

(b)Transfer characteristics for FinFETs with similar Vt, CC but different RSD.

These FinFETs have different Vt, ELR because of RSD induced gm, max variations

Acknowleegement: This work was supported in part by the Visvesvaraya Ph.D. Scheme, MeitY, Government of India MEITY-PHD-250 and in part by the Horizon 2020 ASCENT EU Project (Access to European Nanoelectronics Network) under Project 654384.

References:
[1] A. Ortiz-Conde, F. G. Sánche, J. J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, “A review of recent MOSFET threshold voltage extraction methods,” Microelectron. Rel., vol. 42, no. 4, pp. 583—596, 2002, doi: 10.1016/S0026-2714(02)00027-6

[paper] Ge Twin-Transistor NVM with FinFET Structure

Siao-Cheng Yan, Chong-Jhe Sun, Meng-Ju Tsai (Student Member, Ieee), Lun-Chun Chen,

Mu-Shih Yeh (Member, IEEE), Chien-Chang Li, Yao-Jen Lee and Yung-Chun Wu (Member, IEEE)

Germanium Twin-Transistor Nonvolatile Memory with FinFET Structure

IEEE J-EDS vol. 8, pp. 589-593, 2020

DOI: 10.1109/JEDS.2020.2999616

Abstract: Germanium is a promising alternative material for use in advanced technology nodes because it exhibits symmetrical mobility of holes and electrons. Embedded nonvolatile memory (NVM) is essential in electronic devices with integrated circuit (IC) technology, including future Ge-based technology. In this paper, we demonstrate Ge twin-transistor NVM with a fin field-effect transistor (FinFET) structure. This Ge twin-transistor NVM exhibits high programming and erasing speeds and satisfactory reliability. Moreover, the masks and fabrication process of this Ge twin-transistor NVM are identical to those of Ge-channel FinFETs. Thus, Ge twin-transistor NVM is a promising candidate for embedded NVM applications in future high-performance Ge complementary metal–oxide–semiconductor technology (CMOS).

FIG:  (a) Schematic top view of the Ge Twin NVM with one fin,

and (b) process flow of the Ge Twin NVM

Acknowledgements: This work was supported in part by Ministry of Science and Technology, Taiwan, under contract MOST 108-2221-E-007-003, and in part by Taiwan Semiconductor Research Institute, Taiwan.

[paper] Compact Modeling of Parasitic FET capacitance

Sharma, S. M., Singh, A., Dasgupta, S., & Kartikeyan, M. V. 

A review on the compact modeling of parasitic capacitance: 

from basic to advanced FETs. 

Journal of Computational Electronics

DOI: 10.1007/s10825-020-01515-4

Abstract: This paper presents a review on the development of parasitic-capacitance modeling for metal–oxide–semiconductor feldefect transistors (MOSFETs), covering models developed for the simple parallel-plate capacitance and the nonplanar and coplanar plate capacitances required for the intrinsic and extrinsic part of such devices. A comparative study of various extrinsic capacitance models with respect to a reference model is used to analyze the benefts of the various approaches. Capacitance models for basic MOSFETs and advance multigate FETs with two-dimensional (2D) and three-dimensional (3D) structures are reviewed. It is found that the elliptical feld lines between the gate electrodes and source/drain region are modeled very well, while deviations of ±2% in the orthogonal plate capacitance are observed when the gate electrode thickness is varied from 5 to 20nm.

Fig: The 3D structure of a FinFET

Acknowledgements: The authors would like to thank the Department of Electronics and Communication Engineering, IIT Roorkee, for their valuable support in carrying out this research work.

[paper] Analog/RF Tri-metal Gate FinFET

N. G. P, S. Routray and K. P. Pradhan

Assessment of Analog/RF performances for 10 nm Tri-metal Gate FinFET

2020 4th IEEE EDTM; 2020, pp. 1-4

Penang, Malaysia

DOI: 10.1109/EDTM47692.2020.9117846

Abstract: Reduction in parasitic capacitance and resistance in FinFET is quite necessary in order to achieve high performance. In this paper, an intensive study on structural advancement in three different ways is implemented in basic FinFET structure such as (a) addition of thin silicide layer as interfacial layer between the contact and source/drain (b) extended and elevated source/drain (c) addition of hybrid spacer. Additionally, comparative study on the analog and RF performance is performed and analyzed for this structure between single material gate (SMG) and tri material gate (TMG) FinFET with all above enhancements. The analog parameters that have been analyzed are transconductance (gm), transconductance generation factor (TGF), output conductance (gd), and intrinsic gain (gm/gd). Similarly, the RF parameters like gate capacitance (CGG), cut-off frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP), and gain transconductance frequency product (GTFP) are reported. Even though there is a degradation in the mobility for the TMG FinFET, but on a whole provides better performance. Furthermore, the effect of temperature on the drain current and transconductance has been shown for the TMG structure by varying the temperature from 200 to 350K with intervals of 50K which would be the extension to this paper. Analysis gives a potential overview on different structural improvement in order to achieve higher performance.

Fig. I. Top view of the proposed FinFET structure

Fig. II. (a) Gate capacitance (b) cutoff frequency (c) intrinsic delay (d) TFP (e) GFP (f) GTFP plots by variation of gate material.

[paper] Device Scaling for 3-nm Node and Beyond

Opportunities in Device Scaling for 3-nm Node and Beyond:

FinFET Versus GAA-FET Versus UFET

U. K. Das and T. K. Bhattacharyya

in IEEE TED, vol. 67, no. 6, pp. 2633-2638, June 2020, 

doi: 10.1109/TED.2020.2987139

Abstract: The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet, and U-shaped FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To accommodate a contacted gate pitch (CGP) of 32 nm and below, the gate length is scaled down to 14 nm and beyond. While going from 5-nm node (N5) to 3-nm node (N3) dimensions, the GAA-lateral nanosheet (LNS) shows 8% reduction in the effective drain current (I_eff) due to an enormous rise in short channel effects, such as subthreshold slope (SS) and drain-induced barrier lowering (DIBL). On the other hand, 5-nm diameter-based lateral nanowire shows an 80% rise in I_eff. Therefore, to enable future devices, we explored electrostatics and I_eff in FinFET, GAA-FET, and UFET architectures at a scaled dimension. The performances of both Si- and SiGe-based transistors are compared using an advanced TCAD device simulator.

Fig: Transistor architectures for future technologies. (a) FinFET device

(in {001} substrate plane, and sidewalls are in {110} planes) with crosssectional

fin channel (5 nm thin). (b) Fin is changed into a four-stacked

GAA-LNWs. (c) GAA- LNS having 20-nm width (W). (d) UFET structure.

Acknowledgment: The authors would like to thank Dr. Bidhan Pramanik, IIT Goa, India, Dr. KB Jinesh, IIST, Trivandrum, India, and Dr. Geert Eneman, IMEC, Leuven, Belgium, for their valuable technical support.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9078841&isnumber=9098120

[paper] Electrical characterization of advanced MOSFETs

Valeriya Kilchytska, Sergej Makovejev, Babak Kazemi Esfeh, Lucas Nyssens, Arka Halder,

Jean-Pierre Raskin and Denis Flandre

Electrical characterization of advanced MOSFETs towards analog and RF applications

IEEE LAEDC, San Jose, Costa Rica, 2020, 

doi: 10.1109/LAEDC49063.2020.9073536

Abstract - This invited paper reviews main approaches in the electrical characterization of advanced MOSFETs towards their target analog and RF applications. Advantages and necessity of those techniques will be demonstrated on different study cases of various advanced MOSFETs, such as FDSOI, FinFET, NW in a wide temperature range, based on our original research over the last years. 

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9073536&isnumber=9072949

Acknowledgements - This work was partially funded by Eniac “Places2Be”, Ecsel “Waytogofast”, FNRS - FRFC “Towards Highly-efficient 10 nm MOSFETs”, FP7 “Nanosil” and “Nanofunction” projects. The authors thank our colleagues from CEA-Leti, ST and Imec, and particularly, F. Andrieu, O. Faynot, T. Poiroux, S. Barraud, M. Haond, N. Planes, N. Collaert, C. Claeys, M. Jurczak, B. Parvais, R. Rooyackers, for providing UTBB FD SOI, NW and FinFET devices and valuable discussions.

[paper] Compact Device Models for FinFET and Beyond

D. D. Lu, M. V. Dunga, A. M. Niknejad, C.Bing Hu, F.-X. Liang, W.-C. Hung, J. Lee, C.-H. Hsu
and M.-H. Chiang,

Compact device models for FinFET and beyond

ArXiv, vol. abs/2005.02580, 2020

Abstract - Compact device models play a significant role in connecting device technology and circuit design. BSIM-CMG and BSIM-IMG are industry standard compact models suited for the FinFET and UTBB technologies, respectively. Its surface potential based modeling framework and symmetry preserving properties make them suitable for both analog/RF and digital design. In the era of artificial intelligence / deep learning, compact models further enhanced our ability to explore RRAM and other NVM-based neuromorphic circuits. We have demonstrated simulation of RRAM neuromorphic circuits with Verilog-A based compact model at NCKU. Further abstraction with macromodels is performed to enable larger scale machine learning simulation.

Fig: Simulation of a novel floating - gate synaptic transistor. (a) Device structure with separate negative feedback gate (nfb) for programming and synaptic gate (sg) readout. (b) Equivalent circuit diagram for compact modeling 

Acknowledgements - The authors would like to express sincere gratitude to Chip Implementation Center (CIC), Hsinchu, Taiwan for providing SPICE simulation environment for RRAM simulations.

[paper] Design Strategies for Ultralow Power 10nm FinFETs

Design Strategies for Ultralow Power 10nm FinFETs

Abhijeet Walkea^a, Garrett Schlenvogtb^b, Santosh Kurineca^a

^aDepartment of Electrical & Microelectronic Engineering, RIT, New York, USA

^bTCAD Application Engineer, Silvaco

Received 12 June 2017, Accepted 19 June 2017, Available online 20 June 2017

Abstract: In this work, new design strategies for 10nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20pA/μm< I_OFF <50pA/μm) and ultralow power (ULP) (I_OFF <20pA/μm) requirements using three dimensional (3D) TCAD simulations. The punch-through stop implant, source and drain junction placement and gate workfunction are varied in order to study the impact on the OFF-state current (I_OFF), transconductance (g_m), gate capacitance (C_gg) and intrinsic frequency (f_T). It is shown that the gate length of 20nm for the 10nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction.

[read more https://doi.org/10.1016/j.sse.2017.06.012]

[paper] Statistical model of the NBTI-induced ΔVth, ΔSS, and Δgm degradations in advanced pFinFETs

Statistical model of the NBTI induced threshold voltage, subthreshold swing, and transconductance degradations in advanced pFinFETs
J. Franco, B. Kaczer, S. Mukhopadhyay, P. Duhan, P. Weckx, Ph.J. Roussel, T. Chiarella, L.-Å. Ragnarsson, L. Trojman, N. Horiguchi, A. Spessot, D. Linten, A. Mocuta
2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2016, pp. 15.3.1-15.3.4.
DOI: 10.1109/IEDM.2016.7838422

Abstract

We study the stochastic NBTI degradation of pFinFETs, in terms of ΔVth, ΔSS, and Δgm. We extend our Defect-Centric model to describe also the SS distribution in a population of devices of any area, at any stage of product aging. A large fraction of nanoscale devices is found to show a peak g m improvement after stress. We explain this effect in terms of the interaction of individual defects with the percolative channel conduction, and we propose a statistical description of g m aging. Our Vth, SS, and gm aging models are pluggable into reliability-enabled compact models to estimate design margins for a wide variety of circuits. Selected nanoscale device characteristics resulting from 3 percolation paths, generated with the EKV model [read more...]

[Course] Advanced CMOS/FinFET Fabrication

February 6, 2017; Portland, OR, USA

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller. The question looming in everyone’s mind is “How far into the future can this continue?” Advanced CMOS/FinFET Fabrication is a 1-day course that offers detailed instruction on the processing used in a modern integrated circuit, and the processing technologies required to make them. We place special emphasis on current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.

Register for this Course

[BOOK] FinFET Modeling for IC Simulation and Design Using the BSIM-CMG Standard

 FinFET Modeling for IC Simulation and Design Using the BSIM-CMG Standard
 Yogesh Singh Chauhan, Darsen Lu, Sriramkumar Venugopalan, Sourabh Khandelwal, Juan Pablo Duarte, Navid Paydavosi, Ai Niknejad, Chenming Hu

DESCRIPTIONThis book is the first to explain FinFET modeling for IC simulation and the industry standard – BSIM-CMG - describing the rush in demand for advancing the technology from planar to 3D architecture, as now enabled by the approved industry standard. The book gives a strong foundation on the physics and operation of FinFET, details aspects of the BSIM-CMG model such as surface potential, charge and current calculations, and includes a dedicated chapter on parameter extraction procedures, providing a step-by-step approach for the efficient extraction of model parameters.

KEY FEATURES

• Learn how to do FinFET modeling using the BSIM-CMG standard from the experts
• Authored by the lead inventor and developer of FinFET, and developers of the BSIM-CMG standard model, providing an experts’ insight into the specifications of the standard
• The first book on the industry-standard FinFET model - BSIM-CMG

With this book you will learn:

• Why you should use FinFET
• The physics and operation of FinFET
• Details of the FinFET standard model (BSIM-CMG)
• Parameter extraction in BSIM-CMG
• FinFET circuit design and simulation

READ MORE:
​http://store.elsevier.com/product.jsp?isbn=9780124200319
http://www.amazon.com/FinFET-Modeling-IC-Simulation-Design/dp/0124200311
http://www.amazon.in/FinFET-Modeling-IC-Simulation-Design/dp/0124200311

Devices That You Definitely Will (and Just Might) Use: Emerging Transistor Technologies for the Near-and Long-Term

 WEDNESDAY June 04, 4:00pm - 6:00pm | Room 302 

 TRACK: EDA

 TOPIC AREA: EMERGING TECHNOLOGIES

 SPECIAL DAC SESSION 63: Devices That You Definitely Will (and Just Might) Use: Emerging Transistor Technologies for the Near-and Long-Term

Chair:  Michael Niemier; Univ. of Notre Dame, IN
Organizers:  Michael Niemier; Univ. of Notre Dame, IN
Xiaobo Sharon Hu; Univ. of Notre Dame, IN

Want to learn about the latest developments in FinFET-based processor design? What other transistor technologies might follow FinFETs and would they bring new design and modeling challenges? Come to this session to hear about both near- and long-term transistor technologies and their prospects for continuing Moore’s Law-based performance scaling trends. The session will begin with a discussion of FinFET technology; subsequent presentations will discuss tunnel transistors (TFETs) as well as other emerging FET technologies that could reenable voltage scaling. The session will conclude with a discussion of modeling efforts that consider the impact of new device technologies on von Neumann architectures as well as hybrid analog/digital circuits and architectures.

63.1 FinFET's and Their Implications for Design Now and in the Future

• Speaker: Rob Aitken; ARM Ltd., San Jose, CA
  Greg Yeric; ARM Ltd., Austin, TX
  Brian Cline; ARM Ltd., Austin, TX
  Lucian Shifren; ARM Ltd., San Jose, CA

63.2 Emerging Devices for Logic: Can a Low-Power Switch Be Fast?

• Speaker: Thomas Theis; IBM T.J. Watson Research Center, Yorktown Heights, NY

63.3 Energy Efficient Tunnel-FET Transistors for Beyond CMOS Logic

• Speaker: Uygar Avci; Intel Corp., Portland, OR
  Daniel Morris; Intel Corp., Portland, OR
  Ian Young; Intel Corp., Hillsboro, OR

63.4 Steep Slope Devices: Enabling New Architectural Paradigms

• Speaker: Vijaykrishnan Narayanan; Pennsylvania State Univ., State College, PA
  Karthik Swaminathan; Pennsylvania State Univ., State College, PA
  Huichu Liu; Pennsylvania State Univ., State College, PA
  Moon Seok Kim; Pennsylvania State Univ., State College, PA
  Xueqing Li; Pennsylvania State Univ., State College, PA
  Jack Sampson; Pennsylvania State Univ., University Park, PA

[more about the DAC Conference]