[paper] CMOS Technology for Analog Applications in High Energy Physics

Gianluca Traversi, Luigi Gaioni, Lodovico Ratti, Valerio Re and Elisa Riceputi

Characterization of a 28 nm CMOS Technology

for Analog Applications in High Energy Physics 

in IEEE Transactions on Nuclear Science

DOI: 10.1109/TNS.2024.3382348

1 INFN Pavia and Dipartimento di Ingegneria e Scienze Applicate, Uni. Bergamo, Italy
2 INFN Pavia and Dipartimento di Ingegneria Industriale e dell’Informazione, Uni. Pavia, Italy

Abstract: In the last few years, the 28 nm CMOS technology has raised interest in the High Energy Physics community for the design and implementation of readout integrated circuits for high granularity position sensitive detectors. This work is focused on the characterization of the 28 nm CMOS node with a particular focus on the analog performance. Small signal characteristics and the behavior of the white and 1/f noise components are studied as a function of the device polarity, dimensions, and bias conditions to provide guidelines for minimum noise design of front-end electronics. Comparison with data extracted from previous CMOS generations are also presented to assess the performance of the technology node under evaluation. 

Fig: Transconductance efficiency gm/ID as a function of the normalized

drain current IDL/W for NMOS (a) and PMOS (b) devices (|VDS| = 0.9 V)

Acknowledgment: The activity leading to the results presented in this paper was carried out in the framework of the Falaphel project, funded by the Italian Institute for Nuclear Physics (INFN). The authors wish to thank Prof. Massimo Manghisoni (University of Bergamo) for the valuable advice which contributed to improve this work and Dr. Stefano Bonaldo (University of Padova) for fruitful discussions on the measurement results. The authors wish to thank also Barbara Pini (INFN Torino) for the wire bonding of the chips, Emilio Meroni and Nicola Cattaneo (University of Bergamo) for the characterization activity.

[chapter] GAA Transistors

Srivastava, Shobhit, and Abhishek Acharya

Challenges and future scope of gate-all-around (GAA) transistors

in "Device Circuit Co-Design Issues in FETs"; 

Shubham Tayal et al. (Editors)

231 CRC Press, 22 Aug 2023 - Technology & Engineering

Introduction: No doubt, FinFET technology is the slogger of today's semiconductor world. But as demand for further scaling with a desire for ultra-low-power and high-speed applications results in undesired short-channel effects, a new transistor is required. This is where gate-all-around (GAA) devices come into being. The GAA structure helps to mitigate unwanted short-channel effects by enhancing channel controllability. In GAAFETS, the channel surrounds all of its sides through a high-K and interfacial oxide layer. Thanks to science and technological innovation, the GAAFET family brings together different transistors and their competitive benefits. This chapter tries to answer why and how 3D devices emerge. In addition to the limitation of FinFET (a 3D device, gate surrounded by three sides), it further talks about the scope and challenges of different competitive GAAFET members (nanowire FET, nanosheet FET, junctionless nanosheet FET, complementary PET, and forksheet FET) of the GAAFET family. It is worth mentioning that a smaller benefit of the device performance exerts a massive performance enhancement on circuit-level applications. However, the advantages of device enhancement concurrently exaggerate the limitation of devices at circuit-level applications. So, an elaborated idea of GAAFETs holding the benefits and challenges at the circuit is also discussed here.

FIG: Structural evolution of transistors from planar to 3D forksheet FET technology

[paper] Atomic-scale defects in Si/SiO2 transistors

Stephen J. Moxim1, Fedor V. Sharov1, David R. Hughart2, Gaddi S. Haase2, Colin G. McKay2, and Patrick M. Lenahan1

Atomic-scale defects generated in the early/intermediate stages of dielectric breakdown in Si/SiO2 transistors

Appl. Phys. Lett. 120, 063502 (2022);

DOI:10.1063/5.0077946

   

1 The Pennsylvania State University, USA
2 Sandia National Laboratories, New Mexico, USA

Abstract: Electrically detected magnetic resonance and near-zero-field magnetoresistance measurements were used to study atomic-scale traps generated during high-field gate stressing in Si/SiO2 MOSFETs. The defects observed are almost certainly important to time-dependent dielectric breakdown. The measurements were made with spin-dependent recombination current involving defects at and near the Si/SiO2 boundary. The interface traps observed are Pb0 and Pb1 centers, which are silicon dangling bond defects. The ratio of Pb0/Pb1 is dependent on the gate stressing polarity. Electrically detected magnetic resonance measurements also reveal generation of E′ oxide defects near the Si/SiO2 interface. Near-zero-field magnetoresistance measurements made throughout stressing reveal that the local hyperfine environment of the interface traps changes with stressing time; these changes are almost certainly due to the redistribution of hydrogen near the interface.

FIG: Atomic-scale picture of defect formation and hydrogen motion during the early and intermediate stages of SiO2 degradation and breakdown.

Acknowledgements: This work was supported by the Defense Threat Reduction Agency (DTRA) under Award No. HDTRA1-18-0012. The content of the information does not necessarily reflect the position or the policy of the federal government and no official endorsement should be inferred

[paper] Transistors Based on Lateral PtSe2 Heterostructures

Gaetano Calogero*, Damiano Marian, Enrique G. Marin**, Gianluca Fiori 

and Giuseppe Iannaccone

Physical insights on transistors based on lateral heterostructures 

of monolayer and multilayer PtSe2 via Ab initio modelling of interfaces

Sci Rep 11, 18482 (2021)

DOI: 10.1038/s41598-021-98080-y

  
Dipartimento di Ingegneria dell’Informazione, Università di Pisa  (I)
*Consiglio Nazionale delle Ricerche, Istituto per le Microelettronica e Microsistemi (I)
**Dipartimento Electronica, Facultad de Ciencias, Universidad de Granada (SP)

Abstract: Lateral heterostructures (LH) of monolayer-multilayer regions of the same noble transition metal dichalcogenide, such as platinum diselenide (PtSe2), are promising options for the fabrication of efficient two-dimensional field-effect transistors (FETs), by exploiting the dependence of the energy gap on the number of layers and the intrinsically high quality of the heterojunctions. Key for future progress in this direction is understanding the effects of the physics of the lateral interfaces on far-from-equilibrium transport properties. In this work, a multi-scale approach to device simulation, capable to include ab-initio modelling of the interfaces in a computationally efficient way, is presented. As an application, p- and n-type monolayer-multilayer PtSe2 LH-FETs are investigated, considering design parameters such as channel length, number of layers and junction quality. The simulations suggest that such transistors can provide high performance in terms of subthreshold characteristics and switching behavior, and that a single channel device is not capable, even in the ballistic defectless limit, to satisfy the requirements of the semiconductor roadmap for the next decade, and that stacked channel devices would be required. It is shown how ab-initio modelling of interfaces provides a reliable physical description of charge displacements in their proximity, which can be crucial to correctly predict device transport properties, especially in presence of strong dipoles, mixed stoichiometries or imperfections.

Fig: Block diagram of the multi-scale procedure. Bulk DFT calculations of the materials forming the LH are performed using a plane wave basis. The resulting Hamiltonians are then projected onto MLWF and used as building blocks to construct a LH Hamiltonian with an arbitrarily long channel. The resulting LH Hamiltonian is finally used as input in NanoTCAD ViDES to simulate LH-FETs in far-from-equilibrium conditions.

Acknowledgements: This work has been supported by the European Commission through the Horizon 2020 Framework Program, Future Emerging Technologies QUEFORMAL project (contract n. 829035). The authors thank Dr. Alessandro Fortunelli for useful discussions.

[paper] Flexible Megahertz Organic Transistors

Jakob Leise^1,4, Jakob Pruefer^1,4, Ghader Darbandy¹, Aristeidis Nikolaou^1,4, Michele Giorgio², Mario Caironi², Ute Zschieschang³, Hagen Klauk³, Alexander Kloes¹, Benjamin Iñiguez⁴

and James W. Borchert⁵

Flexible megahertz organic transistors and the critical role of the device geometry on their dynamic performance

Journal of Applied Physics 130, 125501 (2021); 

DOI: 10.1063/5.0062146

  
1NanoP, TH Mittelhessen University of Applied Sciences, Gießen 35390, Germany
2Center for Nano Science and Technology @PoliMi, Istituto Italiano di Tecnologia, Milano 20133, Italy
3Max Planck Institute for Solid State Research, Stuttgart 70569, Germany
4DEEA, Uniersitat Rovira i Virgili, Tarragona 43007, Spain
5Georg August University of Goettingen, Goettingen 37077, Germany
  

Abstract: The development of organic thin-film transistors (TFTs) for high-frequency applications requires a detailed understanding of the intrinsic and extrinsic factors that influence their dynamic performance. This includes a wide range of properties, such as the device architecture, the contact resistance, parasitic capacitances, and intentional or unintentional asymmetries of the gate-to-contact overlaps. Here, we present a comprehensive analysis of the dynamic characteristics of the highest-performing flexible organic TFTs reported to date. For this purpose, we have developed the first compact model that provides a complete and accurate closed-form description of the frequency-dependent small-signal gain of organic field-effect transistors. The model properly accounts for all relevant secondary effects, such as the contact resistance, fringe capacitances, the subthreshold regime, charge traps, and non-quasistatic effects. We have analyzed the frequency behavior of low-voltage organic transistors fabricated in both coplanar and staggered device architectures on flexible plastic substrates. We show through S-parameter measurements that coplanar transistors yield more ideal small-signal characteristics with only a weak dependence on the overlap asymmetry. In contrast, the high-frequency behavior of staggered transistors suffers from a more pronounced dependence on the asymmetry. Using our advanced compact model, we elucidate the factors influencing the frequency-dependent small-signal gain and find that even though coplanar transistors have larger capacitances than staggered transistors, they benefit from substantially larger transconductances, which is the main reason for their superior dynamic performance.

Fig: Schematic cross-section of a top-contact (TC) organic TFT. Here, the semiconductor layer separates the source and drain contacts from the gate dielectric and thus from the gate-field-induced charge-carrier channel; hence, these transistors are also referred to as staggered TFTs. The overlap regions are assumed as a series connection of two capacitances. However, when the organic semiconductor (OSC) is operated in accumulation, the accumulation charges change the behavior of the series connection. The charge density at the source end of the channel is assumed to be found in the entire gate-to-source overlap region. 

Acknowledgments: The authors thankfully acknowledge funding for this project from the German Federal Ministry of Education and Research (“SOMOFLEX,” No. 13FH015IX6) and EU H2020 RISE (“DOMINO,” No. 645760), and the German Research Foundation (DFG) under Grant Nos. KL 1042/9-2, KL 2223/6-1, and KL 2223/6-2 (SPP FFlexCom). The authors would like

[paper] Perspective of Ultra-Scaled CMOS

Ab initio perspective of ultra-scaled CMOS

from 2D-material fundamentals to dynamically doped transistors

Aryan Afzalian 

Open Access; npj 2D Mater Appl 5, 5 (2021) 

DOI: 10.1038/s41699-020-00181-1 

Abstract: Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Fig: Switching energy vs delay (EDP) of high-performance MOSFET and D2-FET inverters. EDP of 1ML-HfS2 high-performance inverter cells, at various VDD (0.4 V to 0.7 V), made of L = 5 nm and L = 3 nm stacked DG MOSFETs (5 ribbons/device) and L = 0 nm and L = nm stacked SG-D2-FETs (nine ribbons/device). The EDP performance of Si HP inverter cells made of L = 12 nm stacked Si-GAA MOSFETs (tS = 5 nm, 8 wires/device) and L = 5 nm stacked Si SG-D2-FETs (tS = 3 nm, 7 ribbons/device) are also shown for comparison. The inverters are loaded with a 50 contacted-gate-pitch-long metal line (https://irds.ieee.org/editions/2018). The extrinsic capacitances of the cell layout are also included in the load capacitance. IOFF = 10 nA/μm. ΔL = 4 nm for the D2-FETs.

Acknowledgements: Part of the computing resources and services used in this work were provided by the VSC (Flemish Supercomputer Center), funded by the Research Foundation–Flanders (FWO) and the Flemish Government. The author acknowledges the support of Dr. G. Gaddemane for the DFTP e-ph coupling calculations.

Open Access: This article is licensed under a Creative Commons Attribution 4.0 International License

[ESSCIRC 2015] Low-power analog RF circuit design based on the inversion coefficient

[ref] Enz, Christian; Chalkiadaki, Maria-Anna; Mangla, Anurag, "Low-power analog/RF circuit design based on the inversion coefficient," in ESSCIRC 2015 - 41st , vol., no., pp.202-208, 14-18 Sept. 2015

Abstract: This paper discusses the concept of the inversion coefficient as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including velocity saturation. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design. The use of the inversion coefficient and the derived figures-of-merit for optimization and design is demonstrated through simple examples. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of a commercial 40-nm bulk CMOS process as well as with simulations using the BSIM6 model.

Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6

URL / doi: 10.1109/ESSCIRC.2015.7313863