[paper] RTN of a 28-nm Cryogenic MOSFET

HeeBong Yang, Marcel Robitaille, Xuesong Chen, Hazem Elgabra, Lan Wei, Na Young Kim

Random Telegraph Noise of a 28-nm Cryogenic MOSFET in the Coulomb Blockade Regime

IEEE Electron Device Letters, vol. 43, no. 1, pp. 5-8, Jan. 2022

DOI: 10.1109/LED.2021.3132964.

  

* Institute for Quantum Computing, Waterloo Institute for Nanotechnology (CA)

Abstract: We observe rich phenomena of two-level random telegraph noise (RTN) from a commercial bulk 28-nm p-MOSFET (PMOS) near threshold at 14 K, where a Coulomb blockade (CB) hump arises from a quantum dot (QD) formed in the channel. Minimum RTN is observed at the CB hump where the high-current RTN level dramatically switches to the low-current level. The gate-voltage dependence of the RTN amplitude and power spectral density match well with the transconductance from the DC transfer curve in the CB hump region. Our work unequivocally captures these QD transport signatures in both current and noise, revealing quantum confinement effects in commercial short-channel PMOS even at 14 K, over 100 times higher than the typical dilution refrigerator temperatures of QD experiments (< 100 mK). We envision that our reported RTN characteristics rooted from the QD and a defect trap would be more prominent for smaller technology nodes, where the quantum effect should be carefully examined in cryogenic CMOS circuit designs.

Fig: (a) The trapping behaviors are illustrated with empty trap (solid line) and occupied trap (dashed line) across the hump area of the |ID| -|VGS| sweep. (b) The current power spectral density (PSD) of the discretized data with the 1/f2 PSD guideline in red.

Acknowledgment: J. Watt and C. Chen in Intel for samples, A. Malcolm for early work, and J.Baugh for helpful discussions are appreciated.

[paper] RTN and BTI statistical compact modeling

G.Pedreira^a, J.Martin-Martinez^a, P.Saraza-Canflanca^b, R.Castro Lopez^b, R.Rodriguez^a, E.Roca^b, F.V.Fernandez^b, M.Nafria^a 

Unified RTN and BTI statistical compact modeling from a defect-centric perspective

Solid-State Electronics

Available online 25 June 2021, 108112

In Press, Journal Pre-proof

DOI: 10.1016/j.sse.2021.108112

a Universitat Autònoma de Barcelona (UAB), Electronic Engineering Department, REDEC group. Barcelona, Spain
b Instituto de Microelectrónica de Sevilla, IMSE-CNM, CSIC and Universidad de Sevilla, Spain

Abstract: In nowadays, deeply scaled CMOS technologies, time-dependent variability effects have become important concerns for analog and digital circuit design. Transistor parameter shifts caused by Bias Temperature Instability and Random Telegraph Noise phenomena can lead to deviations of the circuit performance or even to its fatal failure. In this scenario extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at near threshold, nominal and accelerated aging conditions. Statistical modelling of RTN and BTI combined effects covering the full voltage range is presented. 

The results of this work suppose a complete modelling approach of BTI and RTN that can be applied in a wide range of voltages for reliability predictions.

[paper] JART VCM v1 Verilog-A Compact

JART VCM v1 Verilog-A Compact

Model User Guide

Christopher Bengel, David Kaihua Zhang, Rainer Waser, Stephan Menzel

Electronic Materials Research Laboratory; RWTH Aachen University
Forschungszentrum Jülich

Abstract: The JART VCM v1a model was developed to simulate the switching characteristics of ReRAM devices based on the valence change mechanism. In this model, the ionic defect concentration (oxygen vacancies) in the disc region close to the active electrode (AE) defines the resistance state. The concentration changes due to the drift of the ionic defects. Furthermore, these oxygen vacancies act as mobile donors and modulate the Schottky barrier at the AE/oxide interface. In this model, Joule heating is considered, which significantly accelerates the switching process at high current levels. Since the JART VCM v1b model represents an improvement of the JART VCM v1a model, this user guide will have its focus on the JART VCM v1b model. Here, the equivalent circuit diagram (ECD) as well as some equations have been modified to explain the switching dynamics more accurately  Based on the JART VCM v1b model, a variability model was developed, which includes both device-to-device and cycle-to-cycle variability. In terms of the device-to-device variability, the VCM cells are initiated with statistical distributed parameters: filament lengths, filament radii and maximum and minimum values for the oxygen vacancy concentration in the disc. The cycle-to-cycle variability is achieved by changing the four quantities during SET and RESET. The latest extension of the JART VCM v1b also includes RTN, which is based on statistical jumps of oxygen vacancies into and out of the disc region.

Fig: Equivalent circuit diagram of the JART VCM v1b model (a) 

along with the electrical model in Verilog-A (b).

The Verilog-A code of this model can be downloaded here (Verilog-A file).
The User Guide for this model version can be downloaded here (User Guide PDF).

[paper] Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS

T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto and K. Kobayashi

Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS

2017 IEEE ICICDT, Austin, TX, USA, 2017, pp. 1-4.

doi: 10.1109/ICICDT.2017.7993526

Abstract: As device sizes are downscaled to nanometer, Random Telegraph Noise (RTN) becomes dominant. It is indespensable to accurately estimate the effect of RTN. We propose the RTN simulation method for analog circuits. It is based on the charge trapping model. We replicate the RTN-induced threshold voltage fluctuation to attach a variable DC voltage source to the gate of MOSFET by using Verilog-AMS. We confirm that drain current of MOSFETs temporally fluctuates. The fluctuations of RTN are different for each MOSFET. Our proposed method can be applied to estimate the temporal impact of RTN including multiple transistors. We can successfully replicate RTN-induced frequency fluctuations in 3-stage ring oscillators as similar as the measurement results [read more...]

[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva, H. P. Tuinhout, A. Zegers-van Duijnhoven, G. I. Wirth and A. J. Scholten

"A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping" 

in IEEE TED, vol. 64, no. 8, pp. 3331-3336, Aug. 2017.
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm [read more...]

[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva; H. P. Tuinhout; A. Zegers-van Duijnhoven; G. I. Wirth; A. J. Scholten;

in IEEE Transactions on Electron Devices, vol.PP, no.99, pp.1-6
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. [read more...]