[paper] PSP RF Model

Xiaonian Liu1, 2, and Yansen Liu1, 2

Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract: An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 µm CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The PSP RF subcircuit model and its S-par s fitting

results of NMOS with Wf = 2 µm, Lf = 0.12 µm, nf = 16

Acknowledgment: This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

[paper] SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

Tianshi Liu¹, Hua Zhang¹, Sundar Babu Isukapati², Emran Ashik³, Adam J. Morgan², Bongmook Lee³, Woongje Sung², Ayman Fayed¹, Marvin H. White¹, and Anant K. Agarwal¹

SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

IEEE Journal of the Electron Devices Society, vol. 10, pp. 129-138, 2022, 

DOI: 10.1109/JEDS.2022.315036

   
1 Department of Electrical & Computer Engineering, The Ohio State University, Columbus, OH 43210, USA
2 College of Nanoscale Science and Engineering, State University of New York Polytechnic Institute, Albany, NY 12309, USA
3 Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, NC 27695, USA

Abstract: Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600 V lateral SiC power MOSFETs and low-voltage SiC CMOS devices. It enables application-specific SiC ICs with high power output and work under harsh (high-temperature and radioactive) environments compared to Si power ICs. This work presents the device characteristics, SPICE modeling, and SiC CMOS circuit demonstrations of the first two lots of the proposed SiC power IC technology. Level 3 SPICE models are created for the high-voltage lateral power MOSFETs and low-voltage CMOS devices. SiC ICs, such as the SiC CMOS inverter and ring oscillator, have been designed, packaged, and characterized. Proper operations of the circuits are demonstrated. The effects of the trapped interface charges on the characteristics of SiC MOSFETs and SiC ICs are also discussed.

FIG: Cross-sectional view of the SiC MOSFETs (lot2)

Acknowledgment The authors would like to thank the team at Analog Devices (ADI), Hillview facility for the fabrication of devices and Advanced Research Projects Agency-Energy (ARPA-E). The authors also thank D. Xing for providing the customized gate driver for the dynamic characterizations of the circuits

[paper] Compact Model for SiC Power MOSFETs

Cristino Salcines¹, Sourabh Khandelwal² and Ingmar Kallfass¹ 

A Compact Model for SiC Power MOSFETs 

for Large Current and High Voltage Operation Conditions 

(2021) arXiv-2104. 

1 University of Stuttgart Stuttgart, Germany

2 Macquarie University Sydney, Australia  

Abstract: This work presents a physics based compact model for SiC power MOSFETs that accurately describes the I-V characteristics up to large voltages and currents. Charge-based formulations accounting for the different physics of SiC power MOSFETs are presented. The formulations account for the effect of the large SiC/SiO2 interface traps density characteristic of SiC MOSFETs and its dependence with temperature. The modeling of interface charge density is found to be necessary to describe the electrostatics of SiC power MOSFETs when operating at simultaneous high current and high voltage regions. The proposed compact model accurately fits the measurement data extracted of a 160 milli ohms, 1200V SiC power MOSFET in the complete IV plane from drain-voltage Vd = 5mV up to 800 V and current ranges from few mA to 30 A.

Fig: Output characteristics up to high current and high voltage in logarithmic scale for VGS = 6V to 20V in steps of 0.5V. Symbols are measurements and solid lines simulations of the proposed model. The logarithmic scale eases the visualization of both low and high VDS voltages in a single graph.

[paper] Symmetric Source and Drain Voltage Clamping Scheme

K. Xia¹ (Senior Member, IEEE)

Symmetric Source and Drain Voltage Clamping Scheme

for Complete Source-Drain Symmetry in Field-Effect Transistor Modeling

in IEEE Transactions on Electron Devices

DOI: 10.1109/TED.2020.3004799

¹NXP Semiconductors N.V., Chandler, AZ 85224 USA

Abstract: For structurally symmetric field-effect transistors with respect to the source and the drain, their models should be electrically symmetric about the source-drain interchange. This article shows that the commonly used drain-source voltage clamping technique breaks such a symmetry. This article then presents a symmetric source and drain voltage clamping scheme to solve the problem. The effectiveness of the new scheme is demonstrated by both the planar MOSFET model PSP and the FinFET model BSIM-CMG.

Fig: Fourth order derivative of I_x with respect to V_x during Gummel symmetry test for an n-MOSFET on a 130nm technology. V_g = 1.15V. Vb = 0V. W/L = 10.02μm/0.15μm. V_d = −V_s = V_x. T=27^◦C. V_x stepsize is 10mV in the measurement and 0.1mV in the simulation, respectively.

[Short Course] Modeling and Simulation of Nano-Transistors

Short Course

Modeling and Simulation of Nano-Transistors

6 - 10 July 2020 at Outreach Auditorium,IIT Kanpur

http://www.iitk.ac.in/nanolab/sc2020/

by Prof. Yogesh S. Chauhan

Nanolab, IIT Kanpur

http://home.iitk.ac.in/~chauhan/

Aim: VLSI design will soon use transistors whose size will be as small as 10nm. The aim of this short course is to educate and train bright minds on different aspects of Nano-transistors. Modeling especially compact modeling is the heart of circuit simulation. TCAD simulations are used for early device design and to understand the internal physics of transistor. Electrical characterization includes current and capacitance voltage measurement of transistor. RF measurement is an exciting area which involves understanding of devices as well as high frequency effects. This short course will cover various topics in modeling, simulation and characterization of transistors especially at nanoscale.

Topics: (1) VLSI design and Nanoelectronics, (2) Physics and Operation of MOSFET, (3) SPICE and Circuit simulation, (4) TCAD simulation: Theory and demonstration, (5) Compact Modeling: Theory and demonstration, (6) Scaling and Moore's Law, (7) Nano-Transistors: FinFET, FDSOI, Negative Capacitance FET, Nanosheet FETs, 2D-FETs etc. (8) Characterization: Current and capacitance measurement, (9) RF CMOS and GaN High Electron Mobility Transistors

Hands-on Sessions: (1) Verilog-A coding, (2) SPICE ckt. Simulation, (3) TCAD Simulation, (4) Parameter Extraction

Coordinator: Prof. Yogesh S. Chauhan Dept. of Electrical Engg., IIT Kanpur

Registration: This short course has been postponed to end of this year or early next year due to ongoing pandemic. New Dates will be announced once normalcy returns in the country.

Article reached 1,000 reads

A. Bazigos, M. Bucher, J. Assenmacher, S. Decker, W. Grabinski and Y. Papananos

An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs

IEEE Transactions on Electron Devices,

vol. 58, no. 11, pp. 3751-3758, Nov. 2011.

doi: 10.1109/TED.2011.2164080

Abstract:

The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implanted devices. The generalized adjusted CC method is based on the theory of the charge-based MOS transistor model. It introduces an adjusted current criterion, depending on VDS , allowing to coherently determine VTH for the entire range of VDS from linear operation to saturation. The method uses commonly available ID versus VG data with focus on moderate inversion. The method is validated with respect to the ideal surface potential model, and its suitability is demonstrated with technology-computer-aided-design data from a 65nm CMOS technology and measured data from a 90nm CMOS technology. Comparison with other widely used threshold voltage extraction methods is provided.

[paper] Improvements to a compact MOSFET model for design by hand

Improvements to a compact MOSFET model for design by hand

A. de Jesus Costa, F. Martins Cardoso, E. Pinto Santana and A. I. Araújo Cunha

15th IEEE NEWCAS

Strasbourg, France, 2017, pp. 225-228

doi: 10.1109/NEWCAS.2017.8010146

Abstract: In this work, an improved version of the basic structure of a compact MOSFET model and the respective parameters extraction methodology are proposed. The aim of this approach is to increase accuracy in hand calculations for analog circuit design without significantly increasing its complexity. The influences of both inversion level and channel length are considered in the modeling of a few features such as mobility, threshold voltage and onset of saturation. Simple design examples of current sinks and sources are accomplished to compare the basic and the improved models [read more...]

[paper] Compact Electro-Mechanical-Fluidic Model for Actuated Fluid Flow System

Compact Electro-Mechanical-Fluidic Model for Actuated Fluid Flow System

T. K. Maiti, Member, IEEE, L. Chen, H. Zenitani, H. Miyamoto, Member, IEEE,

M. Miura-Mattausch, Fellow, IEEE, and H. J. Mattausch, Senior Member, IEEE

in IEEE Journal on Multiscale and Multiphysics Computational Techniques, 

vol. 2, no. , pp. 124-133, 2017.

doi: 10.1109/JMMCT.2017.2731878

Abstract: This paper presents a compact electro-mechanical-fluidic system-modeling method for multidomain system simulation based on multidomain physics that considers the total energy conservation condition, in terms of respective potential and flow quantities. Models for electrical, mechanical, and fluidic domains are developed to design the example of a blood pumping system, where the blood flow is driven by electrically controlled organic actuators. The electrical domain includes an organic mosfet-based control circuit, the mechanical domain includes organic actuators, and the fluidic domain includes a flexible fluid-flow channel. Control circuit, actuators, and fluid models are coupled through equivalent circuits, where interconnection relationships between two neighboring domains are expressed using the energy conservation concept. The model accuracy is verified with finite element method (FEM) based numerical simulation. Significantly faster simulation speed than with FEM and good accuracy were achieved [read more...]

TABLE: CORRESPONDING FORCE AND FLOW EQUATIONS FOR ELECTRICAL AND
MECHANICAL DOMAINS ARE SUMMARIZED [21]-[23]

[21] S. D. Senturia, Microsystems Design. Norwell, MA: Kluwer Academic Publisher, 2001.

[22] T. K. Maiti, L. Chen, H. Miyamoto, M. Miura-Mattausch, and H. J. Mattausch, “Modeling of electrostatically actuated fluid flow system for mixed-domain simulation,” in 20th Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 190-193, Sept. 2015, USA.

[23] T. K. Maiti, L. Chen, H. Miyamoto, M. Miura-Mattausch, and H. J. Mattausch, “Mixed domain compact modeling framework for fluid flow driven by electrostatic organic actuators,” in 45th European Solid-State Device Research Conference (ESSDERC), pp. 52-55, Sept. 2015, Austria. 

Mini-Colloquium (MQ) on Nanoelectronics

AGENDA
DATE: Saturday Aug. 26, 2016

VENUE: IIT Kanpur L16

This Mini-Colloquium (MQ) on Nanoelectronics is being hosted by the IEEE Electron Device Society UP Chapter in collaboration with the Department of Electrical Engineering at IIT Kanpur. Distinguished speakers from renowned universities will be presenting on wide range of topics in Nanoelectronics. The MQ will be organized into 1 hour talks by the speakers. The agenda would be as follows:

Time	Topic	Speaker
9:00 - 9:15	Inauguration
9:15 - 9:30	High Tea
9:30 - 10:30	Nanotransistors with 2D materials: Opportunities and Challenges	Prof. Navkanta Bhat IISc
10:30 - 11:30	Revisiting gate C-V characterization for high mobility semiconductor MOS devices	Prof. Anisul Haque East West Univ.
11:30 - 11:45	Tea
11:45 - 12:45		Prof. V. Ramgopal Rao IIT Delhi
12:45 - 14:15	Lunch
14:15 - 15:15	ASM-HEMT - First Industry Standard Compact Model for GaN HEMTs	Prof. Yogesh Singh Chauhan IIT Kanpur
15:15 - 16:15	Spintronics - Perspectives and Challenges	Prof. Brajesh Kumar Kaushik IIT Roorkee
16:15 - 16:30	Tea
16:30 - 17:30	Advanced Hetero structure based Nano Scale MOSFETs	Prof. Chandan Kumar Sarkar Jadavpur Univ.

Coordinator: Dr. Yogesh S.Chauhan IIT Kanpur, India
Website: http://www.iitk.ac.in/nanolab/MQ/index.html