[chapter] Low-Voltage Analog IC Design

Deepika Gupta¹

Low-Voltage Analog Integrated Circuit Design

Nanoscale VLSI. Book series (ESIEE) (2020) pp 3-22

DOI: 10.1007/978-981-15-7937-0_1

¹Department of Electronics and Communication Engineering, IIIT Naya Raipur, India

Abstract: In this chapter, we review the challenges and effective design techniques for ultra-low-power analog integrated circuits. With the miniaturization, having low-power low-voltage mixed signal IC is essential to maintain the electric field in the device. This constraint presents bottleneck for the researchers to design robust analog circuits. Specifically, the low value of supply voltage with small technology influences many specifications of analog IC, e.g., power supply rejection, dynamic range and immunity to noise, etc. In addition, it also affects the ability of the MOS transistor to be operated in the strong inversion region. Note that with the technology reduction, power supply VDD is reducing but the threshold voltage VT is not decreasing proportionally to maintain low leakage current. However, this process reduces the overdrive voltage and limits the staking of transistors. In this case, the transistor can be made to work in weak inversion to work and reduce the power consumption. Further, reduction in VDD to achieve low-power consumption causes many other circuit-related issues such as PVT variations, degradation of dynamic range, mismatching in circuits element and differential paths. There have been many design methods developed for the ultra-low-power analog ICs. In this chapter, we will discuss some of the design techniques to reduce the power consumption in analog ICs. In addition, we will also discuss the basic building blocks of analog circuits with discussed design techniques. The charge-based EKV model can be a very suitable example of a MOS simulation model to be used in all inversion regions of transistor operations [Enz 2017]. In EKV model, the smallest number of core parameters is needed for the accurate behavioral modeling of transistor. Particularly, charge-based EKV model is beneficial for the analysis of analog circuits because it allows the analysis with simple calculations over different inversion regions. Hence, developing new device simulation models specific for analog circuit design is crucial.

Fig: Vth and Vdd scaling trend vs. Leff  [Zhao 2006]

References:

[Enz 2018] Enz C, Chicco F, Pezzotta A (2017) Nanoscale MOSFET modeling-part 1: the simplified EKV model for the design of low-power analog circuits. IEEE Solid-State Circuits Magazine 9(3):26–35

[Zhao 2006] Zhao W, Cao Y (2006) New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans Electron Devices 53(11):2816–2823

[book] Systematic Design of Analog CMOS Circuits

Paul G. A. Jespers, Boris Murmann
Cambridge University Press; 31 Oct 2017; 342pp

Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables the exploration of analog circuit tradeoffs using the gm/ID ratio as a central variable in script-based design flows, and eliminates time-consuming iterations in a circuit simulator. Supported by downloadable MATLAB code, and including over forty detailed worked examples, this book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS.

[paper] Improvements to a compact MOSFET model for design by hand

Improvements to a compact MOSFET model for design by hand

A. de Jesus Costa, F. Martins Cardoso, E. Pinto Santana and A. I. Araújo Cunha

15th IEEE NEWCAS

Strasbourg, France, 2017, pp. 225-228

doi: 10.1109/NEWCAS.2017.8010146

Abstract: In this work, an improved version of the basic structure of a compact MOSFET model and the respective parameters extraction methodology are proposed. The aim of this approach is to increase accuracy in hand calculations for analog circuit design without significantly increasing its complexity. The influences of both inversion level and channel length are considered in the modeling of a few features such as mobility, threshold voltage and onset of saturation. Simple design examples of current sinks and sources are accomplished to compare the basic and the improved models [read more...]

[ngspice] FM Bugger Circuit

Project Summary by https://www.eeweb.com
The project circuit design is a FM Bugger circuit. It works like a transmitter that transmits and projects information signals into the air wherein a FM radio will act as a receiver which would receive the transmitted signal. The circuit and the FM radio must be tuned-in with the same frequency to be able to transmit and receive information in the same channel. The FM bugger circuit is originally designed to be used like a spy gadget to eavesdrop other people’s conversations. Though it is designed that way, it is pretty much useful as a transmitter or as a walkie-talkie to relay messages in a distance [read more...]

Testing and Design Procedure
The FM bugger circuit is tested using PartSim and the NGSpice to test the output of the circuit:

FM Bugger Circuit Simulation
R1 Net1009 Mic 22K
R2 Net1009 Net1016 47K
R3 Net1003 0 33K
C1 Net1016 Mic 1NF
C2 Net1016 0 1NF
C3 Net1002 Net1003 4.7pF
C4 Net1002 Antenna 1NF
C5 Net1009 0 22NF
C6 Net1009 Net1002 50pF
L1 Net1009 Net1002 9NH
Q1 Net1002 Net1016 Net1003 2N2222
V1 Net1009 0 3V
V2 Mic 0 SINE ( 1 1 20Khz 0.0S )
R4 0 Antenna 1K
.options rshunt = 1.0e12 KEEPOPINFO
.MODEL 2N2222 NPN IS =3.0611E-14 NF =1.00124
+ BF =220 IKF=0.52 VAF=104 
+ ISE=7.5E-15 NE =1.41 NR =1.005 BR =4 
+ IKR=0.24 VAR=28 ISC=1.06525E-11 NC =1.3728 RB =0.13 
+ RE =0.22 RC =0.12 CJC=9.12E-12 MJC=0.3508 VJC=0.4089 
+ CJE=27.01E-12 TF =0.325E-9 TR =100E-9
.control
OP
write Net1002 Net1003 Net1009 Net1016 Mic Antenna I(V1) I(V2)
set appendwrite true
rusage everything
.endc
.end

Conclusion
The simulation of the FM bugger circuit in PartSim shows that the circuit is working. The microphone was assumed to have an input of a 20 kHz sinusoidal wave. Then, the output signal at the load, R4 assumed to be the antenna for the circuit, turns out to produce a FM signal. Therefore, the FM bugger circuit itself has a great possibility to succeed and operate in real

Project Links:
http://www.schematics.com/embed/fm-bugger-circuit-36638/
http://www.pcbweb.com/projects/DqEwZcNdcy3ddghPnJefdJIzTcWqLd

[paper] Readout electronics for LGAD sensors

Readout electronics for LGAD sensors

O. Alonso,^a N. Franch,^a J. Canals,^a F. Palacio,^a M. López,^a A. Vilà,^a A. Diéguez,^a
M. Carulla,^b D. Flores,^b S. Hidalgo,^b A. Merlos,^b G. Pellegrini^b and D. Quirion^b
aDepartment of Engineering: Section of Electronics, University of Barcelona,
C/ Martí i Franquès nº1, Barcelona, 08028 Spain
^bInstituto de Microelectrónica de Barcelona — Centro Nacional de Microelectrónica (IMB-CNM),
Campus UAB, Cerdanyola del Vallès, Bellaterra, Barcelona, 08193 Spain
doi:10.1088/1748-0221/12/02/C02069

Abstract: In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865mm  0.965mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. A first approach to find the proper dimensioning of the input transistor has been done using a Matlab script, where the transconductance value has been calculated with the EKV model

Acknowledgments This work has been partially funded by the Spanish national projects FPA2013-48387 and FPA2015-71292. In addition, this work has been done in the framework of RD50 CERN collaboration.

[paper] Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

Aishwarya Natarajan and Jennifer Hasler

Georgia Institute of Technology Atlanta USA

Analog Integr Circ Sig Process (2017), pp 1–12

doi:10.1007/s10470-016-0914-y

ABSTRACT: An open-source simulator to design and implement circuits and systems, replicating the results from the Field Programmable Analog Array (FPAA) is presented here. The fundamental components like the transistors, amplifiers and floating gate devices have been modeled based on the EKV model with minimal parameters. Systems including continuous-time filters and the analog front-end of a speech processing system have been built from these basic components and the simulation results and the data from the FPAA are shown. The simulated results are in close agreement to the experimental measurements obtained from the same circuits compiled on the FPAA fabricated in a 350 nm process [read more...]