Sep 30, 2021

[SEMI Press Release] SEMI Applauds European Chips Act, Aimed at Boosting Semiconductor R&D and Manufacturing https://t.co/WZOd8Sw5Sh #Europe #research #development #semiconductors  #manufacturing #publicpolicy #semi #chip #EU https://t.co/mHGUZkRaXY



from Twitter https://twitter.com/wladek60

September 30, 2021 at 08:31PM
via IFTTT

[paper] New Design Concept for the IoT Era

Pedro Toledo, Graduate Student Member, IEEE, Roberto Rubino, Graduate Student Member, IEEE, Francesco Musolino, Member, IEEE, and Paolo Crovetti, Senior Member, IEEE
Re-Thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era
IEEE Transactions on Circuits and Systems—II: Express Briefs, 
Vol. 68, No. 3, March 2021
DOI:  10.1109/TCSII.2021.3049680

* DET, Politecnico di Torino (IT)

Abstract: A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed.
Fig: a) Kuijk’s Bandgap voltage reference [i]. b) Microcontroller-based proof
of concept prototype.
REF:
[i] K. E. Kuijk, “A precision reference voltage source,” IEEE J. Solid-StateCircuits, vol. SSC-8, no. 3, pp. 222–226, Jun. 1973.

[book] MEMS Product Development

Fitzgerald, Alissa M., Chung, Charles C.
MEMS Product Development: From Concept to Commercialization
ISBN 978-3-030-61709-7

Drawing on their experiences in successfully executing hundreds of MEMS development projects, the authors present the first practical guide to navigating the technical and business challenges of MEMS product development, from the initial concept stage all the way to commercialization. The strategies and tactics presented, when practiced diligently, can shorten development timelines, help avoid common pitfalls, and improve the odds of success, especially when resources are limited. MEMS Product Development illuminates what it really takes to develop a novel MEMS product so that innovators, designers, entrepreneurs, product managers, investors, and executives may properly prepare their companies to succeed.




Table of contents (20 chapters)
  1. The Opportunities and Challenges of MEMS Product Development, pp. 3-8
  2. Economics of Semiconductor Device Manufacturing and Impacts on MEMS Product Development, pp. 9-16
  3. Stages of MEMS Product Development, pp. 17-28
  4. What Is the Product? Requirements Analysis, pp. 31-45
  5. Is There a Business Opportunity? Product Unit Cost Modeling, pp. 47-57
  6. What Is the Budget for Development?, pp. 59-70
  7. Leveraging Third-Party Intellectual Property to Accelerate Product Development, pp. 71-79
  8. Organization Planning for Successful Development, pp. 81-92
  9. The MEMS Product: Functional Partitioning and Integration, pp. 95-110
  10. Starting a New MEMS Device Design, pp. 111-127
  11. Design for Manufacturing: Process Integration and Photomask Layout, pp. 129-148
  12. Design for Back-end-of-Line Processes, pp. 149-156
  13. Strategies for Codevelopment of the Electronics and Package, pp. 157-166
  14. Planning a Development Test Program, pp. 167-183
  15. Risk Mitigation Strategies for Prototype Fabrication, pp. 185-195
  16. Documenting MEMS Product Technology for Transfer to Manufacturing, pp. 197-211
  17. Determining Readiness for Volume Production, pp. 215-222
  18. Selecting a Foundry Partner, pp. 223-239
  19. Transferring Technology for Production, pp. 241-252
  20. Manufacturing Test: Opportunity, Cost, and Managing Risk, pp. 253-268

Sep 29, 2021

[mos-ak] [online publications] 18th MOS-AK ESSDERC/ESSCIRC Workshop Grenoble; Sept. 6, 2021


The MOS-AK Association with local technical program promoters and the International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee have organized its subsequent 18th MOS-AK ESSDERC/ESSCIRC Workshop as a virtual/online event on Sept.6, 2021

Online Publications:
There are MOS-AK technical presentations covering selected aspects of the compact/SPICE modeling and its Verilog-A standardization; see all the slide presentations online at corresponding link:
The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses around the globe later this year and thru the next 2022 year, including:
  • 14th US MOS-AK Workshop, Silicon Valley (US) Dec. 2021
    • in timeframe of IEDM and Q4 CMC Meetings
  • 4th MOS-AK at LAEDC Workshop, Mexico 2022
W.Grabinski on the behalf of International MOS-AK Committee
WG29092021
 

Sep 27, 2021

[paper] Degradations in LDMOS Transistors

Yen-Pu Chen1, Bikram K. Mahajan1, Dhanoop Varghese2, Srikanth Krishnan2, Vijay Reddy2
and Muhammad A. Alam1
Three-point I–V spectroscopy deconvolves region-specific degradations in LDMOS transistors
Appl. Phys. Lett. 119, 122102 (2021); 
DOI: 10.1063/5.0058477

1 Department of ECE, Purdue University, West Lafayette, Indiana 47906, USA
2 Texas Instruments Inc., Dallas, Texas 75043, USA

Abstract: Unlike traditional logic transistors, hot carrier degradation (HCD) in power transistors involves simultaneous and potentially correlated degradation in multiple regions. One must deconvolve and characterize the voltage- and temperature-dependence of these region-specific degradations to develop a predictive HCD model of power transistors. Unfortunately, power transistors' doping and geometrical complexities make it challenging to use traditional defect-profiling techniques, such as charge-pumping or gated-diode methods. This Letter uses a physics-based tandem-FET model of Laterally Diffused MOS (LDMOS) transistors to develop a “three-point I–V spectroscopy” technique that uses the time-evolution of three critical points of the measured I–V characteristics to extract mobility and threshold voltage degradations in the channel and drift regions. This innovative approach should generalize to other configurations of the LDMOS transistor as well.

Fig: The proposed tandem-FET compact model. The channel (ch) and the drift (dr) regions function individually as a MOSFET with different 𝑉th and dimensions. Three adjustable degradation parameters are 𝛥𝜇𝑐ℎ, 𝛥𝑉𝑐ℎth, and 𝛥𝜇𝑑𝑟.

Acknowledgements: Y.-P.C and B.K.M contributed equally to this work. The authors gratefully acknowledge the access to the characterization facilities at Birck Nanotechnology Center, Purdue University, for the results presented in this article.

Sep 23, 2021

[Now Open for Submission] IEEE Journal on Flexible Electronics


 
 
 
 
 
 
The IEEE Journal on Flexible Electronics (J-FLEX) publishes cutting edge research covering all aspects of sensors, transistors, related devices, circuits, systems on flexible, disposable, stretchable and degradable substrates. This includes various functional and sustainable materials, material-integrated sensing, interface subsystems, corresponding actuators, energy harvesting, energy storage devices, modelling, simulation, manufacturing, integration or packaging in soft and flexible substrates and all applications of flexible electronics. Topics such as 3D printed or heterogenous integration, use of sustainable materials and processes aligned with circular economy are also in the scope of this journal.
 
 
 
 

Submit your article today, and get published in the IEEE Journal on Flexible Electronics.

 
 
Best regards,

Ravinder Dahiya
Editor-in-Chief, IEEE Journal on Flexible Electronics
 
 
 
 
If you have an IEEE Account, manage your IEEE communications preferences here. Users without an IEEE Account can access the Privacy Portal to view selected preferences and policies.

 
 
 
© 2021 IEEE– All rights reserved.
 
 
 

Sep 22, 2021

[paper] Abstraction NBTI model

Stephan Adolf and Wolfgang Nebel
Abstraction NBTI model
it - Information Technology, Sep. 2021
DOI: 10.1515/itit-2021-0005

Abstract: Negative Bias Temperature Instability (NBTI) is one of the major transistor aging effects, possibly leading to timing failures during run-time of a system. Thus, one is interested in predicting this effect during design time. In this work, an Abstraction NBTI model is introduced reducing the state space of trap-based NBTI models using two abstraction parameters, applying a state transformation to incorporate variable stress conditions. This transformation is faster than traditional approaches. Currently, the conversion into estimated threshold voltage damages is a very time-consuming process.

Fig: Trap in the gate oxide of a PMOS transistor

Acknowledgement: The author thanks Kim Grüttner for proofreading the manuscript of the paper. This research is funded by the German Research Foundation through the Research Training Group “SCARE: System Correctness under Adverse Conditions” (DFG-GRK 1765/2), https://www.uni-oldenburg.de/en/scare/. The simulations were partly performed on the HPC Cluster CARL at the University of Oldenburg (Germany), funded by the DFG through its Major Research Instrumentation Program (INST 184/157-1 FUGG) and the Ministry of
Science and Culture (MWK) of the Lower Saxony State.


Sep 21, 2021

[paper] BioDynaMo: a modular platform for high-performance agent-based simulation

Lukas Breitwieser1,2, Ahmad Hesam1,3, Jean de Montigny1, Vasileios Vavourakis4,5, Alexandros Iosif4, Jack Jennings6, Marcus Kaiser6,7,8, Marco Manca9, Alberto Di Meglio1, Zaid Al-Ars3, Fons Rademakers1, Onur Mutlu2, Roman Bauer10
BioDynaMo: a modular platform for high-performance agent-based simulation
Bioinformatics on 21 September 2021
DOI: 10.1093/bioinformatics/btab649/6371176 
  
1 CERN openlab, CERN, European Organization for Nuclear Research, Geneva, Switzerland
2 ETH Zurich, Swiss Federal Institute of Technology in Zurich, Zurich, Switzerland
3 Delft University of Technology, Delft, The Netherlands
4 Department of Mechanical & Manufacturing Engineering, University of Cyprus, Nicosia, Cyprus
5 Department of Medical Physics & Biomedical Engineering, University College London, UK
6 School of Computing, Newcastle University, Newcastle upon Tyne, UK
7 Department of Functional Neurosurgery, Ruijin Hospital, Shanghai Jiao Tong University School of Medicine, Shanghai, China
8 Precision Imaging Beacon, School of Medicine, University of Nottingham, UK
9 SCimPulse Foundation, Geleen, Netherlands
10 Department of Computer Science, University of Surrey, Guildford, UK

Abstract: Agent-based modeling is an indispensable tool for studying complex biological systems. However, existing simulation platforms do not always take full advantage of modern hardware and often have a field-specific software design.
Results: We present a novel simulation platform called BioDynaMo that alleviates both of these problems. BioDynaMo features a modular and high-performance simulation engine. We demonstrate that BioDynaMo can be used to simulate use cases in: neuroscience, oncology, and epidemiology. For each use case we validate our findings with experimental data or an analytical solution. Our performance results show that BioDynaMo performs up to three orders of magnitude faster than the state-of-the-art baselines. This improvement makes it feasible to simulate each use case with one billion agents on a single server, showcasing the potential BioDynaMo has for computational biology research.
Availability: BioDynaMo is an open-source project under the Apache 2.0 license and is available at www.biodynamo.org. Instructions to reproduce the results are available in supplementary information.
Fig: BioDynaMo’s layered architecture. BioDynaMo is predominantly executed on multi-core CPUs, is able to offload computations to the GPU, and supports Linux operating systems. BioDynaMo provides a rich set of low- and high-level features commonly required in agent-based models. On top of these generic features, BioDynaMo offers model building blocks to simplify the development of a simulation. Even if BioDynaMo does not provide the required building blocks, users still benefit from all generic agent-based features (illustrated by the vertical extension of the “Simulation" layer).

Acknowledgments: We want to thank Giovanni De Toni for his work on the BioDynaMo build system. This work was supported by the CERN Knowledge Transfer office [to L.B. and A.H.]; the Israeli Innovation Authority [to A.H.]; the Research Excellence Academy from the Faculty of Medical Science of the Newcastle University [to J.dM.]; the UCY StartUp Grant scheme [to V.V.]; the Medical Research Council of the United Kingdom [MR/N015037/1 to R.B., MR/T004347/1 to M.K.]; the Engineering and Physical Sciences Research Council of the UK [EP/S001433/1 to R.B., NS/A000026/1, EP/N031962/1 to M.K.]; a PhD studentship funded by Newcastle University’s School of Computing [to J.J.]; the Wellcome Trust [102037 to M.K.]; the Guangci Professorship Program of Ruijin Hospital (Shanghai Jiao Tong Univ.) [to M.K.]; and by several donations by SAFARI Research Group’s industrial partners including Huawei, Intel, Microsoft, and VMware [to O.M.]. The authors have declared that no competing interests exist.



Sep 20, 2021

[paper] Compact Modeling of pH-Sensitive FETs Based on 2D Semiconductors

Tarek El Grour, Francisco Pasadas, Alberto Medina-Rull, Montassar Najari, Enrique G. Marin, Alejandro Toral-Lopez, Francisco G. Ruiz, Andrés Godoy, David Jiménez and Lassaad El-Mir
Compact Modeling of pH-Sensitive FETs Based on Two-Dimensional Semiconductors
arXiv:2109.06585 [physics.app-ph; submitted on 14 Sep 2021]
DOI: 10.1109/TED.2021.3112407
   
LAPHYMNE Laboratory, Gabes University, Gabes, Tunisia
PEARL Laboratory, Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, Spain
The Innovation and Entrepreneurship Centre, Jazan University, Jazan, Saudi Arabia.
Departament d’Enginyeria Electrònica, Escola d’Enginyeria, Universitat Autònoma de Barcelona, Spain

Abstract: We present a physics-based circuit-compatible model for pH-sensitive field-effect transistors based on two-dimensional (2D) materials. The electrostatics along the electrolyte-gated 2D-semiconductor stack is treated by solving the Poisson equation including the Site-Binding model and the Gouy-Chapman-Stern approach, while the carrier transport is described by the drift-diffusion theory. The proposed model is provided in an analytical form and then implemented in Verilog-A, making it compatible with standard technology computer-aided design tools employed for circuit simulation. The model is benchmarked against two experimental transition-metal-dichalcogenide (MoS2 and ReS2) based ion sensors, showing excellent agreement when predicting the drain current, threshold voltage shift, and current/voltage sensitivity measurements for different pH concentrations.
Fig: a) Schematic depiction of a 2D-ISFET b) its quivalent capacitive circuit

Acknowledgments: This work is supported in part by the Spanish Government under the projects TEC2017-89955-P, RTI2018-097876-B-C21 and PID2020-116518GB-I00 (MCIU/AEI/FEDER, UE); the FEDER/Junta de Andalucía under project BRNM-375-UGR18; EC under Horizon 2020 projects WASP No. 825213 and GrapheneCore3 No. 881603. E.G. Marin gratefully acknowledges Juan de la Cierva Incorporación IJCI-2017-32297. A. Toral-Lopez acknowledges the FPU program (FPU16/04043). F. Pasadas acknowledges funding from PAIDI 2020 and Andalusian ESF OP 2014-2020 (20804). F. Pasadas and D. Jiménez also acknowledge the partial funding from the ERDF allocated to the Programa Operatiu FEDER de Catalunya 2014-2020, with the support of the Secretaria d’Universitats i Recerca of the Departament d’Empresa i Coneixement of the Generalitat de Catalunya for emerging technology clusters to carry out valorization and transfer of research results. Reference of the GraphCAT project: 001-P-001702.


Sep 17, 2021

[paper] EKV Model for Bulk-Driven Circuit Design Using gmb/ID Method

Lukas Nagy, Daniel Arbet, Martin Kovac, Miroslav Potocny, Robert Ondica and Viera Stopjakova
EKV Model for Bulk-Driven Circuit Design Using gmb/ID Method
IEEE AFRICON; 13-15 September 2021; Arusha (TZ)
 
Institute of Electronics and Photonics; Faculty of Electrical Engineering and Information Technology; Slovak University of Technology; Bratislava (SK)

Abstract: The paper addresses a development and application of EKV MOS transistor compact model with focus on the ultra low-voltage / ultra low-power analog integrated circuit (IC) design employing bulk-driven (BD) technique. The presented contribution can be viewed as an extension of standard EKV model application and as a contribution to ultra low-voltage IC design techniques. The paper compares the measured and extracted small-signal parameters of standalone transistor samples fabricated in 130 nm CMOS technology and the simulation results obtained using the proposed bulk-driven EKV v2.63 model and foundry-provided BSIM model v3.3. The transistor samples were analyzed with power supply of VDD = 0.4 V The paper also discusses the implementation of 3D graphs as a result of introducing another degree of freedom into the essential MOS transistor characteristics, while maintaining the ease of using the design hand-calculation with the original gm/ID approach.

Fig: Bulk-Driven TEF vs Inversion Coefficient – gmb/ID

Acknowledgment: This work has been supported in part by the Slovak Research and Development Agency under grant APVV 19-0392, the Ministry of Education, Science, Research and Sport of the Slovak Republic under grants VEGA 1/0731/20 and VEGA 1/0760/21, and ECSEL JU under project PROGRESSUS (Agr. No. 876868)

Sep 1, 2021

Keep Your Business Running With KiCad EDA

Get Professional Support For Your KiCad Installation

Trying to accomplish something with KiCad?  From basics wiring to high-speed impedance matching, KiPro has you covered.  Your designers and engineers can get their answers quickly, with no hassles, from IPC CID certified engineers.  

With KiPro, you can get back up and running quickly.  And when you find something in your workflow that KiCad needs to do better, we handle that too! [read more...]