IEEE EDS/SSCS/CAS MQ in Palma

IEEE EDS/SSCS/CAS Mini-Colloquium

FRIDAY 11 September

Sa Riera Building

C/ de Miquel dels Sants Oliver, 2

07122 Palma

IEEE EDS/SSCS/CAS MQ PROGRAM

9:00 - 09:05 Opening

9:05-9:15 Tribute to Prof. Michael S. Shur

9:05-9:15 Tribute to Prof. José Epifânio da Franca

​​​​9:15-10:05 Leveraging semiconductor technology for the benefit of society

Fernando Guarin (Director of IEEE Division I)

10:05-10:55 Power efficient WBG devices for the green transition

Mikael Ostling (KTH, SE)

10:55-11:25 Coffee Break

11:25-12:15 Holistic solutions to future computing - not only scaling

Francesca Iacopi (Purdue University, US)

12:15-13:05 Status of the Compact modeling and its Verilog-A standardization

Wladek Grabinski (MOS-AK, CH and IHP OpenPDK, DE)

13:05-14:25 Lunch​​

14:25-15:15 Graphene thin film technology for neural interfaces

José Antonio Garrido (ICN2, Barcelona, Spain)

15:15-16:05Energy-Efficient Analog IC Design: Exploring Solutions at De vice, Circuit and System Levels

Antonio López (Public University of Navarra, Spain)

IEEE EDS/SSCS/CAS Mini-Colloquium

Friday 11 September 2026

UIB; Sa Riera Building

C/ de Miquel dels Sants Oliver, 2

07122 Palma

Professors Benjamin Iniguez, URV and Rodrigo Picos, UIB, have organize joint IEEE EDS/SSCS/CAS Mini-Colloquium as an integral part of the recent ESSERC2026 in Palma de Mallorca. All the MQ participants followed the MQ program as follows:

Mini-Colloquium Agenda

9:00 - 09:05 Opening

9:05-9:15 Tribute to Michael S. Shur

9:05-9:15 Tribute to José Epifânio da Franca 

9:15-10:05 Leveraging semiconductor technology for the benefit of society

Fernando Guarin (Director of IEEE Division I)

10:05-10:55 Power efficient WBG devices for the green transition

Mikael Ostling (KTH, SE)

10:55-11:25 Coffee Break

11:25-12:15 Holistic solutions to future computing - not only scaling

Francesca Iacopi (Purdue University, US)

12:15-13:05 Status of the Compact modeling and its Verilog-A standardization

Wladek Grabinski (MOS-AK, CH and IHP OpenPDK, DE)

13:05-14:25 Lunch

14:25-15:15 Graphene thin film technology for neural interfaces

José Antonio Garrido (ICN2, Barcelona, Spain)

15:15-16:05 Energy-Efficient Analog IC Design:

Exploring Solutions at Device, Circuit and System Levels

Antonio López (Public University of Navarra, Spain)

[IEEE EDS DL] Multifunctional materials for emerging optoelectronic technologies

IEEE EDS Distinguished Lecture

Hawaii Section Jt. Chapter, ED15/SSC37

December 19 @ 6:30 pm - 8:00 pm

Room: 244, Bldg: Holmes Hall, 2540 Dole St, Honolulu

Hawaii, United States, 96822

Dr. Federico Rosei from the University of Trieste will be presenting a Distinguished Lecturer Seminar titled "Multifunctional materials for emerging optoelectronic technologies" on Friday December 19th at 6:30PM. RSVP one week in advance for a headcount on food [register]

Abstract: functionalities. Such systems are then used as building blocks for the fabrication of various emerging technologies. In particular, nanostructured materials synthesized via the bottom–up approach present an opportunity for future generation low cost manufacturing of devices. We focus in particular on recent developments in solar technologies that aim to address the energy challenge, including third generation photovoltaics, solar hydrogen production, luminescent solar concentrators and other optoelectronic devices. 

Bio: Federico Rosei (MSc (1996) and PhD (2001) from the University of Rome “La Sapienza”) holds the Chair of Industrial Chemistry at the Department of Chemical and Pharmaceutical Sciences, University of Trieste since March 2023. Previously he was Full Professor at the Centre Énergie, Matériaux et Télécommunications, Institut National de la Recherche Scientifique, Varennes (QC) Canada, where he served as Director (07/2011–03/2019). He held the Canada Research Chair (Junior) in Nanostructured Organic and Inorganic Materials (2003–2013) and the Canada Research Chair (Senior) in Nanostructured Materials (2016–2023) and the UNESCO Chair in Materials and Technologies for Energy Conversion, Saving and Storage (2013–2023).

[Deadline] extended to Oct.15 2026

10th IEEE Electron Devices Technology and Manufacturing

(EDTM 2026) Conference

https://ieee-edtm.org/

March 1-4, 2026 Penang, Malaysia 

EDTM2026 paper submission date has been extended to 15th October 2025

Submit your papers today in any of the 13 tracks and see you in Penang, Malaysia from 1st - 4th March 2026.

• Contributed papers will be judged for the best paper award for each technical track
• Each track will have Invited Speakers. Meet prominent Plenary and Keynote Speakers from Industry and academia for research, networking, innovation and commercialization purposes
• Exhibition and sponsorship opportunities to showcase breakthrough technology
• Extended versions of accepted papers to be published in 
• EEE Transactions on Materials for Electron Devices (T-MAT) and 
• Journal of IEEE Electron Devices Society (JEDS)

[C4P] EDTM 2025 in Hong Kong, China

The 9th IEEE Electron Devices Technology and Manufacturing Hong Kong, China, March 9th – 12th, 2025 Theme: Shaping the Future with Innovations in Devices and Manufacturing Call for Papers Three-page camera-ready paper submission starts: August 15, 2024 Paper submission deadline: October 15 October 31, 2025 Notification for Acceptance: December 15, 2024 https://edtm2025.com/ Technical Areas EDTM 2025 solicits papers in all areas of electronic devices, including materials, processes, modeling, device/circuit/system design, reliability, packaging, manufacturing, testing, and yield. EDTM 2025 will include parallel technical sessions of oral and poster presentations. Publication Opportunities The accepted and presented papers will be published in the EDTM 2025 Proceedings, included in IEEE Xplore. The authors of a selected number of high-impact papers will be invited to submit extended versions for publication in the special issue of IEEE Journal of Electron Devices Society (J-EDS) or IEEE Transactions on Electron Devices, subjected to J-EDS and TED policy. Short Courses and Tutorials EDTM 2025 will start with a set of short courses and tutorials on March 9, 2025. Tutorials will cover selected topics from the basics to the state-of-the-art. The Short Courses will discuss the latest research and challenges on emerging and advanced topics. Exhibition EDTM 2025 offers vendors to showcase their newest products and technologies, allowing attendees to learn about new tools and techniques. Award Opportunities EDTM 2025 offers one Best Paper Award in each sub-technical area.

General Chair： Yang Chai (HK PolyU) General Co-Chair： Tim Cheng (HKUST) TPC Chair： Mansun Chan (HKUST) TPC Co-Chair： Yansong Yang (HKUST) Steering Committee: Shuji Ikeda (TEI Solutions) – Chair Bin Zhao (CTI) Arokia Nathan (Cambridge U.) Ravi Todi (Synopsys) Murty Polavarapu (BAE) Roger Booth (Qualcomm) Samar Saha (Prospicient Devices) Albert Wang (UC Riverside) Kazunari Ishimaru (Rapidus) Yogesh Chauhan (IIT Kanpur) Executive Committee: Yang Chai (HK PolyU) Roger Booth (Qualcomm) Mansun Chan (HKUST) Yansong Yang (HKUST) Ru Huang (Southeast) Qiming Shao (HKUST) Merlyne De Souza (U Sheffield) Pei-Wen Li (NCTU) Can Li (HKU) Masumi Saito (Kioxia) Zhongrui Wang (HKU) Meiki Ieong (Simbury) Carmen Fung (HKSTP) Man Hoi Wong (HKUST) Roger Booth (Qualcomm) Huaqiang Wu (Tsinghua) Rino Choi (Inha U.) Bernard Lim (Appscard) Shinichi Yoshida (SONY) Bill Nehrer (Atomera) Bich-Yen Nguyen (SOITEC) Benjamin Iniguez (URV) Edmundo Gutierrez (INAOE) Ming Yang (HK PolyU)

[EDTM] Inauguration Session

8th IEEE EDTM

March 3-6, 2024

Strengthening Globalization in Semiconductors

The 8th Electron Devices Technology and Manufacturing Conference (IEEE EDTM 2024) will be held for the first time in India at Bangalore; the Silicon Valley of India and the hub of semiconductor companies. IEEE EDTM 2024 will be a full four-day conference to be held during March 3-6, 2024. IEEE EDTM 2024 aims to be a premier global forum for researchers and engineers from around the world coming to share new discoveries and discuss any device/manufacturing-related topics, including but not limited to, materials, processes, devices, packaging, modeling, reliability, manufacturing and yield, tools, testing, and any emerging device technologies, as well as workforce training. 

Plenary Talk by Prof. Chenming Hu "Semiconductor – the Next 75 Years?"

[webinar] IEEE SCV-EDS: Investigating quantum speed limits with superconducting qubits

The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Prof. Meenakshi Singh. The title of the lecture is ‘Investigating quantum speed limits with superconducting qubits’

When: Friday, Oct. 20, 2023 – 9am to 10am (PDT)
Where: This is an online event and attendees can participate via Zoom.

Registration or Send an email to hiuyung.wong at ieee.org to get the zoom link indicating if you are IEEE member, IEEE EDS member, IEEE Student member

Abstract: The speed at which quantum entanglement between qubits with short range interactions can be generated is limited by the Lieb-Robinson bound. Introducing longer range interactions relaxes this bound and entanglement can be generated at a faster rate. The speed limit for this has been analytically found only for a two-qubit system under the assumption of negligible single qubit gate time. We seek to demonstrate this speed limit experimentally using two superconducting transmon qubits. Moreover, we aim to measure the increase in this speed limit induced by introducing additional qubits (coupled with the first two). Since the speed up grows with additional entangled qubits, it is expected to increase as the system size increases. This has important implications for large-scale quantum computing.

Speaker Bio: Dr. Singh is an experimental physicist with research focused on quantum thermal effects and quantum computing. She graduated from the Indian Institute of Technology with an M. S. in Physics in 2006 and received a Ph. D. in Physics from the Pennsylvania State University in 2012. Her Ph. D. thesis was focused on quantum transport in nanowires. She went on to work at Sandia National Laboratories on Quantum Computing as a post-doctoral scholar. She is currently an Associate Professor in the Department of Physics at the Colorado School of Mines. At Mines, her research projects include measurements of spin-orbit coupling in novel materials and thermal effects in superconducting hybrids. She recently received the NSF CAREER award to pursue research in phonon interactions with spin qubits in silicon quantum dots.

[EDS MQ/DL] The Transistor Turns 75

The Transistor Turns 75

A Forward Look to Challenges and Opportunities

A series of IEEE EDS Distinguished Lecturer talks on topics in current transistor and electron device research, reflecting on the challenges ahead and the rewards inherrent in overcomming them.

DATE AND TIME	LOCATION	HOSTS	REGISTRATION
Date: 02 Jun 2023 Time: 08:30 AM to 05:30 PM All times are (UTC+00:00) Edinburgh	Moller Institute Cambridge, England UK CB3 ODE Click here for Map	UK and Ireland Section Chapter, ED15 Contact Host	Starts 19 April 2023 06:00 AM Ends 30 May 2023 06:30 PM All times are (UTC+00:00) Edinburgh No Admission Charge Register Now

EDS DL SPEAKERS

• Benjamin Iniguez: Modeling 2D Semiconductor Devices
• Lluis Marsal: Organic Photovoltaics: Opportunities and Challenges
• Arokia Nathan: 
• Fernando Guarin: 75th Anniversary of the Transistor Semiconductor Industry Perspective
• Edmundo A. Gutierrez-D.: DC and RF reliability of advanced bulk and SOI CMOS technologies
• Merlyne De Souza: Challenges to Edge computing: an era beyond silicon CMOS
• Samar Saha: 
• MK Radhakrishnan: Birth and Evolution of Transistor and Its Impact on Humanity
• Xiaojun Guo: Transistor Technologies for Hybrid Integration at Micro- and Macro-scales
• Hiroshi Iwai: Present status and future of the nanoelectronics technology

[Hisayo Momose] My Journey as a Researcher in the Semiconductor Field

 

Hisayo Mosmose's Story 

Read Hisayo Momose's article from the IEEE EDS January Newsletter, "My Journey as a Researcher in the Semiconductor Field."

Dr. Momose has more than 30 years of experience in research and development at Toshiba Corporation, Japan. She is a recipient of several awards and honors, and has authored or co-authored nearly 200 papers published in technical journals and conference proceedings [read more...]

#IEEE #EDS #ElectronDevices #WiEDS #womeinengineering #semiconductors
 

 

 

IEEE EDS MQ at NIT Silchar Silchar, Assam (IN)

IEEE EDS Mini-Colloquium 

on Micro/Nanoelectronics, Devices, Circuits and Systems, 

29-31 Jan 2023 (Hybrid Mode)

DATES	LOCATION	HOST	REGISTER
Date: 29 Jan 2023 Time:10:00AM to 06:00PM  (UTC+05:30)  Add Event to Calendar  iCal  Google Calendar	National Institute of Technology Silchar Dept of ECE, NIT Silchar Silchar, Assam India 788010 Building: ECE/CSE Building	National Inst of Technology - Silchar, ED15 Kolkata Section Chapter NANO42 Co-sponsored by Dr. Trupti R. Lenka	Starts Dec.1, 2022 Ends Jan.28,2023 No Admission Charge Register NOW

Agenda with following contribution Distinguished Lecturers: 

• Anil Kottantharayil (anilkg@ieee.org)
• Gananath Dash (gndash@ieee.org)
• Ajit Kumar Panda (akpanda62@hotmail.com)
• Manoj Saxena (msaxena@ieee.org)
• Brajesh Kumar Kaushik (bkkaushik23@gmail.com)
• Samar Saha (samar@ieee.org)
• Hiroshi Iwai (h.iwai@ieee.org)
• Taiichi Otsuji (taiichi.otsuji.e8@tohoku.ac.jp)
• Pei-Wen Li (pwli@nycu.edu.tw)
• Zhou Xing (EXZHOU@ntu.edu.sg)
• Albert Chin (albert_achin@hotmail.com)
• Mansun Chan (mchan@ust.hk)
• Chao-Sung LAI (cslai@mail.cgu.edu.tw)
• Wladek Grabinski, MOS-AK, EU (wladek@grabinski.ch)

Register NOW

[Program] MINI-COLLOQUIUM ON CAD/EDA MODELING

MINI-COLLOQUIUM ON CAD/EDA MODELING

Sala de Graus, Campus ETSE/ETSEQ

Department of Electronic, Electrical and Automatic Control Engineering, 

University Rovira i Virgili Tarragona, Catalonia, Spain

Chairperson: 

Benjamin Iñiguez, EDS BoG Member and Chair of the ED Spain Chapter

Tuesday, June 28 2022

8:20-8:30 Overview, B. Iñiguez
8:30-9:30 “Characterization and TCAD modeling based design assessment of ultra-high voltage SiC devices,” Muhammad Nawaz (Hitachi Energy, Sweden)
9:30-10:30 “Nanoscale InGaAs FinFETs: Band-to-Band Tunneling and Ballistic Transport,” Jesús del Alamo (MIT, USA)

10:30-11:00 Coffee break

11:00-12:00 “Physics-Based Parameter Extraction for Thin Film Transistors,” Arokia Nathan (Darwin College, University of Cambridge, UK)
12:00-13:00; “Characterization and modeling of organic solar cells,” Lluís F. Marsal (University Rovira I Virgili, Tarragona, Spain)

13:00-15:00 Lunch

15:00-19:00 Meeting of the EDS SRC Region 8 Executive Committee

Wednesday, June 29 2022

11:00-12:00 “Trends and challenges in Nanoelectronics for the next decade,” Elena Gnani (University of Bologna, Italy)
12:00-13:00,“SPICE and Verilog-A Modelling Using FOSS TCAD/EDA Tools: Technology - Devices – Applications” (virtual), Wladek Grabinski (GMC, Switzerland)

13:00-14:20 Lunch

Joint Session 

• MQ on CAD Modeling
• Graduate Student Meeting on Electronic Engineering

14:20-14:30 Overview, B. Iñiguez and J. Ferré-Borrull
14:30-15:30 “Compact modeling of memristive devices for neuromorphic computing,” (virtual) Enrique Miranda (Autonomous University of Barcelona, Spain)
15:30-16:30 Physical Principles to Formulate Thin Film Transistor Models for Circuit Design (virtual), Samar Saha (Prospicient Devices, USA)

16:30-16:35 Closing remarks, B. Iñiguez

[webinar] "More Moore Roadmap" by IRDS and SINANO

IEEE EDS France, IRDS and the SINANO Institute will organize a Webinar 

"More Moore Roadmap"

by Mustafa Badaroglu 

IRDS-IFT More Moore Leader

The webinar will be held on 8th April 2021 at 16:00 Paris time. Interest participants please register via IEEE vTools by the following link: https://events.vtools.ieee.org/event/register/267103

Other Webinars of the IRDS Chapters will be announced in the EDS Newsletters

Joint Spring MOS-AK, SB-MOS and IEEE EDS MQ

Joint Spring MOS-AK Workshop and Symposium on Schottky Barrier MOS (SB-MOS) Devices

with IEEE EDS Mini-Colloquium on “Non-Conventional Devices and Technologies”

September 29 to October 1, 2020

THM Giessen (Germany)

—by Mike Schwarz— The Joint Spring MOS-AK Workshop and Symposium on Schottky Barrier MOS (SB-MOS) devices with IEEE EDS Mini-Colloquium on “Non-conventional Devices and Technologies” was held from September 29 to October 1, 2020. While it was initially planned for spring at THM—University of Applied Sciences in Giessen (Germany), it was shifted to the early autumn due to the COVID-19 pandemic. However, finally the local organizers of NanoP Competence Center for Nanotechnology and Photonics of THM decided to move it to Zoom and perform it virtually. It was sponsored by THM, the EDS Germany Chapter, the IEEE Young Professionals Germany Affinity Group, and the AdMOS company. The event was attended by 69 IEEE members and 115 non IEEE members (guests) from 25 countries during the three days [read more...]

[VIRTUAL] EDS MQ on Compact Modeling

VIRTUAL MINI-COLLOQUIUM ON COMPACT MODELING

IEEE EDS Compact Modeling Technical Committee

EDS Spain Chapter

Department of Electronic, Electrical and Automatic Control Engineering, 

University Rovira I Virgili, Tarragona (Spain)

December 17, 2020 EDS MQ Program (times in CET)
	10:20-10:30 Benjamin Iñiguez, IEEE EDS MQ Chair Department of Electronic, Electrical and Automatic Control Engineering, University Rovira I Virgili, Tarragona (Spain) Opening session
	10:30-11:15 Yogesh. S Chauhan Department of Electrical Engineering, Indian Institute of Technology Kanpur (India) “BSIM-BULK and BSIM-HV: Industry Standard SPICE Models for Analog, RFand High Voltage Applications”
	11:15-12:00 Manoj Saxena Department of Electronics, University of Delhi  (India) “Modeling and Simulation of Robust Ultrasensitive Tunnel Field Effect Transistor Design for Biosensing Applications”
	12·00-12:45 Wladek Grabinski GMC, Commugny (Switzerland) “FOSS TCAD/EDA Tools for Semiconductor Device Modeling”
	12:45-13:30 Arokia Nathan Darwin College, University of Cambridge (UK) “Physics-Based Parameter Extraction for TFTs”
	13:30-15:00 Break
	15:00-15:45 Marcelo Pavanello Department of Electrical Engineering, Centro Universitario FEI, Sao Bernardo do Campo (Brazil) "Quantum Effects on the Mobility of SOI Nanowire MOSFETs Induced by the Active Substrate Bias"
	15:45-16:30 Michael S. Shur Department of Electrical, Systems and Computer Engineering, Rensselaer Polytechnic Institute, Troy NY (USA) “THz Compact SPICE/ADS model”
	16:30-17:15 Edmundo Gutiérrez Department of Electronics, INAOE, Puebla (Mexico) "RF MOSFET degradation modeling up to 67 GHz”
	End of EDS MQ

IEEE EDS Golden List of Reviewers

Golden List of Reviewers for 2020

IEEE TED, Vol. 67, No. 12, Dec. 2020

Stat Data

Country	Reviewers
USA	559
China	286
India	159
Japan	151
S.Korea	121
Taiwan	111
Italy	102
Germany	90
United Kingdom	79
France	64
Belgium	63
Singapore	35
Switzerland	29
Austria	28
Spain	27
Hong Kong	25
Russia	22
Canada	22
Netherlands	19
Iran	14
Brazil	14
Turkey	12
Australia	12
Sweden	10
Poland	10
Greece	10
Saudi Arabia	8
Mexico	8
Israel	5
Ukraine	4
Slovakia	3
Portugal	3
Malaysia	3
Kazakhstan	3
Egypt	3
Algeria	2
Bulgaria	2
Denmark	2
Finland	2
Latvia	2
Lithuania	2
Qatar	2
Romania	2
Venezuela	2
Bangladesh	1
Belarus	1
Croatia	1
Czechia	1
Ireland	1
Kuwait	1
Lebanon	1
Macedonia	1
Slovenia	1
Tunisia	1
UAE	1

[paper] Editorial Special Section on ESSDERC

IEEE TED, Vol. 67, No. 11, November 2020

Mid-September 2020, we were supposed to celebrate in Grenoble the 50th anniversary of the European SolidState Device Research Conference and European Solid-State Circuits Conference (ESSDERC-ESSCIRC), which is the most important European conference dedicated to solid-state devices and circuits. However, in April 2020, more than one-third of the global population was under severe lock-down as a result of the protective public health measures imposed by the different governments, states, or provinces. Because of the COVID-19 pandemic, the ESSDERC-ESSCIRC organizing and steering committees, together with the sponsoring SSCS and EDS IEEE societies, decided to reschedule the in-person conference to September 6–9, 2021, in Grenoble, to add new virtual “Educational Events” held on September 14 and 15, 2020 (presentations available till October 16, 2020, at https://www.esscirc-essderc2020.org/) as well as to invite the ESSDERC-ESSCIRC research community to submit publications to the IEEE TRANSACTIONS ON ELECTRON DEVICES (TED) and to the IEEE SOLID-STATE CIRCUITS LETTERS (SSC-L), respectively, in a brief format. All of these initiatives met great success. Especially, more than 47 TED submissions were received and reviewed, and 32 papers were accepted and have been included in this dedicated section of the November TED issue.

We would like to thank all the authors for taking this opportunity to keep the ESSDERC-ESSCIRC momentum, all the IEEE reviewers for their reactivity, and all the ESSDERC-ESSCIRC sponsors for their trust in this difficult time. Let us think with a positive mind, and acknowledge that this experience opens a new and fruitful collaboration between ESSDERC and TED.

We hope you will enjoy reading these high-quality papers. Stay safe

FRANCOIS ANDRIEU, TPC Chair
CEA-Leti
Université Grenoble Alpes
38054 Grenoble, France

GIOVANNI GHIONE, Editor-in-Chief
Dipartimento di Elettronica e Telecomunicazioni
Politecnico di Torino
10129 Torino, Italy

Editorial Special Section on ESSDERC

 IEEE TED, Vol. 67, No. 11, November 2020

1. Generalized Constant Current Method for Determining MOSFET Threshold Voltage M. Bucher, N. Makris, and L. Chevas pp.4559
2. Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications (Invited Paper) B. Cardoso Paz, M. Cassé, C. Theodorou, G. Ghibaudo, T. Kammler, L. Pirro, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4563
3. A Method for Series-Resistance-Immune Extraction of Low-Frequency Noise Parameters in Nanoscale MOSFETs A. Tataridou, G. Ghibaudo, and C. Theodorou pp.4568
4. Analytical Model for Interface Traps-Dependent Back Bias Capability and Variability in Ultrathin Body and Box FDSOI MOSFETs W. Chen, L. Cai, X. Liu, and G. Du pp.4573
5. Polarization Independent Band Gaps in CMOS Back-End-of-Line for Monolithic High-Q MEMS Resonator Confinement R. Hudeczek and P. Baumgartner pp.4578
6. Out-of-Equilibrium Body Potential Measurement on Silicon-on-Insulator With Deposited Metal Contacts M. Alepidis, A. Bouchard, C. Delacour, M. Bawedin, and I. Ionica pp.4582
7. Evaluation of High-Temperature High-Frequency GaN-Based LC-Oscillator Components A. Ottaviani, P. Palacios, T. Zweipfennig, M. Alomari, C. Beckmann, D. Bierbüsse, J. Wieben, J. Ehrler, H. Kalisch, R. Negra, A. Vescan, and J. N. Burghartz pp.4587
8. Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs R. Y. ElKashlan, R. Rodriguez, S. Yadav, A. Khaled, U. Peralagu, A. Alian, N. Waldron, M. Zhao, P. Wambacq, B. Parvais, and N. Collaert pp.4592
9. Characterization and TCAD Modeling of Mixed-Mode Stress Induced by Impact Ionization in Scaled SiGe HBTs N. Zagni, F. M. Puglisi, G. Verzellesi, and P. Pavan pp.4597
10. Hot-Electron Effects in AlGaN/GaN HEMTs Under Semi-ON DC Stress A. Minetto, B. Deutschmann, N. Modolo, A. Nardo, M. Meneghini, E. Zanoni, L. Sayadi, G. Prechtl, S. Sicre, and O. Häberlen pp.4602
11. Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology S. Sugatani, N. Chujo, K. Sakui, H. Ryoson, T. Nakamura, and T. Ohba pp.4606
12. Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays T. Zanotti, C. Zambelli, F. M. Puglisi, V. Milo, E. Pérez, M. K. Mahadevaiah, O. G. Ossorio, C. Wenger, P. Pavan, P. Olivo, and D. Ielmini pp.4611
13. IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge D. Saito, J. Doevenspeck, S. Cosemans, H. Oh, M. Perumkunnil, I. A. Papistas, A. Belmonte, N. Rassoul, R. Delhougne, G. Kar, P. Debacker, A. Mallik, D. Verkest, and M. H. Na pp.4616
14. Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference Y. Luo, X. Han, Z. Ye, H. Barnaby, J.-s. Seo, and S. Yu pp.4621
15. Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications M. Ezzadeen, D. Bosch, B. Giraud, S. Barraud, J.-P. Noël, D. Lattard, J. Lacord, J. M. Portal, and F. Andrieu pp.4626
16. Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology S. M. Salahuddin, E. Dentoni Litta, A. Gupta, R. Ritzenthaler, M. Schaekers, J.-L. Everaert, H. Yu, A. Vandooren, J. Ryckaert, M.-H. Na, and A. Spessot pp.4631
17. Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: The Effect of Back Bias on Drain Current and Transconductance M. Cassé, B. Cardoso Paz, G. Ghibaudo, T. Poiroux, S. Barraud, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4636
18. Enhanced Ultraviolet Avalanche Photodiode With 640-nm-Thin Silicon Body Based on SOI Technology I. Sabri Alirezaei, N. Andre, and D. Flandre pp.4641
19. TCAD Study of VLD Termination in Large-Area Power Devices Featuring a DLC Passivation L. Balestra, S. Reggiani, A. Gnudi, E. Gnani, J. Dobrzynska, and J. Vobecký pp.4645
20. Analysis of MIS-HEMT Device Edge Behavior for GaN Technology Using New Differential Method R. Kom Kammeugne, C. Leroux, J. Cluzel, L. Vauche, C. Le Royer, R. Gwoziecki, J. Biscarrat, F. Gaillard, M. Charles, E. Bano, and G. Ghibaudo pp.4649
21. Influence of Substrate Resistivity on Porous Silicon Small-Signal RF Properties G. Godet, E. Augendre, J. Lugo-Alvarez, H. Jacquinot, F. X. Gaillard, T. Lorne, E. Rolland, T. Taris, and F. Servant pp.4654
22. Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs N. Makris, M. Bucher, L. Chevas, F. Jazaeri, and J.-M. Sallese pp.4658
23. Local Variability Evaluation on Effective Channel Length Extracted With Shift-and-Ratio Method J. P. Martinez Brito and S. Bampi pp.4662
24. Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors Due to Carrier-Number and Correlated-Mobility Fluctuation A. Nikolaou, G. Darbandy, J. Leise, J. Pruefer, J. W. Borchert, M. Geiger, H. Klauk, B. Iniguez, and A. Kloes pp.4667
25. Macromodel for AC and Transient Simulations of Organic Thin-Film Transistor Circuits Including Nonquasistatic Effects J. Leise, J. Pruefer, A. Nikolaou, G. Darbandy, H. Klauk, B. Iniguez, and A. Kloes pp.4672
26. Compact Modeling and Behavioral Simulation of an Optomechanical Sensor in Verilog-A H. Elmi Dawale, L. Sibeud, S. Regord, G. Jourdan, S. Hentz, and F. Badets pp.4677
27. TCAD Simulation Framework of Gas Desorption in CNT FET NO2 Sensors S. Carapezzi, S. Reggiani, E. Gnani, and A. Gnudi pp.4682
28. Conductance in a Nanoribbon of Topologically Insulating MoS2 in the 1T Phase V. Sverdlov, A.-M. B. El-Sayed, H. Kosina, and S. Selberherr pp.4687
29. Vt Extraction Methodologies Influence Process Induced Vt Variability: Does This Fact Still Hold for Advanced Technology Nodes? M. S. Bhoir, T. Chiarella, J. Mitard, N. Horiguchi, and N. R. Mohapatra pp.4691
30. Multidomain Negative Capacitance Effect in P(VDF-TrFE) Ferroelectric Capacitor and Passive Voltage Amplification K. J. Singh, A. Bulusu, and S. Dasgupta pp.4696
31. Monte Carlo Comparison of n-Type and p-Type Nanosheets With FinFETs: Effect of the Number of Sheets F. M. Bufler, D. Jang, G. Hellings, G. Eneman, P. Matagne, A. Spessot, and M. H. Na pp.4701
32. Impact of Width Scaling and Parasitic Series Resistance on the Performance of Silicene Nanoribbon MOSFETs M. Poljak pp.4705

IEEE Germany EDS Chapter Elections

The IEEE Germany EDS Chapter has elected new ExCom members for the term 2020/2021. An exciting new leadership team has been built to establish EDS activities in Germany.

The new ExCom:

• Chair: Mike Schwarz (TH Mittelhessen)
• Vice Chair: Joachim Burghartz (Universität Stuttgart, IMS Chips)
• Treasurer: Manfred Berroth (Universität Stuttgart)
• Secretary: Sevda Abadpour (Karlsruhe Institute of Technology)

Further information is available online https://r8.ieee.org/germany-eds

Congratulations to Prof. Robert W. Dutton

The 2020 IEEE EDS Celebrated Member and Esteemed EDS Alumni

Dr. Dutton received his degrees from the University of California, Berkeley, and currently instructs electrical engineering at Stanford University. Current members of EDS take pride in the Celebrated Members' accomplishments, drawing from their achievements as inspiration to advance and achieve success in various fields. The award presentation will be held virtually during the 2020 IEDM in December [read more...]

ROBERT W. DUTTON

Robert W. Dutton received the B.S., M.S., and Ph.D. in Electrical Engineering degrees from the University of California, Berkeley, in 1966, 1967, and 1970, respectively. 

He is currently Robert and Barbara Kleist Professor of Electrical Engineering at Stanford University, and Associate Chair for Undergraduate Education. He has held summer staff positions at Fairchild, Bell Telephone Laboratories, Hewlett‐Packard, IBM Research, and Matsushita during 1967, 1973, 1975, 1977, and 1988 respectively. His research interests focus on integrated circuit process, device, and circuit technologies, especially the use of computer‐aided design (CAD) and parallel computational methods. He has published more than 200 journal articles and graduated more than four dozen doctorate students. 

Dr. Dutton was Editor of the IEEE Transactions on Computer Aided Design from 1984 to 1986, the winner of the 1987 IEEE J. J. Ebers Award, 1988 Guggenheim Fellowship to study in Japan, elected to the National Academy of Engineering in 1991, 1996 Jack A. Morton Award, 2000 C&C Prize Japan, University Researcher Award, Semiconductor Industry Association (2000), Phil Kaufman Award, Electronic Design Automation Consortium (2006), and 2014 Bass University Fellow in Undergraduate Education Program, Stanford University.