- Continuation and advancement of hands-on semiconductor human resource development
- Providing opportunities for actual chip manufacturing and verification using NDA-free PDK
- Building a practical and highly reproducible education and implementation model through industry-academia integration
- In exchange for the cost support for this program, we will embed the company's logo on the prototype chip to spread awareness of semiconductor design human resource development as a social contribution activity
Apr 13, 2026
[OpenSUSI] Kicks off Five-Year Plan
Apr 10, 2026
[DATE2026] Open Source Related Talks
| Label | Title | Authors |
|---|---|---|
| TS02.8 | ML-DSA-OSH: An Efficient, Open-Source Hardware Implementation of ML-DSA | Quinten Norga; Suparna Kundu; Ingrid Verbauwhede |
| LK03 | Democratizing Silicon: The Rise of Open-Source EDA and Europe’s Strategic Roadmap | Luca Benini |
| TS10.1 | PICOSNN: Partially Incoherent Configurable Optical Computing Architecture for SNN Acceleration | Bowen Duan; Zhenhua Zhu; Zhengyang Duan; Huazhong Yang; Yuan Xie; Yu Wang |
| TS16.1 | Non-Volatile Spintronic Flip-Flops with Checkpoint Preservation Supported in RISC-V Platform | Jiongzhe Su; Mingtao Chen; Zhanpeng Qiu; Bo Liu; Hao Cai |
| LBR01.4 | Float Fight - Verifying Floating-Point Behavior In Risc-V Simulators | Katharina Ruep, Manfred Schlaegl and Daniel Grosse |
| LBR01.7 | Hybrid Virtual Platform + FPGA Co-Emulation Framework | Lorenzo Ruotolo; Giovanni Pollo; Mohamed Amine Hamdi; Matteo Risso; Yukai Chen; Enrico Macii; Massimo Poncino; Sara Vinco; Alessio Burrello; Daniele Jahier Pagliari |
| TS20.1 | Fault-Tolerance Mapping of Spiking Neural Networks to RRAM-Based Neuromorphic Hardware | Yuqing Xiong; Chao Xiao; Zhijie Yang; Lei Wang; Mengying Zhao |
| TS21.4 | Substrate: A Statically Typed Framework for Designing Highly Configurable Analog and Mixed-Signal Circuit Generators | Rahul Kumar; Rohan Kumar; Borivoje Nikolic |
| SD03 | Open-Source Hardware Landscape | |
| SD03.1 | Open Silicon Fabrication – Made in Europe | Gerhard Kahmen, IHP GmbH, DE |
| SD03.2 | From Schematic To Silicon: Mixed Signal Ic Design In Open Source Flows | Harald Pretl, JKU Linz, AT |
| SD03.3 | Bringing Software Design Thinking To Chip Design | Tomi Rantakari, ChipFlow, GB |
Mar 11, 2026
26th Workshop Analog Circuits
The workshop series offers a platform to present one's own ideas and discuss results with science and industry. The focus is on integrated analog and mixed-signal circuits.
If you have any questions, please contact the organizers by e-mail at: analog2026@ims.uni-hannover.de
Mar 2, 2026
Aalto Microelectronics Fair
| Time | Session |
|---|---|
| 8:30–9:00 | Morning coffee |
| 9:00–9:15 | Opening Aleksi Korsman |
| Keynotes | |
| 9:15–10:00 | Keynote 1: “OpenPDK - Global Scholar Platform”, Wladek Grabinski, Open PDK Initiative |
| 10:05–10:50 | Keynote 2: “Open Source Design Tools in SME IC Design Companies”, Ari Paasio, Kovilta |
| Research overviews | |
| 11:00–11:15 | Research overview: Kari Stadius |
| 11:15–11:30 | Research overview: Prof. Marko Kosunen |
| 11:30–11:45 | Research overview: Prof. Kwantae Kim |
| 11:45–12:45 | Lunch (and posters) |
| 12:45–13:15 | Student talk: “Five years of RISC‑V processor design at Aalto”, Aleksi Korsman |
| 13:15–13:45 | Student talk: “Beyond Neural Networks: Overcoming the Symbolic Bottleneck via Approximate Logarithm Acceleration”, Lingyun Yao |
| Posters | |
| 13:45–14:00 | Poster intro |
| 14:00–15:00 | Posters with coffee and snacks |
| 15:00–15:30 | Feedback and closing |
Should you have any questions, please email Marko Kosunen
Feb 4, 2026
[chapter] Compact/SPICE Modeling
Jul 1, 2025
[mos-ak] [OpenPDK] IHP Analog Academy
- Bandgap reference design and simulation using the gm/Id methodology- RF design of a 50 GHz Medium Power Amplifier with EM simulation- Mixed-signal integration and verification of an 8-bit SAR ADC
- More modules- Updated toolchain support- Improvements to existing flows
- Open PDK GitHub Repository https://github.com/IHP-GmbH/IHP-Open-PDK- Interactive Help via ChatGPT https://chat.openai.com
Apr 11, 2025
[C4P] ICEE 2025
Jan 20, 2025
[book] From Code to Chip
- Front Matter pp. i-xv
- Download chapter PDF
- Introduction pp. 1-4
- Theoretical Basics pp. 5-13
- Circuit Capturing pp. 15-36
- PDK—Design Rule Capturing pp. 37-41
- Placement pp. 43-55
- Routing pp. 57-71
- Experimental Results pp. 73-99
- Outlook pp. 101-103
- Back Matter pp. 105-120
Mar 17, 2024
SSCS April Technical Webinar
- https://zerotoasiccourse.com/
- https://tinytapeout.com
Feb 28, 2024
[FOSSDEM 2024] Open PDK Initiative
There were two DevRooms to discuss the status and further FOSS CAD/EDA IC design tools developments and open PDK initiative:
- Libre-SOC, FPGA and VLSI DevRoom
- Open Hardware and CAD/CAM DevRoom
Jan 5, 2024
ISHI-kai January 2024 event
ープンソースPDKやEDAの状況について、キーマンに語っていただきます
Schedule
Friday, January 26, 2024, 18:00-21:00 (Reception: 18:30)
Venue (onsite)
Google Shibuya Office
3-21-3 Shibuya, Shibuya-ku, Tokyo
Shibuya Stream Google reception meeting
Online Broadcast:
Google Meet: https://meet.google.com/ksa-tjaw-ges
Participation Fee
free
| Time | Speaker | Title | Lecture Outline |
|---|---|---|---|
| Until 18:30 | ISHI-kai | reception | The entrance to the facility closes at this time, so if you are participating locally, please come by this time as much as possible. |
| 18:00 ~ 18:30 | ISHI-kai | Chat time | - |
| 18:30 ~ 19:15 (Lecture: 30min, Q&A: 15min) | Takeshi Hamamoto Minimal Fab Propulsion Organization Device Engineer | minimal Fab open PDK | 1) What is a minimal fab 2) openPDK 3) Design Contest at Semicon 2023 |
| 19:15 ~ 20:00 (Lecture: 30min., Q&A: 15min.) | Junichi Okamura IEEE Senior Member | OpenPDK and the World | - |
| 20:00 ~ 20:45 (Lecture: 30min., Q&A: 15min.) | @noritsuna | About the upcoming open source PDK shuttle | (To be released at a later date) |
| 21:00 | ISHI-kai | closing |
Nov 21, 2023
[webinar] Open Source Silicon Landscape
- Policymakers at the regional, national, and European level who want to strengthen their respective semiconductor ecosystem while collaborating and contributing to the Union’s industry as a whole
- Research and academia representatives who are interested in deepening their knowledge or discovering the potential of the Open Source Silicon landscape
- SMEs in the semiconductor industry who aim to expand and innovate their business by using a cutting-edge approach
- Start-ups that are eager to elevate their business to the next level by embracing vanguard strategies
- Citizen scientists and the general public who would like to have a better understanding of the new horizons in the semiconductor landscape
- Experts active in industrial development who are interested in integrating potential new approaches
The event is free of charge, but registration is mandatory. Registrants will receive the link to access the event by email.
| 11:00 - 11:05 | Welcome |
| 11:05 - 11:10 | Introducing Open Source Silicon |
| 11:10 - 11:20 | BACKGROUND Open source silicon between software and hardware Background |
| 11:20 - 11:40 | POLICY BRIEF PRESENTATION Open source silicon’s position in the semiconductor value chain |
| 11:40 - 12:35 | PANEL Key opportunities and threats relevant to open source silicon strategies |
| 12:35 - 12:45 | Q&A and conclusions |
Aug 2, 2023
[video] Interviews from FSiC, Paris, 2023
Interviews with selected Free Silicon Conference Participation by Matt Venn are available online:
00:23 Luca Alloatti, FSiC Organizing Committee
01:59 Thomas Benz, ETH Zurich
06:05 Jørgen Kragh Jakobsen, IC Works - Open Source Chip Design
08:57 Thomas Parry, SPHERICAL
11:05 Rene Scholz, IHP Microelectronics
14:06 Dan Fritchman, UC Berkeley
18:41 Harald Pretl, Johannes Kepler University Linz
All the conference proceedings (slide presentations and prerecorded talks) are also available at the FSiC website.
May 26, 2023
[paper] Chip-Chat
May 11, 2023
OpenPDK Networking Workshop
Networking Workshop FMD-QNC on 27-28 June 2023
Location:
IHP; Im Technologiepark 25; 15236 Frankfurt (Oder)
Contact:
Sergei Andreev; Phone: +49 335 5625 523
|
Presentation |
Presenter/Institution |
Timeline |
|
Day 1 |
||
|
Welcome by coordinator FMD-QNC |
Dr. Andreas Bruning |
9:00-9:10 |
|
Introduction FMD-QNC project status and IHP OpenPDK Roadmap |
Dr. Rene Scholz |
9:10-9:30 |
|
Status OpenPDK and OpenTooling for SG13G2 BiCMOS technology |
Sergei Andreev |
9:30-10:00 |
|
An Ultra-Low-Power High-Density Wireless Biomedical Sensing System
|
Prof. Harald Pretl |
10:00-10:30 |
|
Teaching digital design by using open-source EDA tools |
Prof. Steffen Reith |
10:30-11:00 |
|
Coffee break |
11:00-11:40 |
|
|
CMOS Rail-to-Rail Operational Amplifier for HPGe Radiation Detector |
Prof. Herman Jalli Ng |
11:40-12:10 |
|
Design-flow approaches for mmWave and sub-THz integrated transceiver circuits for radar and communication |
Sasha Breun
|
12:10-12:40 |
|
Lunch break |
12:40-13:40 |
|
|
TBD |
Dr. Frank K. Gurkaynak |
13:40-14:10 |
|
TBD |
Joachim Hebeler |
14:10-14:40 |
|
Coffee break |
14:40-15:10 |
|
|
TBD |
Prof.
Dietmar Kissinger |
15:10-15:40 |
|
LibMan - an easy way to manage your open source design flow |
Dr. Anton Datsuk |
15:40-16:10 |
|
Get together (Barbecue) |
|
17:00-… |
|
Day 2 |
||
|
ngspice - status and future developments |
Prof. Holger Vogt |
9:00-9:20 |
|
DMT - Python Toolkit for Device Modeling |
Mario Krattenmacher |
9:20-9:40 |
|
OpenVAF - Next Generation Verilog-A Compiler with ngspice integration |
Mario Krattenmacher |
9:40-10:00 |
|
Coffee break |
10:00-10:40 |
|
|
Best practices for implementing and optimizing KLayout DRC and LVS decks |
Matthias Köfferlein |
10:40-11:00 |
|
Generating DRC and LVS Runsets for KLayout |
Dr. Andreas Krinke |
11:00-11:20 |
|
OpenEMS in open source EDA |
Jan Taro Svejda |
11:20-11:40 |
|
Lunch break |
11:40-12:40 |
|
|
Panel discussion on the roadmap – open source tools for IC design Topics:
|
Dr. Norbert Herfurth Panelists: TBD |
12:40-14:10 |
Apr 6, 2023
[Deadline] #TinyTapeout 3
#TinyTapeout and #SiliWiz are online tools you can use to learn how ASICs are designed, made and how they work. You can even get your designs affordably manufactured!
Matt Venn has some free slots for #TinyTapeout 3 for you and your students - just send him a DM to get started!
Deadline is 24th April! Apply today at https://tinytapeout.com/
Mar 22, 2023
[analog-wg] Video of March 21 AWG Meeting
The AWG Video Meeting on March 21, 2023 included two presentations:
- Ken Kundert "Why Fund OpenVAF"
- Pascal Kuthe "OpenVAF: An innovative open-source Verilog-A Compiler"
|
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|
- 4th April: Update from Tim Edwards: Magic and PEX extraction
- 18th April: Update from Sadayuki Yoshitomi: Ecosystem of compact model development
- 2nd May (tentative): Update from C. Enz,EPFL: test structures measurements
Jan 24, 2023
Mixed Signal SoC design Marathon using eSim & SKY130
Marathon Date : 23 Sept. - 8 Oct. 2022
The following submissions are adjudged as Outstanding, Excellent, Very good and Good by the FOSSEE and the VSD teams.
List of Outstanding Circuits:
| # | Participant | Circuit | Institute | GitHub |
|---|---|---|---|---|
| 1 | Milad Vafaieenezhad | Window Comparator Along with MOD-16 Counter for Counting Based Data Line Selection Operation | Shahed University | View Repo |
| 2 | Krunal Badlani | Crack Sensing Circuit | Indian Institute of Technology Hyderabad | View Repo |
| 3 | Karuppusamy V | Flash Type ADC | Bannari Amman Institute of Technology | View Repo |
| 4 | Inderjit Singh Dhanjal | 32-bit SRAM implementation in eSim using Skywater 130nm CMOS technology | K. J. Somaiya College of Engineering | View Repo |
| 5 | Tanay Das | Design of a Class D Audio Amplifier IC Using Sliding Mode Control and Negative Feedback | Sikkim Manipal Institute of Technology | View Repo |
| 6 | Jayanth Nedunuri | Implementation of 4 bit Two Step Flash ADC | Jyothishmathi institute of Technology and Science | View Repo |
| 7 | Aishwarya Balkrishna Patil | Design and Implementation of Automatic Security Monitoring System | Kolhapur Institute of Technology’s College of Engineering, Kolhapur | View Repo |
| 8 | Swagatika Meher | 3-bit CMOS based TIQ comparator Flash ADC | Odisha University of Technology and Research, Bhubaneswar, Odisha | View Repo |
| 9 | Surya V | 3-bit Flash ADC using ROM-based Encoder | National Institute of Technology, Tiruchirapalli | View Repo |
| 10 | Sanket M Mantrashetti | Design of 8x8 SRAM based on 6T SRAM cell | R. V. College of Engineering | View Repo |
| 11 | Avishek Choudhary | 10-bit C2C DAC | Thapar Institute of Engineering and Technology | View Repo |
| 12 | Nalinkumar S | Implementation of Quadruple - Window Comparator Along with Prioritized MOD-16 Counter for Data Line Multiplexing Operation | Madras Institute of Technology Campus, Anna University | View Repo |
| 13 | Rubankumar D | Astable Multivibrator Along with MOD-16 Counter for Counting Based Data Line Selection Operation | Madras Institute of Technology Campus, Anna University | View Repo |
| 14 | Vanshika Tanwar | Implementation of 3 Bit Flash ADC performed in eSim | Dronacharya Group Of Institutions, Greater Noida | View Repo |
| 15 | Ravi Prakash Vishwakarma | 8 Bit Counter/Ramp Type ADC | Madan Mohan Malaviya University Of Technology | View Repo |
| 16 | E Balakrishna | Implementation of 4 Bit Flash ADC mixed signal circuit using 130nm performed in eSim | Dronacharya Group of Institution, Greater Noida | View Repo |
Contact eSim-fossee:
For more information about the marathon, write to us at contact-esim[at]fossee[dot]in











