SSCS April Technical Webinar

SSCS April Technical Webinar

Getting Started with Open Source Silicon, Presented By: Matthew Venn

Abstract: In this presentation, Matt Venn will share his experience of getting started with chip design using the free and open source tools. Going from zero to 20 chips in 3 years, there are plenty of successes and failures to share. Matt will then move on to sharing the best resources, inspirational example projects, and showcase some of his own tools. The presentation will finish with a demonstration showing just how easy and cheap it is to get your own chip manufactured today.

Biography: Matt Venn is a science & technology communicator and electronic engineer. He has been involved with open source silicon for the last 3 years and has sent 20 chips for manufacture. He has helped over 600 people learn the tools, with 300 people taking part in manufacturable designs:

• https://zerotoasiccourse.com/
• https://tinytapeout.com

Date: 2024-04-19 Time: 11 AM ET

Location Webinar - Online

Contact Aeisha VanBuskirk – a.vanbuskirk@ieee.org

Register Here

[FOSSDEM 2024] Open PDK Initiative

FOSDEM 2024 was a two-day event organized by volunteers to promote the widespread use of free and open source software. Took place at the ULB Solbosch campus in the beautiful city of Brussels (Belgium), FOSDEM is widely recognized as the best FOSS conference in Europe.

There were two DevRooms to discuss the status and further FOSS CAD/EDA IC design tools developments and open PDK initiative:

• Libre-SOC, FPGA and VLSI DevRoom
• Verilog-AMS in Gnucap
• FOSS CAD/EDA tools supporting the open access PDK initiative
• Open Hardware and CAD/CAM DevRoom
• ngspice circuit simulator - stand-alone and embedded into KiCad

FOSDEM'24 Inauguration Session

ISHI-kai January 2024 event

2024年1月イベント「オープンソースPDK団体」勉強会国内外のオ
ープンソースPDKやEDAの状況について、キーマンに語っていただきます

With the recent rise in the semiconductor industry, the movement of open source PDK and EDA in Japan and overseas has become active. Therefore, in this study session, key people will talk about the status of open source PDK and EDA in Japan and overseas.

Schedule

Friday, January 26, 2024, 18:00-21:00 (Reception: 18:30)

Venue (onsite)

Google Shibuya Office
3-21-3 Shibuya, Shibuya-ku, Tokyo
Shibuya Stream Google reception meeting

Online Broadcast: 

Google Meet: https://meet.google.com/ksa-tjaw-ges

Participation Fee

free

Timetable

Time	Speaker	Title	Lecture Outline
Until 18:30	ISHI-kai	reception	The entrance to the facility closes at this time, so if you are participating locally, please come by this time as much as possible.
18:00 ～ 18:30	ISHI-kai	Chat time	-
18:30 ~ 19:15 (Lecture: 30min, Q&A: 15min)	Takeshi Hamamoto Minimal Fab Propulsion Organization Device Engineer	minimal Fab open PDK	1) What is a minimal fab 2) openPDK 3) Design Contest at Semicon 2023
19:15 ~ 20:00 (Lecture: 30min., Q&A: 15min.)	Junichi Okamura IEEE Senior Member	OpenPDK and the World	-
20:00 ~ 20:45 (Lecture: 30min., Q&A: 15min.)	@noritsuna	About the upcoming open source PDK shuttle	(To be released at a later date)
21:00	ISHI-kai	closing

What is ISHI-kai?

The association was named ISHI-kai (Inter-linked Society on Homemade IC Kai). The name was conceived from the Society Community (Association) that handles open (democratized) ISHI = stone = Silicon = semiconductors (ASIC/LSI/IC) and connects various fields.

OpenMPW (Open Multi Project Wafer), which appeared as a forerunner, is a shuttle program created by Google investing in Efabless, and includes the tools necessary for making semiconductors (ASIC/LSI/IC) (EDA/PDK) to ISHI manufacturing in IC fabs). This is exactly the "openness of semiconductors (ASIC/LSI/IC) and EDA/PDK" of the open source movement (democratization of software) that started with GNU!

Therefore, this association was established as a user society community (association) that focuses not only on experts in semiconductors (ASIC/LSI/IC) in the past, but also on those who see the potential of the open source movement of semiconductors (ASIC/LSI/IC) in the future and those who want to create new semiconductors (ASIC/LSI/IC).

We/ISHI-kai will continue to work toward a world where semiconductors (ASIC/LSI/IC) and EDA/PDK can be used by everyone, just as OSs, compilers, libraries, apps, electronic boards, 3D CAD and 3D printers that we/ISHI-kaire only available to experts can now be used by everyone as open source software, open hardware, open modeling, etc.

As for the future activity plan, we/ISHI-kai have a policy of revolutionizing the semiconductor (ASIC/LSI/IC) field by involving people from other fields, and we/ISHI-kai will hold events such as hands-on seminars for ultra-beginners for other fields and in-depth study sessions for experts, form a team to challenge the OpenMPW shuttle and Chipathon from around the world, and Maker we/ISHI-kai would like to participate in events such as Faire, so thank you.

Precautions

As events move online, we/ISHI-kai ask participants to act in accordance with the spirit of the Code of Conduct. If you have any problems, please contact the organizer. If it is judged that there is no improvement in the request even if there is no abuse such as vandalism or malicious intent, we/ISHI-kai may respond on a case-by-case basis. 

https://www.contributor-covenant.org/ja/version/2/0/code_of_conduct/

Acknowledgements

Thanks to the kindness of Google for providing a real/onsite venue.

[webinar] Open Source Silicon Landscape

Unveiling the Open Source Silicon Landscape: 

a cutting-edge approach for the European semiconductor industry

5 December 2023

Who should attend and why:

• Policymakers at the regional, national, and European level who want to strengthen their respective semiconductor ecosystem while collaborating and contributing to the Union’s industry as a whole
• Research and academia representatives who are interested in deepening their knowledge or discovering the potential of the Open Source Silicon landscape
• SMEs in the semiconductor industry who aim to expand and innovate their business by using a cutting-edge approach
• Start-ups that are eager to elevate their business to the next level by embracing vanguard strategies
• Citizen scientists and the general public who would like to have a better understanding of the new horizons in the semiconductor landscape
• Experts active in industrial development who are interested in integrating potential new approaches

Registration:

The event is free of charge, but registration is mandatory. Registrants will receive the link to access the event by email.

Agenda:

11:00 - 11:05	Welcome
11:05 - 11:10	Introducing Open Source Silicon
11:10 - 11:20	BACKGROUND Open source silicon between software and hardware Background
11:20 - 11:40	POLICY BRIEF PRESENTATION Open source silicon’s position in the semiconductor value chain
11:40 - 12:35	PANEL Key opportunities and threats relevant to open source silicon strategies
12:35 - 12:45	Q&A and conclusions

[video] Interviews from FSiC, Paris, 2023

Interviews from the Free Silicon Conference, Paris, 2023

The 2023 Free Silicon Conference (FSiC) took place in Paris (Sorbonne Université, 4 Place Jussieu, Paris) on July 10 - 12 2023 (Monday to Wednesday). The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification.

Interviews with selected Free Silicon Conference Participation by Matt Venn are available online:

00:00 FSiC 2023 Intro, Matt Venn

00:23 Luca Alloatti, FSiC Organizing Committee

01:59 Thomas Benz, ETH Zurich

06:05 Jørgen Kragh Jakobsen, IC Works - Open Source Chip Design

08:57 Thomas Parry, SPHERICAL

11:05 Rene Scholz, IHP Microelectronics

14:06 Dan Fritchman, UC Berkeley
18:41 Harald Pretl, Johannes Kepler University Linz

All the conference proceedings (slide presentations and prerecorded talks) are also available at the FSiC website.

[paper] Chip-Chat

Jason Blocklove, Siddharth Garg, Ramesh Karri, and Hammond Pearce^

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design

arXiv preprint arXiv:2305.13243 [cs.LG] 22 May 2023

New York University, NY USA

^University of New South Wales Sydney, Australia

Abstract: Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before synthesizing circuit elements. Automating this translation could reduce sources of human error from the engineering process. But, it is only recently that artificial intelligence (AI) has demonstrated capabilities for machine-based end-to-end design translations. Commercially available instruction-tuned Large Language Models (LLMs) such as OpenAI’s ChatGPT and Google’s Bard claim to be able to produce code in a variety of programming languages; but studies examining them for hardware are still lacking. In this work, we thus explore the challenges faced and opportunities presented when leveraging these recent advances in LLMs for hardware design. Using a suite of 8 representative benchmarks, we examined the capabilities and limitations of the state of the art conversational LLMs when producing Verilog for functional and verification purposes. Given that the LLMs performed best when used interactively, we then performed a longer, fully conversational case study where a hardware engineer co-designed a novel 8-bit accumulator-based microprocessor architecture. We sent the benchmarks and processor to tapeout in a Skywater 130nm shuttle, meaning that these ‘Chip-Chats’ resulted in what we believe to be the world’s first wholly-AI-written HDL for tapeout.

Fig: Processor synthesis information - Above (a) Components. Left: (b) Final processorGDS render by ‘kLayout’, I/O ports on left side, grid lines = 0.001 um.

Opportunities: Still, when the human feedback is provided to the more capable ChatGPT-4 model, or it is used to co-design, the language model seems to be a ‘force multiplier’, allowing for rapid design space exploration and iteration. In general, ChatGPT-4 could produce functionally correct code, which could free up designer time when implementing common modules. Potential future work could involve a larger user study to investigate this potential, as well as the development of conversational LLMs specific to hardware design to improve upon the results.

OpenPDK Networking Workshop

OpenPDK, OpenTooling and Open Source Design

An Initiative to Push Development

Date:
Networking Workshop FMD-QNC on 27-28 June 2023
Location:
IHP; Im Technologiepark 25; 15236 Frankfurt (Oder)
Contact:
Sergei Andreev; Phone: +49 335 5625 523

Free Registration: 

OnLine

The workshop is organised by IHP and FMD (Research Fab Microelectronics Germany) within the framework of the FMD-QNC Project.

Within the project FMD-QNC analog circuit design with open source software shall be enabled. For this purpose, both the open source design tools and a process design kit of the semiconductor technology used must support the entire design flow with sufficient quality. IHP provides its 130 nm BiCMOS technology SG13G2 for open source design. This technology is particularly suited for high frequency and mixed signal design applications. While basic tool support already exists for digital circuit design, it is still very rudimentary for analog designs and especially for high frequency designs. A considerable effort has to be put into the development of the design tools as well as into the creation of the technology specific Process Design Kit (PDK).

The 2-day workshop is intended to promote exchange and networking between tool developers, the PDK developers at IHP and designers. Tool developers are to present the capabilities of the tools as well as planned enhancements. Designers are to present ideas that can be used for training chip designers. Requirements for open source design tools for digital design, mixed signal design, and high frequency design are to be highlighted.

Discussions will identify and prioritize gaps for a complete design flow in the open source tools and PDK. The workshop will thus help to concrete the planning for the Open Design Platform and to create a roadmap for future work.

Presentation	Presenter/Institution	Timeline
Day 1
Welcome by coordinator FMD-QNC	Dr. Andreas Bruning Research Fab Microelectronics Germany	9:00-9:10
Introduction FMD-QNC project status and IHP OpenPDK Roadmap	Dr. Rene Scholz IHP	9:10-9:30
Status OpenPDK and OpenTooling for SG13G2 BiCMOS technology	Sergei Andreev IHP	9:30-10:00
An Ultra-Low-Power High-Density Wireless Biomedical Sensing System	Prof. Harald Pretl Johannes Kepler University Linz	10:00-10:30
Teaching digital design by using open-source EDA tools	Prof. Steffen Reith Rhein Main University of Applied Sciences	10:30-11:00
Coffee break		11:00-11:40
CMOS Rail-to-Rail Operational Amplifier for HPGe Radiation Detector	Prof. Herman Jalli Ng Karlsruhe University of Applied Sciences	11:40-12:10
Design-flow approaches for mmWave and sub-THz integrated transceiver circuits for radar and communication	Sasha Breun FAU Erlangen	12:10-12:40
Lunch break		12:40-13:40
TBD	Dr. Frank K. Gurkaynak ETH Zurich	13:40-14:10
TBD	Joachim Hebeler Karlsruhe Institute of Technology	14:10-14:40
Coffee break		14:40-15:10
TBD	Prof.  Dietmar Kissinger Ulm University	15:10-15:40
LibMan - an easy way to manage your open source design flow	Dr. Anton Datsuk IHP	15:40-16:10
Get together (Barbecue)		17:00-…
Day 2
ngspice - status and future developments	Prof. Holger Vogt	9:00-9:20
DMT - Python Toolkit for Device Modeling	Mario Krattenmacher SemiMod	9:20-9:40
OpenVAF - Next Generation Verilog-A Compiler with ngspice integration	Mario Krattenmacher SemiMod	9:40-10:00
Coffee break		10:00-10:40
Best practices for implementing and optimizing KLayout DRC and LVS decks	Matthias Köfferlein	10:40-11:00
Generating DRC and LVS Runsets for KLayout	Dr. Andreas Krinke TU Dresden	11:00-11:20
OpenEMS in open source EDA	Jan Taro Svejda University of Duisburg-Essen	11:20-11:40
Lunch break		11:40-12:40
Panel discussion on the roadmap – open source tools for IC design Topics: Digital design flow Analog design flow Challenges in RF design	Dr. Norbert Herfurth IHP Panelists: TBD	12:40-14:10

[Deadline] #TinyTapeout 3

Are you a #teacher and interested in microelectronics?

Visit https://tinytapeout.com/

#TinyTapeout and #SiliWiz are online tools you can use to learn how ASICs are designed, made and how they work. You can even get your designs affordably manufactured!

Matt Venn has some free slots for #TinyTapeout 3 for you and your students - just send him a DM to get started!

Deadline is 24th April! Apply today at https://tinytapeout.com/

[analog-wg] Video of March 21 AWG Meeting

The Analog Workgroup (AWG) was formed by the CHIPS Alliance TSC to explore collaborations in open source Analog/Mixed-Signal design and verification. It focuses on sharing best practices, ideas, tooling (analog automation), and other challenge areas in the design space. The workgroup is composed of both industry and university members.

The AWG Video Meeting on March 21, 2023 included two presentations:

• Ken Kundert "Why Fund OpenVAF"
• Pascal Kuthe "OpenVAF: An innovative open-source Verilog-A Compiler"

Please note the following line of topics for the Analog Workgroup

• 4th April: Update from Tim Edwards: Magic and PEX extraction
• 18th April: Update from Sadayuki Yoshitomi: Ecosystem of compact model development 
• 2nd May (tentative): Update from C. Enz,EPFL:  test structures measurements

Mixed Signal SoC design Marathon using eSim & SKY130

Marathon Date : 23 Sept. - 8 Oct. 2022

The following submissions are adjudged as Outstanding, Excellent, Very good and Good by the FOSSEE and the VSD teams.

• Outstanding
• Excellent
• Very Good
• Good

List of Outstanding Circuits:

#	Participant	Circuit	Institute	GitHub
1	Milad Vafaieenezhad	Window Comparator Along with MOD-16 Counter for Counting Based Data Line Selection Operation	Shahed University	View Repo
2	Krunal Badlani	Crack Sensing Circuit	Indian Institute of Technology Hyderabad	View Repo
3	Karuppusamy V	Flash Type ADC	Bannari Amman Institute of Technology	View Repo
4	Inderjit Singh Dhanjal	32-bit SRAM implementation in eSim using Skywater 130nm CMOS technology	K. J. Somaiya College of Engineering	View Repo
5	Tanay Das	Design of a Class D Audio Amplifier IC Using Sliding Mode Control and Negative Feedback	Sikkim Manipal Institute of Technology	View Repo
6	Jayanth Nedunuri	Implementation of 4 bit Two Step Flash ADC	Jyothishmathi institute of Technology and Science	View Repo
7	Aishwarya Balkrishna Patil	Design and Implementation of Automatic Security Monitoring System	Kolhapur Institute of Technology’s College of Engineering, Kolhapur	View Repo
8	Swagatika Meher	3-bit CMOS based TIQ comparator Flash ADC	Odisha University of Technology and Research, Bhubaneswar, Odisha	View Repo
9	Surya V	3-bit Flash ADC using ROM-based Encoder	National Institute of Technology, Tiruchirapalli	View Repo
10	Sanket M Mantrashetti	Design of 8x8 SRAM based on 6T SRAM cell	R. V. College of Engineering	View Repo
11	Avishek Choudhary	10-bit C2C DAC	Thapar Institute of Engineering and Technology	View Repo
12	Nalinkumar S	Implementation of Quadruple - Window Comparator Along with Prioritized MOD-16 Counter for Data Line Multiplexing Operation	Madras Institute of Technology Campus, Anna University	View Repo
13	Rubankumar D	Astable Multivibrator Along with MOD-16 Counter for Counting Based Data Line Selection Operation	Madras Institute of Technology Campus, Anna University	View Repo
14	Vanshika Tanwar	Implementation of 3 Bit Flash ADC performed in eSim	Dronacharya Group Of Institutions, Greater Noida	View Repo
15	Ravi Prakash Vishwakarma	8 Bit Counter/Ramp Type ADC	Madan Mohan Malaviya University Of Technology	View Repo
16	E Balakrishna	Implementation of 4 Bit Flash ADC mixed signal circuit using 130nm performed in eSim	Dronacharya Group of Institution, Greater Noida	View Repo

Contact eSim-fossee:
For more information about the marathon, write to us at contact-esim[at]fossee[dot]in

[Special Issue] ACM Transactions on Machine Learning for CAD / EDA

ACM Transactions on Design Automation of Electronic Systems

Special Issue on Machine Learning for CAD / EDA 

Guest Editors: 

• Yibo Lin, Peking University

• Avi Ziv, IBM Research, Haifa, Israel

• Haoxing Ren, NVIDIA Corp.

Advances in Machine Learning (ML) over the past half-dozen years have revolutionized the effectiveness of ML for a variety of applications. However, design processes present challenges that require parallel advances in ML and CAD as compared to traditional ML applications such as image classification. 

This special issue seeks original submission on ML applications to the entire design flow - including ML applications to validation and test. The application of machine learning to mask preparation and layout generation are topics which are seeing very active research recently. ML is also being applied to improve the robustness of integrated circuits and systems. Power and thermal management are probably the most important limiting factors for ICs today - ML-based techniques are being explored to address this bottleneck. All these topics, as well as further potential topics mentioned below, are of interest to this special issue. In addition to submissions from academia, submissions from industry are much welcome. 

Topics of interest to this special issue include, but not limited to, the following:

• ML for system-level design

• ML approaches to logic design and synthesis

• ML for timing

• ML for clock networks and power grids

• ML for variation-aware design, analysis and optimization

• ML for physical design

• ML for analog design

• ML for power and thermal management

• ML for Design Technology Co-Optimization (DTCO)

• ML methods to predict aging and reliability

• Labeled and unlabeled data in ML for CAD

• ML techniques for resource management in many cores

• ML for verification and validation

• ML for test

• ML for library design and optimization 

Important Dates:

• Submissions deadline: February 15, 2022

• First-round review decisions: April 15, 2022

• Deadline for revision submissions: May 15, 2022

• Notification of final decisions: June 15, 2022

• Tentative publication: Summer 2022 

Submission Information: 

Authors are encouraged to submit high-quality original research contributions. Please clearly identify the additional material from any original conference or workshop paper in your submitted manuscript. Submissions should be made through the ACM TODAES submission site (http://mc.manuscriptcentral.com/todaes) and formatted according to TODAES author guidelines at: https://dl.acm.org/journal/todaes/author-guidelines. Select the paper type “Special Issue on Machine Learning for CAD/EDA.” 

For questions and further information, please contact guest editors at:

• Yibo Lin

• Avi Ziv

• Haoxing Ren

Guardian of Verilog-A Compact Models

on 02/02/2020, Geoffrey Coram, Staff CAD Engineer at Analog Devices and Verilog-A Recommended Practices CMC Chair was honored by Prof. Chenming Hu and the BSIM Group at UC Berkeley, naming him as "Guardian of Verilog-A Compact Models for the Global Semiconductor Industry"

10th All-Russia MES-2021 Conference

10th All-Russia Science and Technology Conference

Problems of Advanced Micro- and Nanoelectronic Systems Development 

MES-2021

March - November 2021

Moscow | Zelenograd

MES-2021 is dedicated to urgent issues of design automation of microelectronic systems, SoC, IP-blocks and a new element base of micro-and nanoelectronics. These issues have been and remain actual to science and technology, as evidenced by the major topics of the Annual International Conference on CAD and the development of micro-and nanoelectronic devices. MES is the largest conference in the field of CAD microelectronics in Russia and CIS countries. Proceedings of the MES conference is included in HAC list (issue 23.03.2021, pos. 2017) of Russian scientific journals, where should be published the main results of the PhD and DSc theses.

The upcoming 10th MES-2021 conference will be held mainly in the correspondence format, starting on March 01, 2021, and it will be concluded with its plenary session in November 2021.

Key discussion topics

1. Theoretical aspects of micro-and nanoelectronic systems (MES).
2. Methods and tools of design automation for micro-and nanoelectronic circuits and systems (VLSI CAD).
3. Experience of development of digital, analog, digital to analog, radio functional blocks of VLSI.
4. Features of VLSI design for nanometer technologies.
5. SoCs for advanced radioelectronic equipment.
6. Exhibition and presentation of commercial products.

Fields of interest of the conference include (but is not limited to) the following topics of relevant studies of VLSI design and VLSI design automation techniques:

Design

1. Circuits and Systems based on nanometer technologies

2. Systems on Chip

3. Digital VLSI Design

4. Design of analog functional blocks and radio VLSI

5. Design of mixed-signal VLSI

6. Methods of structural synthesis of analog, digital and mixed VLSI and complex functional blocks

7. Specialized (resistant to special effects, photosensitivity, etc.) VLSI

Simulation

1. Methods of simulation of digital, analog and mixed circuits and systems

2. Methods for radio VLSI simulation

3. Structural, logical, circuit, mixed and layout simulation

4. Methods for generating models and macromodels for VLSI CAD

5. Device and Technology simulation

6. Behavioral simulation

Information processing methods

1. Information coding

2. Digital data processing

3. Use of artificial intelligence methods, neural networks, etc. in micro- and nanoelectronic system designs

4. Unconventional arithmetic

5. High-performance computers

The development of nanoelectronic systems on new principles

1. Nanomagnetic storage devices

2. Magnetosensor structures

Call for participation in the conference program

I stage - After registration at least one of the co-authors of the report one can send an article. To do this, using their registration data, please log in (see upper right corner of screen). Fill in all required fields. On the website you should send a file containing the main text of the article (in Russian or English) and an extended abstract in English (if the main text is in Russian) or a simple abstract in Russian (if the main text of the article in English). Requirements for the articles sent to MES.

II stage - sending additional documents only for the articles, which have been reviewed and accepted to the conference program.

Visit the 10th MES-2021 conference website at: http://www.mes-conference.ru/index.php

7th All-Russian Workshop on CAD of IC Design

7th All-Russian Workshop on computer aided design (CAD) of integrated circuits (IC) to be held at NRNU MEPhI on December 12-14, 2017. The free workshop is organized by NRNU MEPhI jointly with Cadence Design Systems. The program and further information about the Workshop is available via site cad.mephi.ru.

Program 

(with timetable and detailed information in pdf format)

12 December 2017

08:45 - 09:15	Registration (University entrance)
09:30 - 13:00	Conference hall 3rd floor of the main lecture building
	- Synthesis in Genus (28nm technology)
	- Introduction to Joules
	- Innovus 17.1 Topical Introduction
13:00 - 14:00	Lunch break
14:00 - 18:15	Conference hall 3rd floor of the main lecture building
	- Introduction to Stylus
	- Physical verification with the help of PVS
	- A new generation of verification software - Xcelium and Indago
	- The history and future of megatrends in EDA

13 December 2017

9:00 - 18:00	Laboratory V-315 of the Department of Electronics (Practical classes)
	- Behavioral modeling
	- Logical synthesis
	- Simulation of a Verilog modules with element delays
	- Physical design of the digital modules
	- Verification of the digital modules

14 December 2017

10:00 - 12:00	Laboratory V-315 of the Department of Electronics
	- Working discussions, summarizing

Contact Event Secretary: E. Atkin
+7 495 7885699 ext. 9155
+7 499 3242597