May 31, 2021

May 26, 2021

[Review] Nanosheet Transistors Technology

Firas N. A. Hassan Agha1, Yasir H. Naif2, Mohammed N. Shakib3
Review of Nanosheet Transistors Technology
Tikrit Journal of Engineering Sciences (2021) 28 (1): 40-48
ISSN: 1813-162X (Print) ; 2312-7589 (Online)
DOI: http://doi.org/10.25 30/tjes.28.1.05
available online at: http://www.tj-es.com

1Electrical Department/ Engineering College; Mosul University; Mosul, Iraq
2Department of Computer Engineering; Faculty of Engineering, Tishk; International University; Erbil, Iraq
3Faculty of Electrical and Electronics; Engineering Technology, University; Malaysia Pahang; Pekan, Malaysia


Abstract: Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nano-dimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).
Fig: Development of Field Effect Transistor from FinFET to MBCFET [Credit: Samsung]

Acknowledgment: The authors would like to thank University of Mosul for their support.


Principles, Applications, And The Future Of #Piezoelectric #MEMS https://t.co/1tVZd6d9xI #semi https://t.co/vgcNu4WGpt



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May 25, 2021

Global #200mm #Fab Capacity on Pace to Record Growth



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May 25, 2021 at 08:28PM
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#US #chip stimulus could unlock $150 billion, create 10 #fabs



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May 25, 2021 at 02:37PM
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[papers] Aging and Device Reliability Compact Modeling

IEEE International Reliability Physics Symposium
(IRPS 2021)

[1] N. Chatterjee, J. Ortega, I. Meric, P. Xiao and I. Tsameret, "Machine Learning On Transistor Aging Data: Test Time Reduction and Modeling for Novel Devices," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-9, doi: 10.1109/IRPS46558.2021.9405188.

Abstract: Accurately modeling the I-V characteristics and current degradation for transistors is central to predicting circuit end-of-life behavior. In this work, we propose a machine learning model to accurately model current degradation at various stress conditions and extend that to make nominal use-bias predictions. The model can be extended to track and predict any parametric change. We show an excellent agreement of the model with experimental results. Furthermore, we use a deep neural network to model the I-V characteristics of aged transistors over a wide drain and gate playback bias range and show an excellent agreement with experimental results. We show that the model is reliably able to interpolate and extrapolate demonstrating that it learns the underlying functional form of the data.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405188&isnumber=9405088

[2] P. B. Vyas et al., "Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-4, doi: 10.1109/IRPS46558.2021.9405197.

Abstract: Accurate prediction of device aging plays a vital role in the circuit design of advanced-node CMOS technologies. In particular, hot-carrier induced aging is so complicated that its modeling is often significantly simplified, with focus limited to digital circuits. We present here a novel reliability-aware compact modeling method that can accurately capture the full post-stress I-V characteristics of the MOSFET, taking into account the impact of drain depletion region on induced defects.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405197&isnumber=9405088

[3] Z. Wu et al., "Physics-based device aging modelling framework for accurate circuit reliability assessment," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-6, doi: 10.1109/IRPS46558.2021.9405106.

Abstract: An analytical device aging modelling framework, ranging from microscopic degradation physics up to the aged I-V characteristics, is demonstrated. We first expand our reliability oriented I-V compact model, now including temperature and body-bias effects; second, we propose an analytical solution for channel carrier profiling which-compared to our previous work-circumvents the need of TCAD aid; third, through Poisson's equation, we convert the extracted carrier density profile into channel lateral and oxide electric fields; fourth, we represent the device as an equivalent ballistic MOSFETs chain to enable channel “slicing” and propagate local degradation into the aged I-V characteristics, without requiring computationally-intensive self-consistent calculations. The local degradation in each channel “slice” is calculated with physics-based reliability models (2-state NMP, SVE/MVE). The demonstrated aging modelling framework is verified against TCAD and validated across a broad range of VG/VD/T stress conditions in a scaled finFET technology.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405106&isnumber=9405088

Circuit Design and Simulation Marathon using eSIM

 

Indian Institute of Technology, Bombay

We are happy to announce the first ever #Circuit #Design and #Simulation #Marathon using #eSim! This event is jointly organized by #FOSSEE and VLSI System Design. The FOSSEE project developed at Indian Institute of Technology, Bombay is powered by MINISTRY OF EDUCATION, GOVERNMENT OF INDIA.

To know more about the Circuit Design and Simulation Marathon, please visit https://hackathon.fossee.in/esim/

Important dates:
>> Registration: 21 May 2021 - 15 June 2021
>> Marathon Launch : 17 June 2021

May 21, 2021

SIA/Oxford Economics Report: Robust federal incentives for domestic chip manufacturing



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DIY chip for $10k Efabless, a community chip creation platform



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[Program] SICT2021 aims to bridge the gap between research in the Information and Communications Technology (ICT) and the overarching and inter-related social, environmental, and economic questions of our time https://t.co/fyMzfIun8Z #semi https://t.co/gtU7xulUHt



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May 18, 2021

[paper] An Accurate Analytical Modeling of Contact Resistances in MOSFETs

G. Bokitko, D. S. Malich, V. O. Turin*, and G. I. Zebrev
An Accurate Analytical Modeling of Contact Resistances in MOSFETs
Preprint · May 7, 2021 DOI: 10.13140/RG.2.2.29348.40321

National Research Nuclear University MEPHI, Moscow, Russia;
*Orel State University, Russia;


Abstract: As the MOSFET channel lengths decrease, the influence of parasitic source-drain resistance on the current characteristics becomes more and more important. The contact resistance is becoming a growing impediment to transistor power and performance scaling. This is a common challenge for SOI FETs, FinFETs and GAAFETs and any other type of transistor. Most of the modern compact models that are used in circuits simulations are too much technology oriented. We find it important to construct an analytical approach that could be served as a basis for compact modeling. This approach is based on analytical solution Kirchhoff’s equations and on the diffusion-drift field effect transistor model.

Fig: Equivalent MOSFET circuit with series resistance


[paper] Generalized Devices for SPICE Simulation of Soft Errors

Chiara Rossi, André Chatel and Jean-Michel Sallese*
Modeling Funneling Effect With Generalized Devices for SPICE Simulation of Soft Errors
in IEEE Transactions on Electron Devices,
doi: 10.1109/TED.2021.3076028 
* EPFL, 1015 Lausanne (CH)

Abstract: Recent advances in CMOS scaling have made circuits more and more sensitive to errors and dysfunction caused by ionizing radiation, even at ground level, requiring accurate modeling of such effects. Besides generation, transport, and collection of radiation-induced excess carriers, another phenomenon, called funneling, has to be modeled for an accurate prediction of soft errors. The funneling effect occurs when the radiation track crosses a space charge region and generates excess carriers with a density higher than the doping close to it. These carriers distort the electric field of the space charge region, deeply changing the transport mechanism, from diffusion in a field-free semiconductor to drift. The objective of this work is to include funneling as part of the generalized lumped devices model in order to obtain a complete tool for SPICE-compatible simulations of single-event effects (SEEs). The latter approach has been recently proposed to simulate radiation-induced charges in the silicon substrate and is based on the so-called generalized lumped devices that simulate charge generation, propagation, and collection using standard circuit simulators. The generalized devices are here extended to include funneling and used to simulate an alpha particle impinging on the bulk of nMOS and pMOS transistors. The results obtained are validated with TCAD numerical simulations. Finally, a static random-access memory (SRAM) struck by an alpha particle is analyzed. The model predicts that the occurrence of a soft error, i.e., flipping of memory state, may depend on whether or not there is funneling. This justifies the need for accurate modeling of funneling phenomena to predict SEEs in ICs.

FIG: Generalized devices network obtained for the pMOS substrate. The mesh is drawn in gray dashed lines. The network is not shown around the radiation track; only the mesh is reported, which is denser to linearize the generation profile and excess carrier gradients.

Aknowlwdgement: This work was supported by the Swiss National Science Foundation (NSF) under Grant 200021_165773.

World’s First Fully #Recyclable #Printed #Electronics



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May 17, 2021

South #Korea plans US$450 #billion #semiconductor spend https://t.co/VZlr2nmDI8 #semi https://t.co/esg0nOljwu



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[FOSSEE eSim] EDS Webinar Invite - 26 May 2021

As part of our commitment to advancing the vision and mission of the Electron Devices Society, we are pleased to invite you to attend our next scheduled EDS Webinars

Topic: "eSim: An open source CAD software for circuit simulation"

Presenter:  Prof. Kannan Moudgalya

Read: Biography

Date: 26 May 2021

Time: 11:00 AM EST (Convert to your time zone)


Abstract: Free and Open Source Software for Education (FOSSEE) (https://fossee.in) is a project initiated by the Ministry of Education at IIT Bombay.  It promotes many open source software systems, such as Scilab, Python, R, OpenModelica, OpenFOAM and DWSIM. It also promotes open source hardware projects, such as Arduino, and OpenPLC. By combining KiCAD and Ngspice, FOSSEE has developed an open source circuit simulation software eSim (https://esim.fossee.in).  By incorporating GHDL, eSim has been made capable of carrying out mixed signal simulation.  This capability has been extended to simulate circuits with microcontrollers, with every instruction being implemented through a function written in C.  Finally, the FOSSEE team is in the process of creating a cloud version of eSim. FOSSEE carries out several activities to promote circuit simulation through eSim.  It has trained about 10,000 students (4,000 women and 6,000 men) and 5,000 faculty members (2,000 women and 3,000 men) on the use of eSim.  FOSSEE helps colleges migrate their labs from proprietary software to eSim.  More than 200 electronic circuits have been coded in eSim by students across India, and these are released as open educational resources. The FOSSEE team has also created automatic converters to migrate PSpice and LTSpice schematics to KiCAD, and hence, eSim.  More than 100 such coverted circuits are released as open educational resources. These resources are available to everyone anywhere in the world. The talk will begin with an introduction to Spoken Tutorials (https://spoken-tutorial.org) the methodology developed by the speaker for large scale training on IT topics.

 

All participants will receive WebEx details prior to the event.  We sincerely hope that you can join us for this special event. Register Now!

May 14, 2021

[paper] Vertical Transistor with a sub-1-nm Channel



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May 12, 2021

4th International DevIC 2021 Conference

DevIC 2021 LogoDevIC 2021

Conference Date: 19-20 May, 2021

(New date after Postponement due to COVID-19 and W.B. State General Election)
We are pleased to announce the upcoming 4th International Conference “2021 Devices for Integrated Circuit (DevIC)”, to be held at Kalyani Government Engineering College from March 24-25 May 19-20, 2021, organized by IEEE KGEC Student Branch Chapter in association with Department of ECE, KGEC and technically co-sponsored by IEEE EDS Kolkata Chapter. There will be keynote lectures, talks, tutorials, and oral presentations  by eminent researchers. We solicit original research and technical papers not published elsewhere.

DevIC 2021 Conference committee appeals ALL to contribute in West Bengal State Emergency Relief Fund and assist the State in prevention and control of situation arising out of unforeseen emergencies like COVID-19 (CORONA)

  • IEEE EDS Kalyani Government Engineering College Student Branch Chapter has decided to contribute to the West Bengal State Emergency Relief Fund to combat the coronavirus outbreak.

  • IEEE EDS Kalyani Government Engineering College Student Branch Chapter  thanks Dr. Wladek Grabinski (Senior IEEE EDS Member, MOS-AK (EU)) for coming forward to contribute to fight the Corona Virus outbreak.

Due to rapid increase in COVID affected people, request to Kindly join our hands and support us by donating to West Bengal State Emergency relief Fund

  • We must act immediately to take on the second, more severe wave of COVID-19.
  • Your support is vital and critical!
  • NO amount is small!!!
  • Your contribution will truly create an impact!!!
  • Kindly motivate others to donate!!!
  • Donate in West Bengal State Emergency Relief Fund to collectively fight against unprecedented COVID-19 pandemic.

DevIC 2021 is appealing all the participants to help fight the pandemic and saving lives.

Click here to donate in West Bengal State Emergency Relief Fund

Due to COVID-19, the conference will be organized in the online mode. 

DevIC 2021 Conference Committee

Kalyani Government Engineering College (KGEC) Website

May 11, 2021

Video lecture on Circuit Simulation and Device Modeling

Professor Mansun Chan, HKUST, has started a series of video lecture on Circuit Simulation and Device Modeling in his youtube channel https://www.youtube.com/channel/UCQKeknQioXvHk1wZZB-dliw/playlists He has finished about half and will continue to upload material in the rate of one video/month.  Please feel free to share if whenever you think is appropriate.  If you have any comments, please let Prof.Chan know.

Post of Assistant/Associate Professor

Namashivaya

Amrita Center for Nanosciences and Molecular Medicine is now inviting applications for the post of Assistant/Associate Professor and for Assistant Professor of Practice, in the Nano-Energy division. We are looking for candidates with excellent research experience and accomplishments in the field of energy and nanotechnology. Interested candidates should send detailed CV and copy of certificates to researchsecretary@aims.amrita.edu . You must also apply online. 
The last date for the receipt of applications is June 6.
 
Visit https://www.amrita.edu/jobs for more information. Phone: 0484 2858750.

Join us to change the world through your research! 


May 10, 2021

Atomistic TNL TCAD Solutions

Greetings from Dr. Praveen Saxena. We wish good health to all recipients of the mail.  As a result of the significant disruption that is being caused by COVID-19 pandemic all around world and especially in India, everybody need to stay at home as preventive care and remain busy with some task. We are concerned about you and your family well-being. Please take care and stay safe.

 

 This is the best time to evaluate the Unmatched family of Innovative Atomistic TNL TCAD simulators. You may freely download the software from below link:

http://www.technextlab.com/login.php                                     

 

Register yourselves and download the TNL setup. Tech Next Lab will provide you 1- months licenses for all simulators free of cost along with technical support.

 

We are pleased to introduce in-house developed Unmatched family of Innovative Atomistic TNL TCAD simulators, including EpiGrow (Epitaxial Growth), FullBand (Material Characterization), HallMobility (Material Characterization), THz Spectroscopy (Material Characterization), and Monte Carlo Particle Device simulators (MCPDS).

 

All products are proprietary products of Tech Next Lab (P) Ltd. We provide instant technical and sales solution for the queries and feedback come from the customers. You may find more details about TNL TCAD tools on our website: www.technextlab.com

 

We may assure you that our simulators will surely help in expediting the most of semiconductor Technologies Developments and also benefits your students from teaching prospective. Few Publications:

 

For MOCVD epitaxial growth you may find more details:

https://www.sciencedirect.com/science/article/abs/pii/S0925838819329858

 

For GaN based technology for FET device applications:

https://link.springer.com/chapter/10.1007/978-981-15-5262-5_61

 

For Group-III nitrides and its alloys:

https://www.nature.com/articles/s41598-020-75588-3

 

Group II-VI Material Characterization:

https://link.springer.com/article/10.1007/s11664-021-08756-4

.

 

For Detector Application:

https://publications.drdo.gov.in/ojs/index.php/dsj/article/view/11177

https://link.springer.com/article/10.1007/s11082-020-02488-1

 

 

Feel free to write <info@technextlab.com> in case you have any query.

Looking forward to hear from you ASAP.

Best Regards,

Praveen

 


Atomistic TNL TCAD simulators:

 TNL Framework: TNL Framework includes family of innovative simulators based on atomistic level. It provides innovative technology solution to semiconductor industry. The technology development is expensive process and suffers with lot of technical challenges & issues. TNL framework is designed to innovate the semiconductor device designing. It accommodate atomistic based thin film growth simulator, full band simulator, material characterization simulator and Monte Carlo particle device simulator. 

 EpiGrow Simulator: EpiGrow simulator is world's first commercial innovative atomistic epitaxial growth simulator to grow thin film inside MBE/MOCVD reactors. EpiGrow simulator is powerful tool to trace atomistic thin and thick film growth inside reactors. Kinetic Monte Carlo algorithms keeps Randomness in adsorption, hopping & desorption processes. It offer cost economical solution for thin film growth technology even for nm thin monolayer. Capable to predict the initial conditions for Molecular Beam Epitaxy & Molecular Organic Chemical Vapor Deposition (MOCVD) reactors. Capable to calculate the lattice constant of monolayer, trace different types of defects, and strain. Optimizer provides flexibility to optimize initial conditions with EpiGrow Simulator and run design of experiments over the computer.

 TNL-FB Simulator:   Full Band Simulator is powerful tool, extends the empirical pseudopotential method to include semiconductors with the zincblende as well as wurtzite structures and simulates electronic band structures with appropriate pseudopotential form factors chosen from the reported reputed references for binary alloy semiconductor materials and interpolate the pseudopotential form factors for ternary alloy semiconductor materials to simulate the full electronic band structures of ternary materials. The bowing of band energies and their deformation potentials is included inside simulator in form of alloy disorder. Capable to simulate the full electronic band structures for the lattice constant of monolayer provided by users. Different types of physical parameters e.g. carrier velocity, effective mass and density of states can be easily tracable on the full electronic band structures of the chosen materials. Provides flexibility to users to chose lattice constant and analyse the full electronic band structures over computer.

 TNL-EM Simulator: Electron Mobility Simulator is powerful tool, simulates carriers transport on full energy band. The microscopic simulation of the motion of individual particles in the presence of the forces acting on them due to external fields as well as the internal fields of the crystal lattice and other charges in the system. In solids, such as semiconductors and metals, transport is known to be dominated by random scattering events due to impurities, lattice vibrations, etc. has been inputted through Monte Carlo technique, which randomize the momentum and energy of charge particles in time. Hence, stochastic techniques to model these random scattering events are particularly useful in describing transport in semiconductors, in particular the Monte Carlo method. Provides flexibility to users to initialize the carriers over full energy band and analyze the transport of carrier to simulate the ensemble velocity of carriers under external electromagnetic forces on computer.

 TNL-TS (THz Spectroscopy) Simulator is powerful tool to simulates motion of charged and interacting particles. The microscopic simulation of the motion of individual particles under the influence of the THz pulse as well as the internal fields of the crystal lattice and influence of other charges, lattice defects etc. In solids, such as semiconductors and metals, transport is known to be dominated by random scattering events due to impurities, lattice vibrations, etc., which randomize the momentum and energy of charge particles in time. The stochastic techniques to model these random scattering events are particularly useful in describing inter and intraband transitions of charge carriers in bulk & nonmaterial. The Monte Carlo technique use for solution of Boltzmann transport equation provides flexibility to users to initialize the carriers over many or particular band of the material and analyze the position, momentum, energy & other properties associated with motion of charged particles under influence of THz Pulses, frequencies ranging from few hundred gigahertz to several terahertz. THz Spectroscopy simulator has capabilities to simulate the microscopic conductivity of weakly confined, classical electrons in absence of depolarization effects without need of any approximations of fitting parameters to calibrate the Drude-Smith conductivities..

 TNL-PD Simulator: World's Fastest Monte Carlo Particle Device simulator includes transport model solution with a self -consistent Boltzmann-Poisson equation and a GUI based feature helps users to select device geometry and doping density in 2D and 3D. The different carrier scattering mechanisms has major influence on the performance of device output and dependent on the density of states (DOS) in each valley which can be accurately inputted through full band structure. The effect of equilibrium states of carrier before start of free flight of carrier has been incorporated in term of inclusion of depletion region through movement of the ensemble of carriers under influence of external electrostatic field obtained by solving the Poisson equation. The quantum confinement effect includes density gradient approach and effective potential approach for computation of quantum confinement effects on the carrier transport under influence of external forces. Particle Device Simulator (PDS) is exploited for unipolar as well as bipolar semiconductor technologies based devices including MOSFET, Multigate FETS, HEMT and P-N junction devices.

 

 

*******************************************

Dr. P. K. Saxena

CEO & CTO,

Tech Next Lab Pvt Ltd (TNL)

Near Nagar Nigam Office Zone-6,

Niwaz Ganj, Lucknow- 226 003 (INDIA)

 

Phone: (+91) 983 915 1284 / (+91) 9415893655

Fax: 0522 2258921

Email: info@technextlab.com 

Web: www.technextlab.com  

Skype ID: praveen.itbhu

Linkedin: https://www.linkedin.com/home?trk=nav_responsive_tab_home  

  

********************************************

[paper] Compact Model for SiC Power MOSFETs

Cristino Salcines1, Sourabh Khandelwal2 and Ingmar Kallfass1 
A Compact Model for SiC Power MOSFETs 
for Large Current and High Voltage Operation Conditions 
(2021) arXiv-2104. 
1 University of Stuttgart Stuttgart, Germany
2 Macquarie University Sydney, Australia  

Abstract: This work presents a physics based compact model for SiC power MOSFETs that accurately describes the I-V characteristics up to large voltages and currents. Charge-based formulations accounting for the different physics of SiC power MOSFETs are presented. The formulations account for the effect of the large SiC/SiO2 interface traps density characteristic of SiC MOSFETs and its dependence with temperature. The modeling of interface charge density is found to be necessary to describe the electrostatics of SiC power MOSFETs when operating at simultaneous high current and high voltage regions. The proposed compact model accurately fits the measurement data extracted of a 160 milli ohms, 1200V SiC power MOSFET in the complete IV plane from drain-voltage Vd = 5mV up to 800 V and current ranges from few mA to 30 A.
Fig: Output characteristics up to high current and high voltage in logarithmic scale for VGS = 6V to 20V in steps of 0.5V. Symbols are measurements and solid lines simulations of the proposed model. The logarithmic scale eases the visualization of both low and high VDS voltages in a single graph.


Quirk is a quantum circuit simulator, great for manipulating and exploring small quantum circuits. Quirk's visual style gives a reasonably intuitive feel of what is happening, state displays update in real time, and is fast and interactive https://t.co/y5Izitamco #semi https://t.co/mLo2ZlSQQb



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May 8, 2021

10th All-Russia MES-2021 Conference

10th All-Russia Science and Technology Conference
Problems of Advanced Micro- and Nanoelectronic Systems Development 
MES-2021
March - November 2021
Moscow | Zelenograd

MES-2021 is dedicated to urgent issues of design automation of microelectronic systems, SoC, IP-blocks and a new element base of micro-and nanoelectronics. These issues have been and remain actual to science and technology, as evidenced by the major topics of the Annual International Conference on CAD and the development of micro-and nanoelectronic devices. MES is the largest conference in the field of CAD microelectronics in Russia and CIS countries. Proceedings of the MES conference is included in HAC list (issue 23.03.2021, pos. 2017) of Russian scientific journals, where should be published the main results of the PhD and DSc theses.
The upcoming 10th MES-2021 conference will be held mainly in the correspondence format, starting on March 01, 2021, and it will be concluded with its plenary session in November 2021.

Key discussion topics
1. Theoretical aspects of micro-and nanoelectronic systems (MES).
2. Methods and tools of design automation for micro-and nanoelectronic circuits and systems (VLSI CAD).
3. Experience of development of digital, analog, digital to analog, radio functional blocks of VLSI.
4. Features of VLSI design for nanometer technologies.
5. SoCs for advanced radioelectronic equipment.
6. Exhibition and presentation of commercial products.

Fields of interest of the conference include (but is not limited to) the following topics of relevant studies of VLSI design and VLSI design automation techniques:

Design
1. Circuits and Systems based on nanometer technologies
2. Systems on Chip
3. Digital VLSI Design
4. Design of analog functional blocks and radio VLSI
5. Design of mixed-signal VLSI
6. Methods of structural synthesis of analog, digital and mixed VLSI and complex functional blocks
7. Specialized (resistant to special effects, photosensitivity, etc.) VLSI

Simulation
1. Methods of simulation of digital, analog and mixed circuits and systems
2. Methods for radio VLSI simulation
3. Structural, logical, circuit, mixed and layout simulation
4. Methods for generating models and macromodels for VLSI CAD
5. Device and Technology simulation
6. Behavioral simulation

Information processing methods
1. Information coding
2. Digital data processing
3. Use of artificial intelligence methods, neural networks, etc. in micro- and nanoelectronic system designs
4. Unconventional arithmetic
5. High-performance computers

The development of nanoelectronic systems on new principles
1. Nanomagnetic storage devices
2. Magnetosensor structures

Call for participation in the conference program
I stage - After registration at least one of the co-authors of the report one can send an article. To do this, using their registration data, please log in (see upper right corner of screen). Fill in all required fields. On the website you should send a file containing the main text of the article (in Russian or English) and an extended abstract in English (if the main text is in Russian) or a simple abstract in Russian (if the main text of the article in English). Requirements for the articles sent to MES.
II stage - sending additional documents only for the articles, which have been reviewed and accepted to the conference program.

Visit the 10th MES-2021 conference website at: http://www.mes-conference.ru/index.php





May 7, 2021

[paper] 1.5-nm Node SGT SRAM Cell



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May 6, 2021

[Workshop] The Future of Nanoelectronics Devices and Systems Beyond Moore

“The Future of Nanoelectronics Devices and Systems Beyond Moore” 
Workshop on August 31, 2021

This one-day Workshop, supported; IEEE, will be devoted to the update of the European contribution to the IRDS Roadmap in the field of More than Moore, Beyond CMOS and Emerging Materials. The main challenges, most promising technologies, needed research efforts and possible applications will be presented in the following sessions; renown EU experts:
  • Beyond CMOS and Emerging Materials
    • Trends in Beyond CMOS
      Clivia Sotomayor-Torres; ICN2 and Jouni Ahopelto; VTT
    • 2D semi-metal to semiconductor transition devices and/or doping of 2D materials
      Farzan Gity; Tyndall
    • GeSn/Ge vertical nanowire GAA FETs
      Qing-Tai Zhao; FZJ
    • Flexible electronics with 2D materials
      Zhenxing Wang; AMO
    • Presentation of the new IRDS More than Moore Roadmap
      Mart Graef; TU Delft
  • Energy Harvesting for Autonomous Systems
    • Summary of the IRDS Energy Harvesting for Autonomous Systems White Paper
      Gustavo Ardila; UGA
    • Energy sustainability problems of IoT networks
      Thomas Skotnicki; CEZAMAT
    • Contribution of triboelectricity for kinetic energy harvesting using electrostatic transduction
      Philippe BASSET; ESIEE, Paris
  • Smart Sensors
    • Summary of the IRDS Smart Sensors White Paper
      Alan O’Riordan; Tyndall
    • Sensing at the Edge: Challenges and Opportunities
      Adrian Ionescu; EPFL
    • Smart Sensors and Systems for environment and human exposure monitoring
      Carmen Moldovan; IMT
  • Smart Energy
    • Summary of the IRDS Smart Energy White Paper
      Mikael Ostling; KTH
    • Smart power devices based Wide Bandgap semiconductors
      William Vandendaele; CEA LETI
    • Materials and substrates for future power devices
      Joff Derluyn; Soitec BU EpiGaN
  • Flexible/Wearable Electronics
    • Roadmap of Flexible Electronics: Challenges and Possible Solutions; Summary of the IRDS White Paper
      Benjamin Iñiguez; URV
    • Schottky barrier and organic devices for neuromorphic circuits
      Laurie Calvet; CNRS; Université Paris Saclay
    • New strategies for sustainable electronics
      Elvira Fortunato; UNL
Program: will be available soon
Registration: free of charge but mandatory; More information: 
EDS
SINANO
Euro
IEEE

[C4P] 3rd ACM/IEEE Workshop on Machine Learning for CAD

Call for Papers: MLCAD

 3rd ACM/IEEE Workshop on Machine Learning for CAD
31 August - 2 September 2021  |  Hybrid Workshop

This workshop focuses on Machine Learning (ML) methods for all aspects of CAD and electronic system design. The workshop is sponsored by both the ACM Special Interest Group on Design Automation (SIGDA) and the IEEE Council on Electronic Design Automation (CEDA). The workshop program will, in addition to technical presentations, also have keynotes and invited speakers from major CAD and industrial companies who will present their vision on machine learning for CAD.

We encourage senior researchers as well as Ph.D. students to be part of this workshop. Submitted papers which have been accepted for presentation at the workshop will be included in the workshop proceedings. A Best Paper Award will be presented at the workshop.

The MLCAD 2021 organizing committee invites proposals for special sessions. A special session is expected to have a minimum of three, up to six speakers, including the organizers, who provide an overview of the topic area. Prospective organizers of special sessions should submit proposals to the special session chair indicating: title and abstract of the session, organizers, a list of topics (please provide a list of all talks, speakers and their short biographies, co-authors, the contact information of the corresponding author, and an abstract of each contribution).

Paper submissions are due 16 May 2021. Fo more details on paper submission, visit the website

Call for Papers