Showing posts with label rf. Show all posts
Showing posts with label rf. Show all posts

Mar 18, 2024

[paper] Symmetric BSIM-SOI

Chetan Kumar Dabhi, Dinesh Rajasekharan, Girish Pahwa, Debashish Nandi, Naveen Karumuri, Sreenidhi Turuvekere, Anupam Dutta, Balaji Swaminathan, Srikanth Srihari, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu
Symmetric BSIM-SOI: A Compact Model for Dynamically Depleted SOI MOSFETs 
 in IEEE TED (2024)
Part I DOI: 10.1109/TED.2024.3363110
Part II DOI: 10.1109/TED.2024.3363117

1 Department of Electrical Engineering and Computer Sciences, UCB, CA, USA
2 Department of Electrical Engineering, IIT Kanpur, India
3 GlobalFoundries, Bengaluru, India

Abstract: In this article, we present a symmetric surface-potential-based model for dynamic depletion (DD) device operation of silicon-on-insulator (SOI) FETs for RF and analog IC design applications. The model accurately captures the device behavior in partial depletion (PD) and full depletion (FD) modes, as well as in the transition from PD to FD, based on device geometry, doping, and bias conditions. The model also exhibits an excellent source–drain symmetry during dc and small-signal simulations, resulting in error-free higher order harmonics. The model is fully scalable with bias, temperature, and geometry and has been validated extensively with real device data from the industry. The symmetric BSIM-SOI model is developed in Verilog-A and compatible with all commercial SPICE simulators.

FIG: (a) Schematic of a typical SOI MOSFET
(b) Cgg versus Vgb for different substrate bias, with the PD-to-FD transition 

Acknowledgment: The authors thanks the members of the Compact Model Coalition (CMC), particularly Geoffrey J. Coram and Jushan Xie, for testing the model and suggesting improvements. The authors appreciate the CMC QA team’s efforts in conducting a model quality check. Caixia Han and Xiao Sun from Cadence provided a few useful test cases. They thank Ananth Sundaram and Anamika Singh Pratiyush from GlobalFoundries India for the help and discussion regarding DDSOI model intricacies and development. Model code is available at BSIM Website <https://bsim.berkeley.edu/models/bsimsoi/>












Dec 20, 2023

[paper] PSP RF Model

Xiaonian Liu1, 2, and Yansen Liu1, 2
Scalable PSP RF Model for 0.11 µm MOSFETs
Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract: An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 µm CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The PSP RF subcircuit model and its S-par s fitting
results of NMOS with Wf = 2 µm, Lf = 0.12 µm, nf = 16

Acknowledgment: This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

Nov 13, 2023

[paper] PSP RF Model

Xiaonian Liu1, 2 and Yansen Liu1
A Scalable PSP RF Model for 0.11 µm MOSFETs
Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023
DOI :10.2528/PIERL23081405

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China.
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.


Abstract : An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The RF PSP Model Subcircuit

Acknowledgment : This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.



May 11, 2023

OpenPDK Networking Workshop


OpenPDK, OpenTooling and Open Source Design
An Initiative to Push Development
Date:
Networking Workshop FMD-QNC on 27-28 June 2023
Location:
IHP; Im Technologiepark 25; 15236 Frankfurt (Oder)
Contact:
Sergei Andreev; Phone: +49 335 5625 523
Free Registration: 




The workshop is organised by IHP and FMD (Research Fab Microelectronics Germany) within the framework of the FMD-QNC Project.

Within the project FMD-QNC analog circuit design with open source software shall be enabled. For this purpose, both the open source design tools and a process design kit of the semiconductor technology used must support the entire design flow with sufficient quality. IHP provides its 130 nm BiCMOS technology SG13G2 for open source design. This technology is particularly suited for high frequency and mixed signal design applications. While basic tool support already exists for digital circuit design, it is still very rudimentary for analog designs and especially for high frequency designs. A considerable effort has to be put into the development of the design tools as well as into the creation of the technology specific Process Design Kit (PDK).

The 2-day workshop is intended to promote exchange and networking between tool developers, the PDK developers at IHP and designers. Tool developers are to present the capabilities of the tools as well as planned enhancements. Designers are to present ideas that can be used for training chip designers. Requirements for open source design tools for digital design, mixed signal design, and high frequency design are to be highlighted.

Discussions will identify and prioritize gaps for a complete design flow in the open source tools and PDK. The workshop will thus help to concrete the planning for the Open Design Platform and to create a roadmap for future work.

Presentation

Presenter/Institution

Timeline

Day 1

Welcome by coordinator FMD-QNC

Dr. Andreas Bruning
Research Fab Microelectronics Germany

9:00-9:10

Introduction FMD-QNC project status and IHP OpenPDK Roadmap

Dr. Rene Scholz
IHP

9:10-9:30

Status OpenPDK and OpenTooling for SG13G2 BiCMOS technology

Sergei Andreev
IHP

9:30-10:00

An Ultra-Low-Power High-Density Wireless Biomedical Sensing System

 

Prof. Harald Pretl
Johannes Kepler University Linz

10:00-10:30

Teaching digital design by using open-source EDA tools

Prof. Steffen Reith
Rhein Main University of Applied Sciences

10:30-11:00

Coffee break

11:00-11:40

CMOS Rail-to-Rail Operational Amplifier for HPGe Radiation Detector

Prof. Herman Jalli Ng
Karlsruhe University of Applied Sciences

11:40-12:10

Design-flow approaches for mmWave and sub-THz integrated transceiver circuits for radar and communication

Sasha Breun
FAU Erlangen

 

12:10-12:40

Lunch break 

12:40-13:40

TBD

Dr. Frank K. Gurkaynak
ETH Zurich

13:40-14:10

TBD

Joachim Hebeler
Karlsruhe Institute of Technology

14:10-14:40

Coffee break

14:40-15:10

 TBD

Prof.  Dietmar Kissinger
Ulm University

15:10-15:40

LibMan - an easy way to manage your open source design flow

Dr. Anton Datsuk
IHP

15:40-16:10

Get together (Barbecue)

 

17:00-…

Day 2

ngspice - status and future developments

Prof. Holger Vogt

9:00-9:20

DMT - Python Toolkit for Device Modeling

Mario Krattenmacher
SemiMod

9:20-9:40

OpenVAF - Next Generation Verilog-A Compiler with ngspice integration

Mario Krattenmacher
SemiMod

9:40-10:00

Coffee break

10:00-10:40

Best practices for implementing and optimizing KLayout DRC and LVS decks

Matthias Köfferlein


10:40-11:00

Generating DRC and LVS Runsets for KLayout

Dr. Andreas Krinke
TU Dresden

11:00-11:20

OpenEMS in open source EDA

Jan Taro Svejda
University of Duisburg-Essen

11:20-11:40

Lunch break

11:40-12:40

Panel discussion on the roadmap – open source tools for IC design

Topics:

  • Digital design flow
  • Analog design flow
  • Challenges in RF design

Dr. Norbert Herfurth
IHP

Panelists: TBD

12:40-14:10

Feb 20, 2023

[C4P] T-ED Special Issue



Call for Papers - Special Issue on "Wide and Ultrawide Band Gap Semiconductor Devices for RF and Power Applications."

The Special Issue of the IEEE Transactions on Electron Devices (T-ED) will report the most advanced and recent results in the field of wide and ultrawide bandgap semiconductor materials and devices, including papers focused on material fabrication, device processing, reliability investigation, device modeling, thermal aspects, and system-related results.

Submission deadline: 31 August 2023
Publication date: February 2024

Submit papers today: https://bit.ly/3fESTgZ

Guest Editors: 
Prof. Matteo Meneghini, University of Padova, Italy 
Prof. Patrick Fay, University of Notre Dame, USA 
Prof. Digbijoy Nath, IISC Bangalore 
Prof. Geok Ing Ng, Nanyang Technical University, Singapore 
Prof. Junxia Shi, University of Illinois, Chicago 
Prof. Shyh-Chiang Shen, Georgia Tech. 



Jan 12, 2022

[paper] Pseudo-morphic PHEMT: Numerical Simulation Study

Khaouani Mohammed, Hamdoune Abdelkader, Guen Ahlam Bouazza, Kourdi Zakarya, Hichem Bencherif
An Improved Performance of Al0.25Ga0.75N/AlN/GaN/Al0.25Ga0.75N Pseudo-morphic High Electron Mobility Transistor (PHEMT): 
Numerical Simulation Study
IC-AIRES 2021. Lecture Notes in Networks and Systems, vol 361. Springer
DOI: 10.1007/978-3-030-92038-8_80




1. Hassiba Benbouali, Chlef, Algeria
2. University of Abou-Bakr Belkaid, Tlemcen, Algeria
3. Center Exploitation Satellite Communications Agency of Space Oran, Algeria
4. University of Mostefa Benboulaid, Batna, Algeria 

Abstract: In this paper a 9nm T-shaped gate length, Pseudo-morphic High Electron Mobility Transistor (pHEMT AlGaN/AlN/GaN/AlGaN) is studied; we use TCAD software. DC, AC and RF performances assessment allow to exhibit interesting results such as a maximum drain current IDSmax=35mA at VGS=0V, a knee voltage Vknee=0.5V with ON-resistance Ron=0.8Ω-mm, a sub-threshold swing of 75mV/decade, a maximum transconductance value gm=160mS/mm, a DIBL of 36mV/V, a drain lag of 8.5%, a cut-off frequency of 110GHz, a maximum oscillation frequency of 800GHz, and very suitable breakdown voltage VBR of 53.1V. This device can be used in radar, high power and amplifier applications.


Jan 5, 2022

[book] Advanced ASM-HEMT Model for GaN HEMTs

Sourabh Khandelwal
Advanced SPICE Model for GaN HEMTs (ASM-HEMT)
A New Industry-Standard Compact Model 
for GaN-based Power and RF Circuit Design
DOI: 10.1007/978-3-030-77730-2
eBook ISBN: 978-3-030-77730-2

Describes in detail a new industry standard for GaN-based power and RF circuit design. Includes discussion of practical problems and their solutions in GaN device modeling. Covers both radio-frequency (RF) and power electronics application of GaN technology and describes SPICE modeling of both GaN RF and power devices.


Table of contents:

  • Front Matter; pp. i-xv
  • Gallium Nitride Semiconductor Devices; pp. 1-8
  • Compact Modeling; pp. 9-19
  • Introduction to ASM-HEMT Compact Model; pp. 21-31
  • Core Formulations in ASM-HEMT Model; pp. 33-45
  • Non-ideal Effects in Device Current and Their Modeling; pp. 47-62
  • Trapping Models; pp. 63-81
  • Non-Ideal Effects in GaN Capacitances and Their Modeling; pp. 83-100
  • Gate Current Model; pp. 101-113
  • Effect of Ambient Temperature on GaN Device; pp. 115-124
  • Noise Models; pp. 125-130
  • Parameter Extraction in ASM-HEMT Model; pp. 131-150
  • Advance Simulations with ASM-HEMT Model; pp. 153-174
  • Resources for ASM-HEMT Model Users; pp. 175-175
  • Back Matter; pp. 175-188

About the author:
Sourabh Khandelwal is Senior Lecturer at the School of Engineering at Macquarie University, Sydney. He is the lead developer of ASM--HEMT compact model, which is a new industry standard compact model for GaN RF and power devices. Earlier to this role, Manager of Berkeley Device Modeling Center and Postdoctoral Researcher at the BSIM group at University of California, Berkeley. Before that, he worked as Research Engineer at IBM Semiconductor Research. He has over 200 publications in top-tier conferences and journals in the area of semiconductor device modeling and circuit design.

Nov 13, 2021

Advances in RF and THz emerging electronic devices webinar at IPN-UAB

The webinar joitly co-organize together with Instituto Politécnico Nacional, Mexico 
is intended to present and discuss recent advances in RF and THz emerging electronic devices.

Feel free to share the information with your colleagues and/or students. The registration is free, and you can do it here (it is in Spanish but the only required fields are Name, Surname, Email, and Email confirmation). Alternatively, you can follow the live stream in this youtube channel.

The time appearing in the flyers are referred to Mexico City's time. The schedule is starting each day Nov.16-18, 2021 at 16 hrs CET.

If you have further questions you can contact 

   

Jul 21, 2021

[paper] 11.8 GHz Fin Resonant Body Transistor

Analysis and Modeling of an 11.8 GHz Fin Resonant Body Transistor 
in a 14nm FinFET CMOS Process 
Udit Rawat, Student Member, IEEE, Bichoy Bahr*, Member, IEEE, 
and Dana Weinstein, Senior Member, IEEE
arXiv:2107.04502v1 [physics.app-ph] 9 Jul 2021
 
Department of Electrical Engineering, Purdue University, West Lafayette USA
*Kilby Labs - Texas Instruments, Dallas, TX, USA.

Abstract: In this work, a compact model is presented for a 14 nm CMOS-based FinFET Resonant Body Transistor (fRBT) operating at a frequency of 11.8 GHz and targeting RF frequency generation/filtering for next generation radio communication, clocking, and sensing applications. Analysis of the phononic dispersion characteristics of the device, which informs the model development, shows the presence of polarization exchange due to the periodic nature of the back-end-of-line (BEOL) metal PnC. An eigenfrequency-based extraction process, applicable to resonators based on electrostatic force transduction, has been used to model the resonance cavity. Augmented forms of the BSIM-CMG (Common Multi-Gate) model for FinFETs are used to model the drive and sense transistors in the fRBT. This model framework allows easy integration with the foundry-supplied process design kits (PDKs) and circuit simulators while being flexible towards change in transduction mechanisms and device architecture. Ultimately, the behaviour is validated against RF measured data for the fabricated fRBT device under different operating conditions, leading to the demonstration of the first complete model for this class of resonant device integrated seamlessly in the CMOS stack.
Fig: Complete 3D FEM Simulation model depicting two adjoining fRBT unit cells. Mx (x=1-3) and Cy (y=4-6) represent the first 6 metal levels that form a part of the BEOL PnC.

Acknowledgement: This work was supported in part by the DARPA MIDAS Program.



 

Mar 15, 2021

[paper] 3D integrated GaN/RF-SOI SPST switch

Frédéric Drillet, Jérôme Loraine, Hassan Saleh, Imene Lahbib, Brice Grandchamp, Lucas Iogna-Prat, Insaf Lahbib, Ousmane Sow, Albert Kumar and Gregory U'Ren 
RF Small and large signal characterization of a 3D integrated GaN/RF-SOI SPST switch 
International Journal of Microwave and Wireless Technologies, pp. 1–6, 2021.

*X-FAB France, Corbeil-Essonnes (F)

Abstract: This paper presents the radio frequency (RF) measurements of an SPST switch realized in gallium nitride (GaN)/RF-SOI technology compared to its GaN/silicon (Si) equivalent. The samples are built with an innovative 3D heterogeneous integration technique. The RF switch transistors are GaN-based and the substrate is RF-SOI. The insertion loss obtained is below 0.4 dB up to 30 GHz while being 1 dB lower than its GaN/Si equivalent. This difference comes from the vertical capacitive coupling reduction of the transistor to the substrate. This reduction is estimated to 59% based on a RC network model fitted to S-parameters measurements. In large signal, the linearity study of the substrate through coplanar waveguide transmission line characterization shows the reduction of the average power level of H2 and H3 of 30 dB up to 38 dBm of input power. The large signal characterization of the SPST shows no compression up to 38 dBm and the H2 and H3 rejection levels at 38 dBm are respectively, 68 and 75 dBc.

Fig: X-FAB 3D integration proposal cross-section (left) and the picture of a GaN coupon (right).

Acknowledgement: We would like to acknowledge the Nano2022 program for partially funding this work.

Supplementary material: The supplementary material for this article can be found at DOI: 0.101/1759078721000076

Sep 29, 2020

[thesis] RF UTBB FDSOI MOSFET

Vanbrabant, Martin
RF characterization of the back-gate contact on Fully Depleted SOI MOSFETs
http:// hdl.handle.net/2078.1/thesis:26763
Ecole polytechnique de Louvain, Université catholique de Louvain, 2020. 
Academic year 2019–2020: Master in Electrical Engineering
Prom.: Prof. Jean-Pierre Raskin
Readers: Denis Flandre, Valeriya Kilchytska, Lucas Nyssens, Martin Rack

Abstract: Thanks to the thin buried-oxide, the UTBB FDSOI technology with a highly doped region under the BOX is one of the main candidates for future RF applications. One of the most interesting feature of this technology is the possibility to tune the threshold voltage, compensate variability issues and improve the overall device performance. In this work, the impact of the back-gate bias is mainly studied on the threshold voltage and RF FoMs of the front and back-gates.


Figure: Reconstructed (dashed) vs initial (full) Re{Yij} insaturationat VDS=0.8V, VGS=0.8V and VB=0V for a 4-port device.




Sep 8, 2020

[paper] RF Small-Signal Model for Four-Port Network MOSFETs

A High-Frequency Small-Signal Model for Four-Port Network MOSFETs
Alejandro Roman-Loera1, Member, IEEE, Anurag Veerabathini2, Member, IEEE, Luis A.Flores-Oropeza1, Member, IEEE, and Jaime Ramirez-Angulo3, Life Fellow, IEEE
IEEE 63rd IMWSCAS 2020
DOI:10.1109/mwscas48704.2020.9184475 

1Electronic Systems Department, Universidad Autonoma de Aguascalientes, Mexico.
2Maxim Integrated, Chandler, AZ, USA.
3Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA.

Abstract: A high-frequency small-signal model for a MOSFET is proposed considering the parasitic capacitances associated with each terminal that is critical in the design of high-frequency amplifiers. The proposed model allows in obtaining a closed form expression for poles and zeros due to parasitic elements along with the conventional poles and zeros. This model gives an additional degree of freedom in choosing the location of poles and zeros to improve the frequency response. The proposed high-frequency small-signal model for MOSFET is validated in simulation by implementing a high-frequency voltage follower in 0.18µm CMOS process. The proposed model shows the existence of a zero in a voltage follower that is introduced by the parasitic elements at high-frequencies and it is validated with implementation.

Fig: Small signal equivalent circuit of a 4-port MOSFET (a) Conventional model, (b) Model with substrate parasitics, and (c) Model with additional parasitics, and (d) Proposed model.

Acknowledgment: This work has been supported by PRODEP program from SEP (Secretariat of Public Education, Mexico) and Universidad Autonoma de Aguascalientes, Aguascalientes, Mexico.

Sep 3, 2020

Broadband Measurements to 220 GHz

VectorStar ME7838G 70 kHz to 220 GHz Single Sweep VNA Measurements and On-Wafer Calibrations

  • Miniature mmWave MA25400A NLTL module connects directly to probes without cables for best dynamic range and stability
  • MPI TITAN Probes available in 50, 75, and 100 um pitch
  • Probes are field replaceable
On-wafer calibrations:
  • SOLT up 40 or 70 GHz if standards provide required performance
  • LRM, ALRM, LRRM, and multiline TRL up to 220 GHz
  • SOLR when thru is not 0 length, is not well matched, insertion loss is less known, and there is no .s2p file describing the thru
Calibration substrates:
  • Available from MPI
  • When possible, use a ceramic chuck to minimize the potential for multimode parasitic propagation.
  • Alternatively, use an isolation wafer on metal chuck if available

May 25, 2020

[paper] IoT Vision empowered by EH-MEMS and RF-MEMS

Internet of things (IoT); internet of everything (IoE); tactile internet; 5G
A (not so evanescent) unifying vision empowered 
by EH-MEMS (energy harvesting MEMS) and RF-MEMS (radio frequency MEMS)
 Jacopo Iannacci
Fondazione Bruno Kessler (FBK) in Trento (IT)
Sensors and Actuators A: Physical 272 (2018): 187-198

Abstract: This work aims to build inclusive vision of the Internet of Things (IoT), Internet of Everything (IoE), Tactile Internet and 5G, leveraging on MEMS technology, with focus on Energy Harvesters (EH-MEMS) and Radio Frequency passives (RF-MEMS). The IoT is described, stressing the pervasivity of sensing/actuating functions. High-level performances 5G will have to score are reported. Unifying vision of the mentioned paradigms is then built. The IoT evolves into the IoE by overtaking the concept of thing. Further step to Tactile Internet requires significant reduction in latency, it being enabled by 5G.

The discussion then moves closer to the hardware components level. Sets of specifications driven by IoT and 5G applications are derived. Concerning the former, the attention is concentrated on typical power requirements imposed by remote wireless sensing nodes. Regarding the latter, a set of reference specifications RF passives will have to meet in order to enable 5G is developed. Once quantitative targets are set, a brief state of the art of EH-MEMS and RF-MEMS solutions is developed, targeting the IoT and 5G, respectively. In both scenarios, it will be demonstrated that MEMS are able to address the requirements previously listed, concerning EH from various sources and RF passive components.
FIG: Scheme of the pillar drivers supporting evolution of the IoT into IoE andTactile Internet.
Some relevant IoT technology enablers are indicated.
In conclusion, the frame of reference depicted in this work outlines a relevant potential borne by EH-MEMS and RF-MEMS solutions within the unified scenario of IoT, IoE, Tactile Internet and 5G, making the forecast of future relentless growth of MEMS-based devices, more plausible and likely to take place.


Apr 14, 2020

ICMTS2020 #paper: Cutoff Frequency Fluctuation in RF-MOSFETs

2020 ICMTS, April 6-9, Edinburgh (UK)
Novel Statistical Modeling and Parameter Extraction Methodology
of Cutoff Frequency for RF-MOSFETs
Chika Tanaka, Yasuhiko Iguchi, Atsushi Sueoka, and Sadayuki Yoshitomi
Memory Division, Kioxia Corporation
2-5-1, Kasama, Sakae-ku, Yokohama, 247-8585, Japan

Abstract: The cutoff frequency fluctuation in RF-MOSFET has been investigated. Detailed analysis for capacitance fluctuation as well as the extraction of an intrinsic MOSFET parameter were performed. The extracted process parameters were verified by the framework of effective mobility. The global statistical model of cutoff frequency was successfully developed in terms of capacitance fluctuation, considering intrinsic (channel and bulk charge) and extrinsic (overlap and fringe) capacitance components separately and identifying the major variability sources for cutoff frequency by using extracted parameter.
Fig: Calculated σfT is plotted against σfT obtained from measured data.




Jul 12, 2019

IEEE ICECS 2019 paper submission deadline

ICECS 2019 paper deadline submission is approaching fast: July 15th, 2019

Please distribute this reminder to possible contributors and interested researchers and colleagues. Topics of interest include but are not limited to:

• Analog/mixed-signal/RF circuits
• Biomedical and Bio-Inspired Circuits and Systems
• EDA, Test and Reliability
• Digital circuits and systems
• Linear and Non-linear Circuits
• Low-Power Low-Voltage Design
• Microsystems
• Neural networks, Machine and Deep Learning
• Sensors and Sensing Systems
• Signal Processing, Image and Video
• VLSI Systems and Applications

The technical committee invites authors to submit 4-page papers in standard IEEE double-column format, including references, figures and tables, to clearly present the work, methods, originality, significance and applications of the techniques discussed.

Maurizio Valle; IEEE ICECS 2019 General Chair
https://www.ieee-icecs2019.org/

Aug 28, 2017

[paper] Nanoscale MOSFET Modeling

 Nanoscale MOSFET Modeling: 
Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits
C. Enz, F. Chicco and A. Pezzotta
in IEEE Solid-State Circuits Magazine, vol. 9, no. 3, pp. 26-35, Summer 2017
doi: 10.1109/MSSC.2017.2712318

Abstract: This article presents the simplified charge-based Enz-Krummenacher-Vittoz (EKV) [11] metal-oxide-semiconductor field-effect transistor (MOSFET) model and shows that it can be used for advanced complementary metal-oxide-semiconductor (CMOS) processes despite its very few parameters. The concept of an inversion coefficient (IC) is first introduced as an essential design parameter that replaces the overdrive voltage VG-VT0 and spans the entire range of operating points from weak via moderate to strong inversion (SI), including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40- and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation, valid from weak to SI and requiring only the VS parameter mc, is described. The normalized transconductance efficiency Gm/ID, which is a key figure-of-merit (FoM) for the design of low-power analog circuits, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to SI with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance Gds/ID follows a similar dependence with IC than the normalized Gm/ID characteristic but with different parameters accounting for drain induced barrier lowering (DIBL). The methodology for extracting the few parameters from the measured ID-VG and ID-VD characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted silicon on insulator (FDSOI) and Fin-FET 28-nm processes [read more...]

FIG: The simplified EKV model applied to a 28-nm FDSOI CMOS process: 
Gm n UT / ID versus IC for three different transistor channel lengths

References
[1] A. Bahai, “Ultra-low energy systems: Analog to information,” in Proc. European Solid-State Circ. Conf., Sept. 2016, pp. 3–6.
[2] D. Binkley, Tradeoffs and Optimization in Analog CMOS Design. Hoboken, NJ: Wiley, 2008.
[3] W. Sansen, Analog Design Essentials. New York: Springer-Verlag, 2006.
[4] A. Mangla, M. A. Chalkiadaki, F. Fadhuile, T. Taris, Y. Deval, and C. C. Enz, “Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model,” Microelectr. J., vol. 44, no. 7, pp. 570–575, July 2013.
[5] Y. S. Chauhan, S. Venugopalan, M. A. Chalkiadaki, M. A. U. Karim, H. Agarwal, S. Khandelwal, N. Paydavosi, J. P. Duarte, C. C. Enz, A. M. Niknejad, and C. Hu, “BSIM6: Analog and RF compact model for bulk MOSFET,” IEEE Trans. Electron Dev., vol. 61, no. 2, pp. 234–244, Feb. 2014.
[6] C. Enz, M. A. Chalkiadaki, and A. Mangla, “Low-power analog/RF circuit design based on the inversion coefficient,” in Proc. European Solid-State Circ. Conf., Sept. 2015, pp. 202–208.
[7] C. Enz and A. Pezzotta, “Nanoscale MOSFET modeling for the design of low-power analog and RF circuits,” in Proc. Int. Conf. MIXDES, June 2016, pp. 21–26.
[8] W. Sansen, “Analog CMOS from 5 micrometer to 5 nanometer,” in Proc. IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers, Feb. 2015, pp. 1–6.
[9] W. Sansen, “Analog design procedures for channel lengths down to 20 nm,” in Proc. IEEE 20th Int. Conf. Electronics, Circuits, and Systems, Dec. 2013, pp. 337–340.
[10] C. C. Enz and E. A. Vittoz, Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design. Hoboken, NJ: Wiley, 2006.
[11] C. C. Enz, F. Krummenacher, and E. A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications,” Analog Integr. Circuits Signal Process. J., vol. 8, pp. 83–114, July 1995.
[12] P. Heim, S. R. Schultz, and M. A. Jabri, “Technology-independent biasing technique for CMOS analogue micropower implementations of neural networks,” in Proc. Sixth Australian Conf. Neural Networks, Sydney, Australia, 1995, pp. 9–12.
[13] C. C. Enz and E. A. Vittoz, “CMOS low-power analog circuit design,” in EmergingTechnologies: Designing Low Power Digital Systems, R. Cavin and W. Liu, Eds. Piscataway, NJ: IEEE, 1996, pp. 79–133.
[14] E. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operations,” IEEE J. Solid-State Circuits, vol. 12, no. 3, pp. 224–231, June 1977.
[15] A. Mangla, C. C. Enz, and J. M. Sallese, “Figure-of-merit for optimizing the current efficiency of low-power RF circuits,” in Proc. Int. Conf. Mixed Design Integrated Circuits and Systems, June 2011, pp. 85–89.
[16] A. Mangla, “Modeling nanoscale quasi-ballistic MOS transistors,” Ph.D. dissertation, EPFL, Switzerland, Dissertation No. 6385, 2014.
[17] R. R. Troutman and A. G. Fortino, “Simple model for threshold voltage in a short- channel IGFET,” IEEE Trans. Electron. Dev., vol. 24, no. 10, pp. 1266–1268, Oct. 1977.
[18] N. Arora, MOSFET Models for VLSI Circuit Simulation. New York: Springer-Verlag, 1993.
[19] Z. H. Liu, C. Hu, J. H. Huang, T. Y. Chan, M. C. Jeng, P. K. Ko, and Y. C. Cheng, “Threshold voltage model for deep submicrometer MOSFETs,” IEEE Trans. Electron Dev., vol. 40, no. 1, pp. 86–95, Jan. 1993.
[20] M. A. Chalkiadaki, “Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design,” Ph.D. dissertation, EPFL, Switzerland, Dissertation No. 7030, 2016.

Jul 25, 2017

[paper] Compact On-Wafer Test Structures for Device RF Characterization

B. Kazemi Esfeh, K. Ben Ali and J. P. Raskin IEEE Fellow
Compact On-Wafer Test Structures for Device RF Characterization
in IEEE TED, vol. 64, no. 8, pp. 3101-3107, Aug. 2017
doi: 10.1109/TED.2017.2717196

Abstract: The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50um pitch RF probes. It is shown that by using these new test structures, the layout geometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs, is divided by a factor of two. The validity domain of these new compact test structures is demonstrated by comparing their measurement results with classical test structures compatible with 100–150um pitch RF probes. 50um -pitch de-embedding structures have been implemented on 0.18um RF silicon-on-insulator (SOI) technology. Cutoff frequencies and parasitic elements of the RF SOI transistors are extracted and the RF performance of trap-rich SOI substrates is analyzed under small- and large-signal conditions [read more...]



Feb 17, 2017

[call for papers] 2017 IEEE S3S Conference

S3S Conference 2017
Overview: This industry - wide event has gathered, for over 30 years, industry leaders and widely known experts, in a social - oriented environment. Our contributed papers and invited talks are focused on SOI Technology, Low - Voltage Devices/Circuits/Architectures, and 3D Integration. These 3 technologies will play a major role in tomorrow's industry as they enable application - tailored and Energy / Cost efficient circuit designs.
Important Dates
Paper Submission Deadline: May 22, 2017
Acceptance Notification: July 1, 2017

The conference at a glance
Monday to Wednesday, Oct. 16-18, 2017: Technical Sessions
Thursday, Oct.19: Fully - Depleted SOI Circuit Design; Full-day Tutorial
Tuesday, Oct.17: Monolithic 3D Half-day Tutorial

Scope: We welcome papers in the following areas:
Silicon On Insulator (SOI)
• Advanced Materials, Substrate and Processes
• Device Physics, Characterization and Modeling
• Device/Circuit Integration
• SOI Design, Circuits and Applications
• Non-Digital Devices and Applications (RF,
HV, Photonics, NEMS, MEMS, Analog...)
• New SOI Structures, Circuits and Applications
Low-Voltage Microelectronics
• Space-Based and Unattended Remote Sensors
• Biomedical Devices
• Low-Voltage Handheld/wireless systems
• Ultra-Low-Power Digital Computation
• Analog and RF Technologies
• Low Voltage Memory Technologies
• Energy Harvesting Techniques
• Asynchronous Circuits
• Novel Device and Fabrication Technology
3D Integration
• Low Thermal Budget Processing
• Fabrication Techniques and Bonding Methods
• Design and Test Methodologies
• Processes for Multi Wafer Stacking
• 3D IC EDA and Design Technology
• Heterogeneous Structures
• 3D Manufacturing and Logistics
• Reliability of 3D Circuits
• Fault Tolerant 3D Designs

Paper Submission:
Prospective authors should prepare a 2page abstract (follow online guidelines).
Acceptance is based on paper’s technical quality and relevance.

Conference manager contact Joyce Lloyd
6930 De Celis Pl., #36
Van Nuys, CA 91406
Tel: +1 818 795 3768
Fax: +1 818 855 8392

Feb 9, 2017

[paper] RF-MEMS for Future Mobile Applications: Experimental Verification of a Reconfigurable 8-Bit Power Attenuator up to 110 GHz

RF-MEMS for Future Mobile Applications: Experimental Verification of a Reconfigurable 8-Bit Power Attenuator up to 110 GHz
Jacopo Iannacci1 and Christian Tschoban2
1Center for Materials and Microsystems - CMM, Fondazione Bruno Kessler , Trento, ITALY
2Fraunhofer Institut für Zuverlässigkeit und Mikrointegration IZM , Berlin, GERMANY
Journal of Micromechanics and Microengineering
Accepted Manuscript online 8 February 2017
Abstract
RF-MEMS technology is indicated as a key enabling solution to realise the high-performance and highly-reconfigurable passive components that future 5G communication standards will demand for. In this work, we present, test and discuss a novel design concept of an 8-bit reconfigurable power attenuator manufactured in the RF-MEMS technology available at the CMM-FBK, in Italy. The device features electrostatically controlled MEMS ohmic switches, in order to select/deselect resistive loads (both in series and shunt configuration) that attenuate the RF signal, and comprises 8 cascaded stages (i.e. 8-bit), thus implementing 256 different network configurations. Fabricated samples are measured (S-parameters) from 10 MHz to 110 GHz in a wide range of different configurations, and modelled/simulated in Ansys HFSS. The device exhibits attenuation levels (S21) in the range from -10 dB to -60 dB, up to 110 GHz. In particular, the S21 shows flatness from 15 dB down to 3-5 dB, from 10 MHz to 50 GHz, while less linear traces up to 110 GHz. Comprehensive discussion is developed around the Voltage Standing Wave Ratio (VSWR), employed as quality indicator for the attenuation levels. Margins of improvement at design level are also discussed, in order to overcome the limitations of the presented RF-MEMS device. The results of S-parameter simulations performed in the Quite Universal Circuit Simulator (QUCS: qucs.sourceforge.net) for a few significant configurations of the RF-MEMS attenuator from 10MHz to 110GHz are reported, too. [read more...]