[EUMW.EU] IHP Open Source Toolchain

Open-source Toolchain in RF and Digital Design

08:30 - 12:50; Monday 5 October 2026

European Microwave Week 

WM02, Room 3, ExCeL, London

The European Chips Act serves as a strategic roadmap to secure technological sovereignty by aiming for a 20% global market share in semiconductors by 2030. The goal is to minimize the geopolitical supply chain risks and foster a self-sufficient ecosystem. Democratization of hardware development through the development of open-source EDA tools is a key pillar in these aspects. This would lower the entry barriers for SMEs and researchers and ultimately accelerate a collaborative and transparent era of European silicon innovation. There are multiple EU funded projects have started from last few years. These projects are set to offer robust process design kits (PDK) for open-source tools. In parallel, existing open-source tools for IC design are being further enhanced to include necessary functionalities for complete design flow for digital, analogue and RF design. Aligning with above mentioned goals, multiple private, academic, and commercial entities have stepped up towards the development. This workshop aims to share a glimpse of activities in open-source EDA tools developments and chip design activities in Europe. It would begin with a talk about current EU projects and the statuses in open-source EDA development. Then there will be two talks about digital and RF design flow using open-source tools. The final talk is about electro-magnetic simulation for RF circuits. Overall, this workshop is targets to publicize the open-source activities towards the building of a collaborative society in chip design domain. 

The event is aimed at IC designers, researchers, PhD candidates and engineers who already have a basic understanding of chip design and EDA workflows. Familiarity with digital, analogue or RF design will help you get the most from the sessions.

This workshop, chaired by the IHP Team: Corrado Carta, Sergei Andreev, and Farabi Ibne Jamal, gives you a practical view on the following Open-Source R&D Topics:

• European Open-Source EDA projects currently stand
• Sergei Andreev, IHP
• How digital design flows can be built with Open-Source tools
• Frank Kagan Gurkaynak, ETH Zürich
• How Open-Source tools are being applied to RF design 
• Harald Pretl, Johannes Kepler Universität Linz
• How Open-Source EM simulation fits into RF circuit development
• Giovanni Di Pietrantonio, IHP and Volker Mühlhaus, MCS, GmbH

Join the IHP OpenPDK Team if you want to understand where open-source chip design is heading, what is already usable today, and how these tools could complement your own work. Register at the EuMW website.

[program] ICMC2026

INTERNATIONAL COMPACT MODELING CONFERENCE PROGRAM

2026.si2-icmc.org

The 2026 conference continues under the theme “Enhancing Collaboration in Modeling with the Semiconductor Industry.” This year, ICMC especially encourages contributions in several timely and important areas, including electrostatic discharge (ESD) modeling for protection design, reliability and aging-aware compact models and simulation techniques, and the use of AI or machine learning for model development, parameter extraction, and circuit simulation efficiency. The conference also covers a broad range of topics in compact modeling, including the application of device models, device model development, model enhancements and implementations, and emerging devices.

This year’s technical program includes 3 keynote speakers, 7 invited speakers, 28 technical talks, 12 posters and a panel session. The program reflects both the depth and diversity of current modeling research and practice, ranging from model calibration and validation methodologies to reliability, RF, high-voltage, cryogenic, and emerging device applications.

Program at a Glance

Speaker	Title
	Keynote Presentations
Chenming Hu	BSIM, FinFET, and Open Innovation
Yuan Taur	Physical Insights Beyond the Textbook Modeling of MOSFETs and pn-junctions
Elyse Rosenbaum	Measurement Challenges Impeding the Verification of ESD Compact Model Accuracy and Generalizability
	Invited Presentations
James Victory	Modeling and Simulation Challenges in Modern Power Discrete Semiconductor Technologies
Gilson Wirth	Modeling of Low-Frequency Noise and BTI in Electron Devices
Chien-Ting Tung	Application of AI and ML in the Compact Modeling Domain
Michael Stockinger	On-Chip ESD Protection Design Optimization Using ESD Device Compact Models
Darsen Lu	Ferroelectric Memory Devices Compact Modeling and Applications
Meng-Lin Lu	Applications of Machine Learning Techniques in the Compact Modeling Platform
Lorenzo Peri	Compact Quantum Dot Models for Hybrid Microwave Circuits and Quantum Information Processing

Program Grid – Friday, July 30

Time	Session
8:30 - 8:45	Day 1 Welcome (Queens Salon)
8:45 - 9:25	[Keynote] BSIM, FinFET, and Open Innovation by Prof. Chenming Hu
9:25 - 10:25	Advances in Compact Modeling (Queens Salon)
10:25 - 10:45	Coffee Break (Royal Salon & Kings View Room)
10:45 - 12:10	Ferroelectric and other Nonvolatile Memories (Queens Salon)
12:10 - 13:20	Lunch Served (Royal Salon & Kings View Room)
13:20 - 14:00	[Keynote] Physical Insights Beyond the Textbook Modeling of MOSFETs and p-n Junctions by Prof. Yuan Taur
14:00 - 15:05	Emerging Devices and Technologies (Queens Salon)
15:05 - 15:25	Coffee Break (Royal Salon & Kings View Room)
15:25 - 16:30	Wide Bandgap Material Device Models (Queens Salon)
16:30 - 17:00	Poster Introductions (Queens Salon)
17:00	Poster Session & Reception (Verandah Grill/Deck)

Program Grid – Friday, July 31

Time	Session
8:30 - 8:40	Day 2 Welcome (Queens Salon)
8:40 - 9:20	[Keynote] Measurement Challenges Impeding the Verification of ESD Compact Model Accuracy and Generalizability by Prof. Elyse Rosenbaum
9:20 - 10:05	ESD Protections Modeling (Queens Salon)
10:05 - 10:25	Coffee Break (Royal Salon & Kings View Room)
10:25 - 11:55	Machine Learning and Artificial Intelligence in Compact Modeling (Queens Salon)
11:55 - 12:55	Lunch Served (Royal Salon & Kings View Room)
12:55 - 13:55	Panel Session: Machine Learning for Compact Modeling – Promises, Pitfalls, and Paths to Industry Adoption
13:55 - 14:40	Modeling of Noise and Traps (Queens Salon)
14:40 - 15:00	Coffee Break (Royal Salon & Kings View Room)
15:00 - 16:20	Devices at Cryogenic Temperatures (Queens Salon)
16:20 - 17:00	Closing Ceremony & Awards (Queens Salon)

[paper] Cryo FD SOI LNA Design

Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Jose Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mikael Casse, Philippe Galy

Using DC transistor characterization measurements for LNA design at cryogenic temperatures

(2026) researchsquare.com

DOI: 10.21203/rs.3.rs-7754596/v1

1. STMicroelectronics, Crolles (F)
2. Univ. Grenoble Alpes, CNRS, Grenoble-INP, TIMA, Grenoble (F)
3. Univ. Grenoble Alpes, CEA-Leti, Grenoble (F)
4. Univ. Grenoble Alpes, CNRS, Grenoble-INP, IMEP-LAHC, Grenoble (F)

Abstract: The design of Radio Frequency (RF) cryogenic circuits has attracted much interest in recent years due to applications such as quantum computers. Interface electronics with ultra-low levels of power consumption at temperatures as low as 4 K are required. Silicon technologies are being considered for implementation because of the possibility of large-scale qubit integration with energy-efficient readout and control interfaces. However, the design of RF cryogenic circuits is complicated because of the lack of standard design kits with the corresponding component models for their simulation at these temperatures. Alternative approaches to avoid costly design and fabrication cycles are possible, in particular the use of Look-Up-Table (LUT) based techniques that exploit characterization data of circuit components at cryogenic temperature. In this paper, we make use of this approach for the design of a RF Low Noise Amplifier (LNA) using a 28 nm FD-SOI technology that has been characterized at cryogenic temperatures1using DC measurements. Furthermore, we also experimentally demonstrate that the DC measurements used are valid to extract the transistor noise parameters used in the LUT-based analysis.

Fig: Measurement of: (a) transconductance gm, and (b) threshold voltage Vth 

for the 28nm FD-SOI technology, from 300K down to 4K.

Acknowledgements: This work was supported by the French CIFRE program and the Labex MINOS of French program ANR-10-LABX-55-01.

[book] CMOS RF and mm-Wave Transceivers and Synthesizers

CMOS RF and mm-Wave Transceivers and Synthesizers

(1st ed. 2025)

By Bharatha Kumar Thangarasu, Nagarajan Mahalingam, 

Kaixue Ma, Kiat Seng Yeo

Jenny Stanford Publishing

DOI 10.1201/9781003673569

Abstract: Power consumption has become a critical concern in RF/mm-wave integrated circuit (IC) design thanks to new applications from 5G, mobile computing, artificial intelligence, and the Internet of Things. However, big challenges lie ahead for chip designers when they choose to develop ICs using silicon technology for low-power and high-data-rate applications. This is because silicon technology suffers from undesirable energy dissipation due to its lossy substrate and high resistive wiring loss at GHz frequencies. Nonetheless, silicon remains the most suitable material, satisfying the demands of a rapidly growing semiconductor market through low fabrication cost and ease of achieving system-on-chip or system-in-package integration. While long being neglected, low-power RF/mm-wave design has vaulted to the forefront of attention in recent years due to the demand for ultra-low-power transceivers to achieve sustainability. Designing genuinely ubiquitous transceivers for these new applications requires innovations in both system architecture and circuit implementation.

This book closes the gap between a typical textbook with theories that are difficult to understand and a design-oriented book that offers little insight into actual theories. It evaluates and discusses different circuit topologies, receiver and transmitter architectures, phase-locked loop performance metrics, phase noise analysis, and sub-system-level designs that have yet to be reported in other books.

Table of Contents

• Chapter 1: CMOS RF Active and Passive Devices (pp. 1–49)
• Chapter 2: Transceiver Building Blocks (pp. 50–126)
• Chapter 3: Receiver Sub-System (pp. 127–193)
• Chapter 4: Transmitter Sub-System (pp. 194–238)
• Chapter 5: Transceiver System Integration (pp. 239–347)
• Chapter 6: CMOS RF/mm-Wave Oscillators (pp. 348–401)
• Chapter 7: CMOS Frequency Synthesizers (pp. 402–482)

[paper] Symmetric BSIM-SOI

Chetan Kumar Dabhi, Dinesh Rajasekharan, Girish Pahwa, Debashish Nandi, Naveen Karumuri, Sreenidhi Turuvekere, Anupam Dutta, Balaji Swaminathan, Srikanth Srihari, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu

Symmetric BSIM-SOI: A Compact Model for Dynamically Depleted SOI MOSFETs 

 in IEEE TED (2024)

Part I DOI: 10.1109/TED.2024.3363110

Part II DOI: 10.1109/TED.2024.3363117

1 Department of Electrical Engineering and Computer Sciences, UCB, CA, USA

2 Department of Electrical Engineering, IIT Kanpur, India

3 GlobalFoundries, Bengaluru, India

Abstract: In this article, we present a symmetric surface-potential-based model for dynamic depletion (DD) device operation of silicon-on-insulator (SOI) FETs for RF and analog IC design applications. The model accurately captures the device behavior in partial depletion (PD) and full depletion (FD) modes, as well as in the transition from PD to FD, based on device geometry, doping, and bias conditions. The model also exhibits an excellent source–drain symmetry during dc and small-signal simulations, resulting in error-free higher order harmonics. The model is fully scalable with bias, temperature, and geometry and has been validated extensively with real device data from the industry. The symmetric BSIM-SOI model is developed in Verilog-A and compatible with all commercial SPICE simulators.

FIG: (a) Schematic of a typical SOI MOSFET

(b) Cgg versus Vgb for different substrate bias, with the PD-to-FD transition 

Acknowledgment: The authors thanks the members of the Compact Model Coalition (CMC), particularly Geoffrey J. Coram and Jushan Xie, for testing the model and suggesting improvements. The authors appreciate the CMC QA team’s efforts in conducting a model quality check. Caixia Han and Xiao Sun from Cadence provided a few useful test cases. They thank Ananth Sundaram and Anamika Singh Pratiyush from GlobalFoundries India for the help and discussion regarding DDSOI model intricacies and development. Model code is available at BSIM Website <https://bsim.berkeley.edu/models/bsimsoi/>

[paper] PSP RF Model

Xiaonian Liu1, 2, and Yansen Liu1, 2

Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract: An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 µm CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The PSP RF subcircuit model and its S-par s fitting

results of NMOS with Wf = 2 µm, Lf = 0.12 µm, nf = 16

Acknowledgment: This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

[paper] PSP RF Model

Xiaonian Liu^{1, 2} and Yansen Liu¹

A Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

DOI :10.2528/PIERL23081405

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China.
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract : An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The RF PSP Model Subcircuit

Acknowledgment : This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

OpenPDK Networking Workshop

OpenPDK, OpenTooling and Open Source Design

An Initiative to Push Development

Date:
Networking Workshop FMD-QNC on 27-28 June 2023
Location:
IHP; Im Technologiepark 25; 15236 Frankfurt (Oder)
Contact:
Sergei Andreev; Phone: +49 335 5625 523

Free Registration: 

OnLine

The workshop is organised by IHP and FMD (Research Fab Microelectronics Germany) within the framework of the FMD-QNC Project.

Within the project FMD-QNC analog circuit design with open source software shall be enabled. For this purpose, both the open source design tools and a process design kit of the semiconductor technology used must support the entire design flow with sufficient quality. IHP provides its 130 nm BiCMOS technology SG13G2 for open source design. This technology is particularly suited for high frequency and mixed signal design applications. While basic tool support already exists for digital circuit design, it is still very rudimentary for analog designs and especially for high frequency designs. A considerable effort has to be put into the development of the design tools as well as into the creation of the technology specific Process Design Kit (PDK).

The 2-day workshop is intended to promote exchange and networking between tool developers, the PDK developers at IHP and designers. Tool developers are to present the capabilities of the tools as well as planned enhancements. Designers are to present ideas that can be used for training chip designers. Requirements for open source design tools for digital design, mixed signal design, and high frequency design are to be highlighted.

Discussions will identify and prioritize gaps for a complete design flow in the open source tools and PDK. The workshop will thus help to concrete the planning for the Open Design Platform and to create a roadmap for future work.

Presentation	Presenter/Institution	Timeline
Day 1
Welcome by coordinator FMD-QNC	Dr. Andreas Bruning Research Fab Microelectronics Germany	9:00-9:10
Introduction FMD-QNC project status and IHP OpenPDK Roadmap	Dr. Rene Scholz IHP	9:10-9:30
Status OpenPDK and OpenTooling for SG13G2 BiCMOS technology	Sergei Andreev IHP	9:30-10:00
An Ultra-Low-Power High-Density Wireless Biomedical Sensing System	Prof. Harald Pretl Johannes Kepler University Linz	10:00-10:30
Teaching digital design by using open-source EDA tools	Prof. Steffen Reith Rhein Main University of Applied Sciences	10:30-11:00
Coffee break		11:00-11:40
CMOS Rail-to-Rail Operational Amplifier for HPGe Radiation Detector	Prof. Herman Jalli Ng Karlsruhe University of Applied Sciences	11:40-12:10
Design-flow approaches for mmWave and sub-THz integrated transceiver circuits for radar and communication	Sasha Breun FAU Erlangen	12:10-12:40
Lunch break		12:40-13:40
TBD	Dr. Frank K. Gurkaynak ETH Zurich	13:40-14:10
TBD	Joachim Hebeler Karlsruhe Institute of Technology	14:10-14:40
Coffee break		14:40-15:10
TBD	Prof.  Dietmar Kissinger Ulm University	15:10-15:40
LibMan - an easy way to manage your open source design flow	Dr. Anton Datsuk IHP	15:40-16:10
Get together (Barbecue)		17:00-…
Day 2
ngspice - status and future developments	Prof. Holger Vogt	9:00-9:20
DMT - Python Toolkit for Device Modeling	Mario Krattenmacher SemiMod	9:20-9:40
OpenVAF - Next Generation Verilog-A Compiler with ngspice integration	Mario Krattenmacher SemiMod	9:40-10:00
Coffee break		10:00-10:40
Best practices for implementing and optimizing KLayout DRC and LVS decks	Matthias Köfferlein	10:40-11:00
Generating DRC and LVS Runsets for KLayout	Dr. Andreas Krinke TU Dresden	11:00-11:20
OpenEMS in open source EDA	Jan Taro Svejda University of Duisburg-Essen	11:20-11:40
Lunch break		11:40-12:40
Panel discussion on the roadmap – open source tools for IC design Topics: Digital design flow Analog design flow Challenges in RF design	Dr. Norbert Herfurth IHP Panelists: TBD	12:40-14:10

[C4P] T-ED Special Issue

Call for Papers - Special Issue on "Wide and Ultrawide Band Gap Semiconductor Devices for RF and Power Applications."

The Special Issue of the IEEE Transactions on Electron Devices (T-ED) will report the most advanced and recent results in the field of wide and ultrawide bandgap semiconductor materials and devices, including papers focused on material fabrication, device processing, reliability investigation, device modeling, thermal aspects, and system-related results.

Submission deadline: 31 August 2023
Publication date: February 2024

Submit papers today: https://bit.ly/3fESTgZ

Guest Editors: 

Prof. Matteo Meneghini, University of Padova, Italy 

Prof. Patrick Fay, University of Notre Dame, USA 

Prof. Digbijoy Nath, IISC Bangalore 

Prof. Geok Ing Ng, Nanyang Technical University, Singapore 

Prof. Junxia Shi, University of Illinois, Chicago 

Prof. Shyh-Chiang Shen, Georgia Tech. 

[paper] Pseudo-morphic PHEMT: Numerical Simulation Study

Khaouani Mohammed, Hamdoune Abdelkader, Guen Ahlam Bouazza, Kourdi Zakarya, Hichem Bencherif

An Improved Performance of Al0.25Ga0.75N/AlN/GaN/Al0.25Ga0.75N Pseudo-morphic High Electron Mobility Transistor (PHEMT): 

Numerical Simulation Study

IC-AIRES 2021. Lecture Notes in Networks and Systems, vol 361. Springer

DOI: 10.1007/978-3-030-92038-8_80

1. Hassiba Benbouali, Chlef, Algeria

2. University of Abou-Bakr Belkaid, Tlemcen, Algeria
3. Center Exploitation Satellite Communications Agency of Space Oran, Algeria
4. University of Mostefa Benboulaid, Batna, Algeria 

Abstract: In this paper a 9nm T-shaped gate length, Pseudo-morphic High Electron Mobility Transistor (pHEMT AlGaN/AlN/GaN/AlGaN) is studied; we use TCAD software. DC, AC and RF performances assessment allow to exhibit interesting results such as a maximum drain current IDSmax=35mA at VGS=0V, a knee voltage Vknee=0.5V with ON-resistance Ron=0.8Ω-mm, a sub-threshold swing of 75mV/decade, a maximum transconductance value gm=160mS/mm, a DIBL of 36mV/V, a drain lag of 8.5%, a cut-off frequency of 110GHz, a maximum oscillation frequency of 800GHz, and very suitable breakdown voltage VBR of 53.1V. This device can be used in radar, high power and amplifier applications.

[book] Advanced ASM-HEMT Model for GaN HEMTs

Sourabh Khandelwal

Advanced SPICE Model for GaN HEMTs (ASM-HEMT)

A New Industry-Standard Compact Model 

for GaN-based Power and RF Circuit Design

DOI: 10.1007/978-3-030-77730-2

eBook ISBN: 978-3-030-77730-2

Describes in detail a new industry standard for GaN-based power and RF circuit design. Includes discussion of practical problems and their solutions in GaN device modeling. Covers both radio-frequency (RF) and power electronics application of GaN technology and describes SPICE modeling of both GaN RF and power devices.

Table of contents:

• Front Matter; pp. i-xv
• Gallium Nitride Semiconductor Devices; pp. 1-8
• Compact Modeling; pp. 9-19
• Introduction to ASM-HEMT Compact Model; pp. 21-31
• Core Formulations in ASM-HEMT Model; pp. 33-45
• Non-ideal Effects in Device Current and Their Modeling; pp. 47-62
• Trapping Models; pp. 63-81
• Non-Ideal Effects in GaN Capacitances and Their Modeling; pp. 83-100
• Gate Current Model; pp. 101-113
• Effect of Ambient Temperature on GaN Device; pp. 115-124
• Noise Models; pp. 125-130
• Parameter Extraction in ASM-HEMT Model; pp. 131-150
• Advance Simulations with ASM-HEMT Model; pp. 153-174
• Resources for ASM-HEMT Model Users; pp. 175-175
• Back Matter; pp. 175-188

About the author:

Sourabh Khandelwal is Senior Lecturer at the School of Engineering at Macquarie University, Sydney. He is the lead developer of ASM--HEMT compact model, which is a new industry standard compact model for GaN RF and power devices. Earlier to this role, Manager of Berkeley Device Modeling Center and Postdoctoral Researcher at the BSIM group at University of California, Berkeley. Before that, he worked as Research Engineer at IBM Semiconductor Research. He has over 200 publications in top-tier conferences and journals in the area of semiconductor device modeling and circuit design.

Advances in RF and THz emerging electronic devices webinar at IPN-UAB

The webinar joitly co-organize together with Instituto Politécnico Nacional, Mexico 

is intended to present and discuss recent advances in RF and THz emerging electronic devices.

Feel free to share the information with your colleagues and/or students. The registration is free, and you can do it here (it is in Spanish but the only required fields are Name, Surname, Email, and Email confirmation). Alternatively, you can follow the live stream in this youtube channel.

The time appearing in the flyers are referred to Mexico City's time. The schedule is starting each day Nov.16-18, 2021 at 16 hrs CET.

If you have further questions you can contact 

• Aníbal Uriel Pacheco Sanchez or 
• Eloy Ramirez Garcia, IPN co-organizer

   

[paper] 11.8 GHz Fin Resonant Body Transistor

Analysis and Modeling of an 11.8 GHz Fin Resonant Body Transistor 

in a 14nm FinFET CMOS Process 

Udit Rawat, Student Member, IEEE, Bichoy Bahr*, Member, IEEE, 

and Dana Weinstein, Senior Member, IEEE

arXiv:2107.04502v1 [physics.app-ph] 9 Jul 2021

 

Department of Electrical Engineering, Purdue University, West Lafayette USA

*Kilby Labs - Texas Instruments, Dallas, TX, USA.

Abstract: In this work, a compact model is presented for a 14 nm CMOS-based FinFET Resonant Body Transistor (fRBT) operating at a frequency of 11.8 GHz and targeting RF frequency generation/filtering for next generation radio communication, clocking, and sensing applications. Analysis of the phononic dispersion characteristics of the device, which informs the model development, shows the presence of polarization exchange due to the periodic nature of the back-end-of-line (BEOL) metal PnC. An eigenfrequency-based extraction process, applicable to resonators based on electrostatic force transduction, has been used to model the resonance cavity. Augmented forms of the BSIM-CMG (Common Multi-Gate) model for FinFETs are used to model the drive and sense transistors in the fRBT. This model framework allows easy integration with the foundry-supplied process design kits (PDKs) and circuit simulators while being flexible towards change in transduction mechanisms and device architecture. Ultimately, the behaviour is validated against RF measured data for the fabricated fRBT device under different operating conditions, leading to the demonstration of the first complete model for this class of resonant device integrated seamlessly in the CMOS stack.

Fig: Complete 3D FEM Simulation model depicting two adjoining fRBT unit cells. Mx (x=1-3) and Cy (y=4-6) represent the first 6 metal levels that form a part of the BEOL PnC.

Acknowledgement: This work was supported in part by the DARPA MIDAS Program.

 

[paper] 3D integrated GaN/RF-SOI SPST switch

Frédéric Drillet, Jérôme Loraine, Hassan Saleh, Imene Lahbib, Brice Grandchamp, Lucas Iogna-Prat, Insaf Lahbib, Ousmane Sow, Albert Kumar and Gregory U'Ren 

RF Small and large signal characterization of a 3D integrated GaN/RF-SOI SPST switch 

International Journal of Microwave and Wireless Technologies, pp. 1–6, 2021.

*X-FAB France, Corbeil-Essonnes (F)

Abstract: This paper presents the radio frequency (RF) measurements of an SPST switch realized in gallium nitride (GaN)/RF-SOI technology compared to its GaN/silicon (Si) equivalent. The samples are built with an innovative 3D heterogeneous integration technique. The RF switch transistors are GaN-based and the substrate is RF-SOI. The insertion loss obtained is below 0.4 dB up to 30 GHz while being 1 dB lower than its GaN/Si equivalent. This difference comes from the vertical capacitive coupling reduction of the transistor to the substrate. This reduction is estimated to 59% based on a RC network model fitted to S-parameters measurements. In large signal, the linearity study of the substrate through coplanar waveguide transmission line characterization shows the reduction of the average power level of H2 and H3 of 30 dB up to 38 dBm of input power. The large signal characterization of the SPST shows no compression up to 38 dBm and the H2 and H3 rejection levels at 38 dBm are respectively, 68 and 75 dBc.

Fig: X-FAB 3D integration proposal cross-section (left) and the picture of a GaN coupon (right).

Acknowledgement: We would like to acknowledge the Nano2022 program for partially funding this work.

Supplementary material: The supplementary material for this article can be found at DOI: 0.101/1759078721000076

[thesis] RF UTBB FDSOI MOSFET

Vanbrabant, Martin

RF characterization of the back-gate contact on Fully Depleted SOI MOSFETs

http:// hdl.handle.net/2078.1/thesis:26763

Ecole polytechnique de Louvain, Université catholique de Louvain, 2020. 

Academic year 2019–2020: Master in Electrical Engineering

Prom.: Prof. Jean-Pierre Raskin

Readers: Denis Flandre, Valeriya Kilchytska, Lucas Nyssens, Martin Rack

Abstract: Thanks to the thin buried-oxide, the UTBB FDSOI technology with a highly doped region under the BOX is one of the main candidates for future RF applications. One of the most interesting feature of this technology is the possibility to tune the threshold voltage, compensate variability issues and improve the overall device performance. In this work, the impact of the back-gate bias is mainly studied on the threshold voltage and RF FoMs of the front and back-gates.

Figure: Reconstructed (dashed) vs initial (full) Re{Yij} insaturationat VDS=0.8V, VGS=0.8V and VB=0V for a 4-port device.

[paper] RF Small-Signal Model for Four-Port Network MOSFETs

A High-Frequency Small-Signal Model for Four-Port Network MOSFETs

Alejandro Roman-Loera¹, Member, IEEE, Anurag Veerabathini², Member, IEEE, Luis A.Flores-Oropeza¹, Member, IEEE, and Jaime Ramirez-Angulo³, Life Fellow, IEEE

IEEE 63rd IMWSCAS 2020

DOI:10.1109/mwscas48704.2020.9184475 

¹Electronic Systems Department, Universidad Autonoma de Aguascalientes, Mexico.
²Maxim Integrated, Chandler, AZ, USA.
³Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA.

Abstract: A high-frequency small-signal model for a MOSFET is proposed considering the parasitic capacitances associated with each terminal that is critical in the design of high-frequency amplifiers. The proposed model allows in obtaining a closed form expression for poles and zeros due to parasitic elements along with the conventional poles and zeros. This model gives an additional degree of freedom in choosing the location of poles and zeros to improve the frequency response. The proposed high-frequency small-signal model for MOSFET is validated in simulation by implementing a high-frequency voltage follower in 0.18µm CMOS process. The proposed model shows the existence of a zero in a voltage follower that is introduced by the parasitic elements at high-frequencies and it is validated with implementation.

Fig: Small signal equivalent circuit of a 4-port MOSFET (a) Conventional model, (b) Model with substrate parasitics, and (c) Model with additional parasitics, and (d) Proposed model.

Acknowledgment: This work has been supported by PRODEP program from SEP (Secretariat of Public Education, Mexico) and Universidad Autonoma de Aguascalientes, Aguascalientes, Mexico.

Broadband Measurements to 220 GHz

VectorStar ME7838G 70 kHz to 220 GHz Single Sweep VNA Measurements and On-Wafer Calibrations

• Miniature mmWave MA25400A NLTL module connects directly to probes without cables for best dynamic range and stability
• MPI TITAN Probes available in 50, 75, and 100 um pitch
• Probes are field replaceable

On-wafer calibrations:

• SOLT up 40 or 70 GHz if standards provide required performance
• LRM, ALRM, LRRM, and multiline TRL up to 220 GHz
• SOLR when thru is not 0 length, is not well matched, insertion loss is less known, and there is no .s2p file describing the thru

Calibration substrates:

• Available from MPI
• When possible, use a ceramic chuck to minimize the potential for multimode parasitic propagation.
• Alternatively, use an isolation wafer on metal chuck if available

[paper] IoT Vision empowered by EH-MEMS and RF-MEMS

Internet of things (IoT); internet of everything (IoE); tactile internet; 5G
A (not so evanescent) unifying vision empowered 
by EH-MEMS (energy harvesting MEMS) and RF-MEMS (radio frequency MEMS)

 Jacopo Iannacci
Fondazione Bruno Kessler (FBK) in Trento (IT)

Sensors and Actuators A: Physical 272 (2018): 187-198

Abstract: This work aims to build inclusive vision of the Internet of Things (IoT), Internet of Everything (IoE), Tactile Internet and 5G, leveraging on MEMS technology, with focus on Energy Harvesters (EH-MEMS) and Radio Frequency passives (RF-MEMS). The IoT is described, stressing the pervasivity of sensing/actuating functions. High-level performances 5G will have to score are reported. Unifying vision of the mentioned paradigms is then built. The IoT evolves into the IoE by overtaking the concept of thing. Further step to Tactile Internet requires significant reduction in latency, it being enabled by 5G.

The discussion then moves closer to the hardware components level. Sets of specifications driven by IoT and 5G applications are derived. Concerning the former, the attention is concentrated on typical power requirements imposed by remote wireless sensing nodes. Regarding the latter, a set of reference specifications RF passives will have to meet in order to enable 5G is developed. Once quantitative targets are set, a brief state of the art of EH-MEMS and RF-MEMS solutions is developed, targeting the IoT and 5G, respectively. In both scenarios, it will be demonstrated that MEMS are able to address the requirements previously listed, concerning EH from various sources and RF passive components.

FIG: Scheme of the pillar drivers supporting evolution of the IoT into IoE andTactile Internet.
Some relevant IoT technology enablers are indicated.

In conclusion, the frame of reference depicted in this work outlines a relevant potential borne by EH-MEMS and RF-MEMS solutions within the unified scenario of IoT, IoE, Tactile Internet and 5G, making the forecast of future relentless growth of MEMS-based devices, more plausible and likely to take place.

ICMTS2020 #paper: Cutoff Frequency Fluctuation in RF-MOSFETs

2020 ICMTS, April 6-9, Edinburgh (UK)
Novel Statistical Modeling and Parameter Extraction Methodology
of Cutoff Frequency for RF-MOSFETs

Chika Tanaka, Yasuhiko Iguchi, Atsushi Sueoka, and Sadayuki Yoshitomi

Memory Division, Kioxia Corporation

2-5-1, Kasama, Sakae-ku, Yokohama, 247-8585, Japan

Abstract: The cutoff frequency fluctuation in RF-MOSFET has been investigated. Detailed analysis for capacitance fluctuation as well as the extraction of an intrinsic MOSFET parameter were performed. The extracted process parameters were verified by the framework of effective mobility. The global statistical model of cutoff frequency was successfully developed in terms of capacitance fluctuation, considering intrinsic (channel and bulk charge) and extrinsic (overlap and fringe) capacitance components separately and identifying the major variability sources for cutoff frequency by using extracted parameter.

Fig: Calculated σf_T is plotted against σf_T obtained from measured data.

IEEE ICECS 2019 paper submission deadline

ICECS 2019 paper deadline submission is approaching fast: July 15th, 2019

Please distribute this reminder to possible contributors and interested researchers and colleagues. Topics of interest include but are not limited to:

• Analog/mixed-signal/RF circuits
• Biomedical and Bio-Inspired Circuits and Systems
• EDA, Test and Reliability
• Digital circuits and systems
• Linear and Non-linear Circuits
• Low-Power Low-Voltage Design
• Microsystems
• Neural networks, Machine and Deep Learning
• Sensors and Sensing Systems
• Signal Processing, Image and Video
• VLSI Systems and Applications

The technical committee invites authors to submit 4-page papers in standard IEEE double-column format, including references, figures and tables, to clearly present the work, methods, originality, significance and applications of the techniques discussed.

Maurizio Valle; IEEE ICECS 2019 General Chair
https://www.ieee-icecs2019.org/