There were two DevRooms to discuss the status and further FOSS CAD/EDA IC design tools developments and open PDK initiative:
- Libre-SOC, FPGA and VLSI DevRoom
- Open Hardware and CAD/CAM DevRoom
Roadmap: OpenVAF is still in development and there many goals we aim to achieve in the longterm:
Circuit simulators play a critical role in the design of electrical circuits. Accurate simulations enable circuit designers to validate circuit behavior before actual fabrication happens, potentially saving significant re-design costs. The simulation of a circuit critically depends on the so-called compact models and therefore:
Verilog-A has been developed to address these problems and has become the de-facto standard for developing and distributing compact models. It allows implementing compact models via a simulator independent and standardized language. Verilog-A compilers can translate these models to machine code and allow simulators to use these models without manually implementing them. Verilog-A enables:
parameter real NAv = 6.023E26; //Avogadros constant(1/MOLE)// ISFET geometrical parametersparameter real DIHP =0.1E-9;parameter real DOHP =0.3E-9;//ISFET electrochemical parametersparameter real KA = 15.8;parameter real KB = 63.1E-9;parameter real KN = 1E-10;parameter real Nsil = 3.0E+18;parameter real Nnit = 2.0E+18;parameter real Cbulk = 0.1;parameter real epso = 8.85E-12;parameter real epsihp = 32; //relative permittivity of the Inner Helmholtz layerparameter real epsohp = 32; //relative permittivity of the Outer Helmholtz layerparameter real epsw = 78.5; //relative permittivity of the bulk electrolyte solution//Reference-electrode electrochemical parametersparameter real Eabs = 4.7; //absolute potential of the standard hydrogen electrodeparameter real Erel = 0.2;parameter real Phim = 4.7; //work function of the metal back contactparameter real Philj = 1E-3; //liquid-junction potential difference between the refsolution and the electrolyteparameter real Chieo = 3E-3; //surface dipole potential
endT= $temperature;ET= (`P_Q /(`P_K * T));sq = sqrt(8*`P_EPS0*epsw*`P_K * T);CB = (NAv*Cbulk);CH = ((`P_EPS0*epsihp*epsohp) / (epsohp*DIHP + epsihp*DOHP));CD = (sq*ET*0.5)*sqrt(CB);CEQ = 1/(1/CD + 1/CH);V(ref,node) <+ Eabs - Phim - Erel + Chieo + Philj;Eref = V(ref,node);V(x)<+ log(KA*KB)+4.6*V(ph);V(y)<+ log(KA)+2.3*V(ph);V(gm,node) <+ (`P_Q / CEQ) * (Nsil * ((limexp(-2 * V(gm,node) * ET)– limexp(V(x))) / (limexp(-2 * V(gm,node) * ET) + limexp(V(y)) * limexp(-1 * V(gm,node)*ET) + limexp(V(x)))) + Nnit*((limexp(-1 * V(gm,node)*ET))/(limexp(-1* V(gm,node)*ET)+ (KN/KA) * limexp(V(y)))));
capacitor #(.c(CEQ)) Cq(node,gm);resistor #(.r(1G)) RP1(x,gnd);resistor #(.r(1G)) RP2(y,gnd);resistor #(.r(1k)) RPH(ph,gnd);