[paper] FOSS support for CM with Verilog-A

Bűrmen, Árpád, Tadej Tuma, Iztok Fajfar, Janez Puhan, Žiga Rojec, Matevž Kunaver

and Sašo Tomažič

Free software support for compact modelling with Verilog-A

Informacije MIDEM 54, no. 4 (October 9, 2024)

<https://ojs.midem-drustvo.si/index.php/InfMIDEM/article/view/1999>

Abstract: Verilog-A is the analog subset of Verilog-AMS - a hardware description language for analog and mixed-signal systems. Verilog-A is commonly used for the distribution of compact models of semiconductor devices. For such models to be usable a Verilog-A compiler is required. The compiler converts the model equations into a form that can be used by the simulator. Such compilers have been supplied with commercial simulators for many years now. Free software alternatives are much more scarce and limited in the features they offer. The paper gives an overview of Verilog-A, Free software Verilog-A compilers, and Free software/Open source simulators that can simulate compact models defined in Verilog-A. Advantages and disadvantages of individual compilers and simulators are highlighted.

Tab: Comparison of Free software simulators

Asterisk denotes a feature under development as of Sep. 2024

Acknowledgements: This research was funded in part by the Slovenian Research Agency within the research program ICT4QoL—Information and Communications Technologies for Quality of Life, grant number P2-0246.

[FOSSDEM 2024] Open PDK Initiative

FOSDEM 2024 was a two-day event organized by volunteers to promote the widespread use of free and open source software. Took place at the ULB Solbosch campus in the beautiful city of Brussels (Belgium), FOSDEM is widely recognized as the best FOSS conference in Europe.

There were two DevRooms to discuss the status and further FOSS CAD/EDA IC design tools developments and open PDK initiative:

• Libre-SOC, FPGA and VLSI DevRoom
• Verilog-AMS in Gnucap
• FOSS CAD/EDA tools supporting the open access PDK initiative
• Open Hardware and CAD/CAM DevRoom
• ngspice circuit simulator - stand-alone and embedded into KiCad

FOSDEM'24 Inauguration Session

[paper] STT-MTJ Device Model

Haoyan Liu and Takashi Ohsawa
General-Purpose STT-MTJ Device Model Based on the Fokker-Planck Equation
IEEE Transactions On Nanotechnology, VOL. 22, 2023 659 A
DOI: 10.1109/TNANO.2023.3322468.

Graduate School of Information, Production and Systems, Waseda University (J)

Abstract: A thermally agitated device model of spin-transfer torque magnetic tunnel junction (STT-MTJ) based on the Fokker-Planck equation is proposed which is implemented into HSPICE by using Verilog-A. We compared different techniques of finite difference method (FDM) and analyzed the impact of the solvers on computational efficiency and accuracy. A framework is proposed which traces dynamics of a particular STT-MTJ’s angle between the magnetic moments of the free and the pinned layers and makes the model applicable to a wide range of circuits. The model was applied to the 4T2MTJ memory cell array and a leaky integrate and-fire (LIF) neuron circuit to validate the stochastic switching characteristic and the angle prediction function. In the memory array simulations, the CPU time consumption for this model is 1/30 of the model which is based on the stochastic Landau-Lifshitz Gilbert-Slonczewski equation.

Fig: (a) Structure of 1T1MTJ synapse. (b) Binary weights in 10 neurons and an input digit ‘9’ of spiking neural network (surrounded by the dotted square) used for the experiment shown. Each digit is a 28×28 matrix. Each figure shows two output spikes fired in the neurons representing ‘0-9’. The total spike numbers of the neurons which represent 0-9 are 2, 3, 4, 3, 4, 4, 4, 4, 4 and 9. 

Acknowledgement: This work was supported in part by Synopsys Corporation, in part by JSPS KAKENHI under Grant JP20K04626, in part by VLSI Design and Education Center (VDEC), University of Tokyo with collaboration with Cadence Corporation, and in part by the cooperation of organization between Kioxia Corporation and Waseda University.

[paper] Lorentzian noise spectra in compact models

Nikolaos Makris*†, Loukas Chevas* and Matthias Bucher*

Verilog-A based implementation of Lorentzian noise spectra in compact models

26th International Conference on Noise and Fluctuations - ICNF

17th-20th October 2023 - Grenoble - France

DOI: 10.1109/ICNF57520.2023.10472771

* School of Electrical & Computer Engineering, Technical University of Crete (TUC), GR-73100 Chania, Greece        European University on Responsible Consumption and Production (EURECA-PRO) (Joint affiliation)
† Institute of Electronic Structure and Laser, Foundation for Research and Technology-Hellas (IESL-FORTH), GR-71110 Heraklion, Greece

Abstract:In this paper, a simple Verilog-A implementation of Lorentzian noise spectra is introduced that can be used in compact models for the frequency-domain simulation of low-frequency noise in electronic devices. For this purpose, a thermal noise source is combined with a low-pass filter as realized using laplace_nd Verilog-A function in order to achieve Lorentzian noise behavior. This modeling approach can be implemented in any Verilog-A compact model and provides the means for bias-dependent Lorentzian trap modeling. This approach is evaluated in commercial simulator. Application examples are provided to demonstrate the capabilities of this approach.

FIG: Bias dependent model implemented in the EKV3 MOSFET model

Acknowledgements: This work was co-funded by the ERASMUS+ Programme of the European Union (Contract number: 101004049 - EURECA-PRO - EAC-A02-2019 / EAC-A02-2019-1). This research has been co-financed by the European Regional Development Fund of the European Union and Greek national funds through the Operational Program Competitiveness, Entrepreneurship and Innovation, under the call RESEARCH - CREATE - INNOVATE (project code: T2EDK-00340).

[11k online viewers] 7th Sino MOS-AK/Nanjing

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

7th Sino MOS-AK Workshop in Nanjing (CN)

August 11-13, 2023 (online/onsite)

Recent, consecutive, 7th Sino MOS-AK/Nanjing Workshop discussing the Compact/SPICE modeling and its Verilog-A Standardization reached 11k online viewers. The MOS-AK participants and online attendees have followed one day SiC-related device modeling training on August 11 featured presentations by experts currently working at Robert Bosch GmbH and then two days workshop with 24 R&D Compact/SPICE modeling presentations:

[paper] 5-DC-parameter MOSFET model

Deni Germano Alves Neto1, Cristina Missel Adornes1, Gabriel Maranhao1, Mohamed Khalil Bouchoucha2,3, Manuel J. Barragan3, Andreia Cathelin2, Marcio Cherem Schneider1, Sylvain Bourdel3 and Carlos Galup-Montoro1

A 5-DC-parameter MOSFET model for circuit simulation in QucsStudio and SPECTRE

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS) 

DOI: 10.1109/NEWCAS57931.2023.10198173

1 Federal University of Santa Catarina, Florianopolis (BR)
2 STMicroelectronics, Crolles (F)
3 Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Grenoble (F)

Abstract: A minimalist MOSFET model for circuit simulation with only five DC parameters written in Verilog-A is presented. The five parameters can be extracted from direct and simple methods in common circuit simulators. The DC characteristics of transistors in both 180-nm bulk CMOS and 28-nm FD-SOI technologies generated by the five-parameter model are compared with those generated by the BSIM and UTSOI2 models, respectively. The simulation of some basic circuits using the proposed 5-DC-parameter MOSFET model shows good matching with the simulation using the BSIM model, at the benefit of a much simpler set of DC parameters.

Fig: DC characteristic gm/ID vs. id used to extract ζ.

REF:

[1] Advanced Compact MOSFET (ACM) in C. M. Adornes, D. G. Alves Neto, M. C. Schneider, and C. Galup-Montoro, “Bridging the gap between design and simulation of low voltage CMOS circuits,” Journal of Low Power Electronics and Applications, vol. 12, no. 2, 2022.

[analog-wg] Video of March 21 AWG Meeting

The Analog Workgroup (AWG) was formed by the CHIPS Alliance TSC to explore collaborations in open source Analog/Mixed-Signal design and verification. It focuses on sharing best practices, ideas, tooling (analog automation), and other challenge areas in the design space. The workgroup is composed of both industry and university members.

The AWG Video Meeting on March 21, 2023 included two presentations:

• Ken Kundert "Why Fund OpenVAF"
• Pascal Kuthe "OpenVAF: An innovative open-source Verilog-A Compiler"

Please note the following line of topics for the Analog Workgroup

• 4th April: Update from Tim Edwards: Magic and PEX extraction
• 18th April: Update from Sadayuki Yoshitomi: Ecosystem of compact model development 
• 2nd May (tentative): Update from C. Enz,EPFL:  test structures measurements

FOSS Verilog-A Models Repository

Dietmar Warning, ngspice team, has announced his new github project VA-Models repository 
<https://github.com/dwarning/VA-Models>

These Verilog-A model code repository is a compilation of the most important models in the state of public FOSS availability. The intention is to have one place for model access and a platform for discussion and integration into simulators.

At the moment, the models will be compiled by script with openVAF and checked with ngspice version 39. Code changes are introduced only for convergence support or to fulfill Verilog-A language standard requirements. Model equations are untouched. But I am open to integrate code modifications for other compiler/simulator companions as far they are inline with actual LRM 2.4. Simple test case are provided, mainly to show general functionality of the compiled models. 

Don't hesitate to contact Dietmar Warning, ngspice team, if there is something wrong, especially in kind of legal aspects. All the contributions are welcome.

[paper] Zener diode compact modeling and simulation

Mike Brinson

Modelling and simulation of Zener diode noise in the time domain

International Journal of Numerical Modelling Electronic Networks Devices and Fields

January 2023

DOI: 10.1002/jnm.3090

1 Centre for Communications Technology, London Metropolitan University, London, UK.

Abstract: This paper presents a new time domain Zener diode compact model for transient noise simulation. SPICE2 and SPICE3 use piece-wise linear time dependent sources for generating complex waveforms. This approach is not practical when applied to randomly generated noise. Today, through on-going improvements to freely available Circuit simulation tools, SPICE noise generation has moved to a new level. Ngspice, for example, computes white Gaussian noise ‘on-the-fly' as transient Simulation progresses. The proposed model has a simple behavioral structure that supports time domain shot, flicker, and thermal noise. The physical properties of the proposed model are introduced in the second section. This is followed by an evaluation of model performance in the third and fourth sections, including static DC, dynamic Charge, and transient noise characterization. Finally, the fifth section summarizes the conclusions of the research.

FIG: QuCS-S/Ngspice Zener diode behavioural model: subcircuit schematic drawing; intermediate equations and limexp function definition.

DATA AVAILABILITY STATEMENT: Data Sharing not applicable to this article as no datasets were generated or analyzed during the current study.

[OpenVAF] Next-Generation Verilog-A Compiler

OpenVAF is a Next-Generation Verilog-A compiler

that empowers the open source silicon revolution

Roadmap: OpenVAF is still in development and there many goals we aim to achieve in the longterm:

• Noise analysis (planned for 2023)
• Reaching full compliance with the Verilog-A standard
• Behavioral modelling features
• Support for features that allow defining full circuits/full PDKs in Verilog-A
• OSDI integration in Xyce
• Improved documentation
• A detailed paper about the technical innovations in OpenVAF and attendance at international conferences

We, OpenVAF Developers, are always looking for cooperation partners, please do not hesitate to contact SemiMod GmbH.

Circuit simulators play a critical role in the design of electrical circuits. Accurate simulations enable circuit designers to validate circuit behavior before actual fabrication happens, potentially saving significant re-design costs. The simulation of a circuit critically depends on the so-called compact models and therefore:

• The accuracy of the compact-model equations
• The quality of the model parameters

Compact models predict the device terminal characteristics by means of computationally inexpensive equations. With increasingly advanced technologies, compact models have been growing significantly in complexity. At the same time an increasingly diverse set of technologies is offered to designers, requiring specific compact models for each kind of electron device.
The complexity of compact models has made the manual integration into simulators a tedious, error-prone and therefore expensive task. One reason for this is that not only the model equations have to be implemented, but also their symbolic derivatives. Numeric derivatives are not an option because they are orders of magnitude slower to compute than analytical derivatives and can introduce convergence problems due to inaccuracies. It is not uncommon - even in commercial tools - to find model implementation bugs or to observe convergence problems that result from incorrectly implemented derivatives. Some simulators with no or limited Verilog-A integration do not implement certain compact-models and can therefore not be used to simulate some processes at all.
Manually implemented compact models may differ between simulators since EDA vendors often rename parameters or alter particular model equations. Due to these simulator specific peculiarities, PDKs can usually only be used by a few specific simulators.

Verilog-A has been developed to address these problems and has become the de-facto standard for developing and distributing compact models. It allows implementing compact models via a simulator independent and standardized language. Verilog-A compilers can translate these models to machine code and allow simulators to use these models without manually implementing them. Verilog-A enables:

• model development and customization by allowing to quickly modify the model equations without having to worry about model implementation details.
• implementing behavioral or data-driven models, or even entire circuits.
• inherent portability between simulators for both models and PDKs that would not be possible with traditional netlist-based formats.

Model development and customization is necessary for advanced technologies and applications, for example quantum computing, where existing models cannot provide satisfactory results and must be adjusted. It also enables research and development.

[read more at <https://openvaf.semimod.de/>]

[mos-ak] [2nd Announcement and C4P] 4th International MOS-AK/LAEDC Workshop July 3 Puebla (MX)

2nd Announcement and C4P

Together with local online host, the LAEDC Organizers as well as all the Extended MOS-AK TPC Committee, would like to invite you to the 4th International MOS-AK/LAEDC Workshop which will be organized as the virtual/online event on July 3  between 8:30am -  12:30pm (UTC/GMT -5 hours) as a hybrid event in Puebla (MX) providing an opportunity to meet with modeling engineers and researchers from Europe and Latin America.

Upcoming MOS-AK/LAEDC Workshop aims to strengthen a network and discussion forum among experts in the field, enhance an open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors, in particular using Free 130nm Skywater PDK.

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/aging IC designs
• Foundry/Fabless Interface Strategies (eg: Skywater 130nm CMOS)

List of MOS-AK speakers (tentative in alphabetical order) :

• Sergio Bampi, UFRGS (BR)
• Juan Brito, IMPINJ (BR)
• Antonio Cerdeira, CINVESTAV (MX)
• Benjamin Iniguez, URV (SP)
• Roberto Murphy, INAOE (MX)
• Jean-Michel Sallese, EPFL (CH)
• Gilson I Wirth, UFRGS (BR)

Online Abstract Submission is open (any related enquiries can be sent to abstracts@mos-ak.org)

Online Event Registration is open (any related enquiries can be sent to registration@mos-ak.org)

Important Dates: 

• Call for Papers: Dec. 2021
• 2nd Announcement: May 2022
• Final Workshop Program: June 2022
• MOS-AK: July 3 2022, Puebla (MX)
• 8:30am - 12:30pm (UTC/GMT -5 hours) MOS-AK Workshop

W.Grabinski for Extended MOS-AK Committee

WG170522

[paper] DL Physics-Driven MOSFET Modeling

Ming-Yen Kao, H. Kam, and Chenming Hu, Life Fellow, IEEE

Deep-Learning-Assisted Physics-Driven MOSFET Current-Voltage Modeling

in IEEE Electron Device Letters

DOI: 10.1109/LED.2022.3168243

Abstract: In this work, we propose using deep learning to improve the accuracy of the partially-physics-based conventional MOSFET current-voltage model. The benefits of having some physics-driven features in the model are discussed. Using a portion of the Berkeley Short-channel IGFET Common-Multi-Gate (BSIM-CMG), the industry-standard FinFET and GAAFET compact model, as the physics model and a 3-layer neural network with 6 neurons per layer, the resultant model can well predict IV, output conductance, and transconductance of a TCAD-simulated gate-all-around transistor (GAAFET) with outstanding 3-sigma errors of 1.3%, 4.1%, and 2.9%, respectively. Implications for circuit simulation are also discussed.

Fig: (a) Model implementation for circuit simulations, without the relative gm and gds errors terms in the cost function, Model shows larger prediction error in (b) gm and (c) gds.

Acknowledgements: This work was supported by the Berkeley Device Modeling Center, 

UCB, CA (USA)

[paper] Compact Model of JLNGAA MOSFET in Verilog-A

Billel Smaani^1,2, Shiromani Balmukund Rahi³ and Samir Labiod⁴

Analytical Compact Model of Nanowire Junctionless Gate-All-Around MOSFET

Implemented in Verilog-A for Circuit Simulation. 

Silicon (2022)

DOI: 10.1007/s12633-022-01847-9

   

1 Centre Universitaire Abdelhafid Boussouf, Mila, Algeria

2 Electronique Department, Constantine I University, Algeria

3 Department of Electrical Engineering, IIT Kanpur, India

4 Department of Physics, Skikda University, Algeria

Abstract: In the present research article, we have proposed an analytical compact model for Nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor’s operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (ΦS), obtained from approximated solutions of Poisson’s equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (Nd) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator.

Fig: Transient simulation of the implemented Colpitts oscillator using SMASH, where Vout is the output voltage. R = 4 nm, tox = 2 nm, L = 1 μm and Nd = 1E19/cm^3

Acknowledgments: Dr. S. B. Rahi (Indian Institute of Technology, Kanpur, India) for their useful suggestions

Guardian of Verilog-A Compact Models

on 02/02/2020, Geoffrey Coram, Staff CAD Engineer at Analog Devices and Verilog-A Recommended Practices CMC Chair was honored by Prof. Chenming Hu and the BSIM Group at UC Berkeley, naming him as "Guardian of Verilog-A Compact Models for the Global Semiconductor Industry"

[paper] Verilog-A Compact MTJ Model

Etienne Becle, Philippe Talatchian, Guillaume Prenat, Lorena Anghel, Ioan-Lucian Prejbeanu 

Fast Behavioral VerilogA Compact Model for Stochastic MTJ  

51st European Solid-State Device Research Conference; Grenoble 2021

  

CEA-Spintec (F)

Abstract: Spin-Transfer Torque Magnetic Tunnel Junctions (STT-MTJ) are devices featuring stochastic properties. They are promising candidates for non-volatile memory or true random number generators. To design reliable hybrid CMOS circuits including STT-MTJs, one needs to use a compact model accounting for its stochasticity in the circuit simulations. This paper proposes a compact model that accurately mimics the MTJ stochastic switching behavior and meets the needs of fast execution time. The relevance of such a model together with its fast execution velocity are illustrated with a bitstream generator. 

Fig: Schematic representation of the implemented algorithm

Acknowledgement: This work is supported by the French National Research Agency in the framework of the "Investissements d’avenir” program (ANR-15-IDEX-02). 

[paper] Compact Modeling of pH-Sensitive FETs Based on 2D Semiconductors

Tarek El Grour, Francisco Pasadas, Alberto Medina-Rull, Montassar Najari, Enrique G. Marin, Alejandro Toral-Lopez, Francisco G. Ruiz, Andrés Godoy, David Jiménez and Lassaad El-Mir

Compact Modeling of pH-Sensitive FETs Based on Two-Dimensional Semiconductors

arXiv:2109.06585 [physics.app-ph; submitted on 14 Sep 2021]

DOI: 10.1109/TED.2021.3112407

   

LAPHYMNE Laboratory, Gabes University, Gabes, Tunisia

PEARL Laboratory, Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, Spain

The Innovation and Entrepreneurship Centre, Jazan University, Jazan, Saudi Arabia.

Departament d’Enginyeria Electrònica, Escola d’Enginyeria, Universitat Autònoma de Barcelona, Spain

Abstract: We present a physics-based circuit-compatible model for pH-sensitive field-effect transistors based on two-dimensional (2D) materials. The electrostatics along the electrolyte-gated 2D-semiconductor stack is treated by solving the Poisson equation including the Site-Binding model and the Gouy-Chapman-Stern approach, while the carrier transport is described by the drift-diffusion theory. The proposed model is provided in an analytical form and then implemented in Verilog-A, making it compatible with standard technology computer-aided design tools employed for circuit simulation. The model is benchmarked against two experimental transition-metal-dichalcogenide (MoS2 and ReS2) based ion sensors, showing excellent agreement when predicting the drain current, threshold voltage shift, and current/voltage sensitivity measurements for different pH concentrations.

Fig: a) Schematic depiction of a 2D-ISFET b) its quivalent capacitive circuit

Acknowledgments: This work is supported in part by the Spanish Government under the projects TEC2017-89955-P, RTI2018-097876-B-C21 and PID2020-116518GB-I00 (MCIU/AEI/FEDER, UE); the FEDER/Junta de Andalucía under project BRNM-375-UGR18; EC under Horizon 2020 projects WASP No. 825213 and GrapheneCore3 No. 881603. E.G. Marin gratefully acknowledges Juan de la Cierva Incorporación IJCI-2017-32297. A. Toral-Lopez acknowledges the FPU program (FPU16/04043). F. Pasadas acknowledges funding from PAIDI 2020 and Andalusian ESF OP 2014-2020 (20804). F. Pasadas and D. Jiménez also acknowledge the partial funding from the ERDF allocated to the Programa Operatiu FEDER de Catalunya 2014-2020, with the support of the Secretaria d’Universitats i Recerca of the Departament d’Empresa i Coneixement of the Generalitat de Catalunya for emerging technology clusters to carry out valorization and transfer of research results. Reference of the GraphCAT project: 001-P-001702.

[paper] JART VCM v1 Verilog-A Compact

JART VCM v1 Verilog-A Compact

Model User Guide

Christopher Bengel, David Kaihua Zhang, Rainer Waser, Stephan Menzel

Electronic Materials Research Laboratory; RWTH Aachen University
Forschungszentrum Jülich

Abstract: The JART VCM v1a model was developed to simulate the switching characteristics of ReRAM devices based on the valence change mechanism. In this model, the ionic defect concentration (oxygen vacancies) in the disc region close to the active electrode (AE) defines the resistance state. The concentration changes due to the drift of the ionic defects. Furthermore, these oxygen vacancies act as mobile donors and modulate the Schottky barrier at the AE/oxide interface. In this model, Joule heating is considered, which significantly accelerates the switching process at high current levels. Since the JART VCM v1b model represents an improvement of the JART VCM v1a model, this user guide will have its focus on the JART VCM v1b model. Here, the equivalent circuit diagram (ECD) as well as some equations have been modified to explain the switching dynamics more accurately  Based on the JART VCM v1b model, a variability model was developed, which includes both device-to-device and cycle-to-cycle variability. In terms of the device-to-device variability, the VCM cells are initiated with statistical distributed parameters: filament lengths, filament radii and maximum and minimum values for the oxygen vacancy concentration in the disc. The cycle-to-cycle variability is achieved by changing the four quantities during SET and RESET. The latest extension of the JART VCM v1b also includes RTN, which is based on statistical jumps of oxygen vacancies into and out of the disc region.

Fig: Equivalent circuit diagram of the JART VCM v1b model (a) 

along with the electrical model in Verilog-A (b).

The Verilog-A code of this model can be downloaded here (Verilog-A file).
The User Guide for this model version can be downloaded here (User Guide PDF).

[paper] FET Library for VLSI

Taehak Kim¹, Jaehoon Jeong², Seungmin Woo², Jeonggyu Yang¹, Hyunwoo Kim² Ahyeon Nam², Changdong Lee², Jinmin Seo², Minji Kim², Siwon Ryu², Yoonju Oh², and Taigon Song¹,²  

NS3K : A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes 

IEEE ISCAS, 2021, pp. 1-5, DOI 10.1109/ISCAS51556.2021.9401055.

¹School of Electronics Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea
²School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea

Abstract: Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology. 

Fig: Projected 3nm NSFET library development flow. Upper side of each step shows the names of required tools. Each colored-boxes correspond to the steps required for specific tasks: The blue boxes - device development, the orange boxes - digital design, and the green boxes - back end design, respectively.

Acknowledgements: This research was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (2020M3H2A1078045). The EDA tool was supported by the IC Design Education Center(IDEC), Korea. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No.2019R1G1A109470212).

[paper] Dynamic Simulation of a-IGZO TFT Circuits Using AFCM

Y. Hernández-Barrios¹, J. N. Gaspar-Angeles¹, M. Estrada¹, B. Íñiguez², And A. Cerdeira¹

Dynamic Simulation of a-IGZO TFT Circuits Using the Analytical Full Capacitance Model (AFCM)

IEEE Journal of the Electron Devices Society, vol. 9, pp. 464-468, 2021, 

doi: 10.1109/JEDS.2020.3045347

1 SEES, Departamento de Ingeniería Eléctrica, CINVESTAV-IPN, Mexico City 07360, Mexico
2 Departament d’Enginyeria Electrònica, Elèctrica i Automàtica, URV, Tarragona 43007, Spain

Abstract: The Analytical Full Capacitance Model (AFCM) for amorphous oxide semiconductors thin film transistors (AOSTFTs) is first validated, using a 19-stages Ring Oscillator (RO) fabricated and measured. The model was described in Verilog-A language to use it in a circuit simulator in this case SmartSpice from Silvaco. The model includes the extrinsic effects related to specific overlap capacitances present in bottom-gate AOSTFT structures. The dynamic behavior of the simulated circuit, when the TFT internal capacitances are increased or decreased and for different supply voltages of 10, 15 and 20 V, is compared with measured characteristics, obtaining a very good agreement. Afterwards, the AFCM is used to simulate the dynamic behavior of a pixel control circuit for a light emitting diode active matrix display (AMOLED), using an AOSTFT.

FIG: Fabricated and measured 19-stages Ring Oscillator (RO)

of amorphous oxide semiconductors (AOS) thin film transistors (TFTs) 

Aknowlwgement: This work was supported in part by the Consejo Nacional de Ciencia y Tecnología (CONACYT) under Project 237213 and Project 236887; in part by the H2020 program of the European Union under Contract 645760 (DOMINO); in part by contract “Thin Oxide TFT SPICE Model” with Silvaco Inc., under Grant T12129S; and in part by ICREA Academia 2013 from ICREA Institute and the Spanish Ministry of Economy and Competitiveness under Project TEC2015-67883-R GREENSENSE.

 

[Photos] MOS-AK LADEC Mexico April 18, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK LAEDC Workshop

(virtual/online) April 18, 2021

Together with local Host and LAEDC Organizers as well as all the Extended MOS-AK TPC Committee, we have organized the 3rd subsequent MOS-AK/LAEDC workshop which was the Virtual/Online event. There are a couple of the event photos:

MOS-AK Session 1 (APR.18) begun: 8:00am Mexico time zone (GMT-5)

T_1 FOSSEE eSIM: An open source CAD software for circuit simulation

Kannan Moudgalya

IIT Bombay (IN)

T_2 Memristor modeling

Arturo Sarmiento

INAOE (MX)

T_3 Modeling Issues for CMOS RF ICs

Roberto Murphy, Jose Valdes and Reydezel Torres

INAOE (MX)

T_4 Improving Time-Dependent Gate Breakdown of GaN HEMTs with p-type Gate

E. Sangiorgi, A. Tallarico, N. Posthuma, S. Decoutere, C. Fiegna

Universita di Bologna

MOS-AK Session 2 (APR.18) begun: 1:00pm Mexico time zone (GMT-5)

T_5 Compact Models of SiC and GaN Power Devices

Alan Mantooth, Arman Ur Rashid, Md Maksudul Hossain

University of Arkansas (US)

T_6 New analytical model for AOSTFTs

Antonio Cerdeira

CINVESTAV-IPN, Mexico City (MX)

T_7 On the Parameter Extraction of Thin-Film Transistors in Weak-Conduction

Adelmo Ortiz-Conde

Solid State Electronics Laboratory, Simon Bolivar University, Caracas (VE)

End of MOS-AK Workshop
Group Photo