[paper] Anti-ferroelectric/Ferroelectric Stack NC FinFET

Shih-En Huang¹, Student Member, IEEE, Pin Su¹, Member, IEEE, 

and Chenming Hu^1,2, Life Fellow, IEEE

S-curve Engineering for ON-state Performance 

using Anti-ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

2021 - techrxiv.org

1 Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University,  Hsinchu 30010, Taiwan  

2 Department of Electrical Engineering and Computer Science, University of California at Berkeley

Abstract: This work investigates the S-curve engineering by exploiting the anti-ferroelectric (AFE)/ferroelectric (FE) stack negative-capacitance FinFET (NC-FinFET) to improve both the subthreshold swing and ON-state current (ION). The capacitance matching and ON-state performance are evaluated by using a short-channel AFE/FE stack NC-FinFET model. Our study indicates that the AFE/FE gate-stack can theoretically achieve surprising improvements to the OFF-state current (IOFF) and ION relative to IRDS projections. There is significant long-term advantage to IC power consumption and speed if materials with certain AFE and FE characteristics can be developed and introduced into IC manufacturing.

Fig: (a) Equivalent capacitance network of the AFE/FE stack NC-FinFET. The Cafe, Cfe and Cint are the anti-ferroelectric capacitance, ferroelectric capacitance and the internal capacitance, respectively. (b) Capacitance matching comparison at source end shows that the AFE/FE stack improves the high AV region toward high VGS. 

Acknowledgment: The authors would like to thank anonymous referees for critical reading of the manuscript and valuable feedback. This work was supported in part by “Center for the Semiconductor Technology Research” from The Featured Areas Research Center Program within the framework of the Higher Education Sprout Project by the Ministry of Education (MOE), Taiwan, and in part by the Ministry of Science and Technology, Taiwan, under contracts 110-2634-F-009-027 and 110-2218-E-A49-014-MBK.

[paper] Compact Modeling in MFIS Negative-Capacitance FETs

N. Pandey and Y. S. Chauhan

Analytical Modeling of Short-Channel Effects in MFIS Negative-Capacitance FET

Including Quantum Confinement Effects

in IEEE TED (Early Access), DOI: 10.1109/TED.2020.3022002.

Abstract: An analytical 2-D model of double-gate metal-ferroelectric-insulator-semiconductor-negative-capacitance FET (MFIS-NCFET), using Green's function approach, in the subthreshold region, is presented in this article. The explicit solution of coupled 2-D Landau-Devonshire and Poisson equations is analytically derived. Subsequently, an analytical and explicit model of subthreshold slope is developed from potential functions. The developed model includes quantum-mechanical effects, which considers not only geometrical confinements but also electrical confinements. The analytical solution of a 2-D nonhomogeneous Poisson equation coupled with the 1-D Schrödinger equation is used to obtain the potential function in the channel. The impact of the ferroelectric thickness (tfe) on quantum confinement is also studied. We find that larger tfe reduces the quantum confinement effect. Therefore, as tfe increases, threshold voltage roll-off with the variation in Si-body thickness decreases.

Fig: Schematic of DG MFIS-NCFET.

Aknowegement: This work was supported in part by the Swarna Jayanti Fellowship under Grant DST/SJF/ETA-02/2017-18 and in part by the FIST Scheme of the Department of Science and Tech- nology under Grant SR/FST/ETII-072/2016. 

[paper] Analysis and Compact Modeling of Negative Capacitance Transistor

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current
and Negative Output Differential Resistance
Part II: Model Validation

Girish Pahwa, Student Member, IEEE, Tapas Dutta, Member, IEEE, Amit Agarwal,
Sourabh Khandelwal, Member, IEEE, Sayeef Salahuddin, SM IEEE,
Chenming Hu, IEEE Fellow, and Yogesh Singh Chauhan, SM IEEE 

in IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 4986-4992, Dec. 2016

doi: 10.1109/TED.2016.2614436

Abstract: In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation.

[read more at IEEE Xplore]