[paper] artificial synapse

Md. Hasan Raza Ansari, Udaya Mohanan Kannan, and Nazek El-Atab

Silicon Nanowire Charge Trapping Memory for Energy-Efficient Neuromorphic Computing

IEEE Transactions on Nanotechnology (2023)

DOI 10.1109/TNANO.2023.3296673

SAMA Labs, CEMSE Division, KAUST, Thuwal 23955-6900, Saudi Arabia

Department of Electronic Engineering, Gachon University, Seongnam 13120, Korea

Abstract: This work highlights the utilization of the floating body effect and charge-trapping/de-trapping phenomenon of a Silicon-nanowire (Si-nanowire) charge-trapping memory for an artificial synapse of neuromorphic computing application. Charge trapping/de-trapping in the nitride layer characterizes the long-term potentiation (LTP)/depression (LTD). The accumulation of holes in the potential well achieves short-term potentiation (STP) and controls the transition from STP to LTP. Also, the transition from STP to LTP is analyzed through gate length scaling and high-κ material (Al2O3) for blocking oxide. Furthermore, the conductance values of the device are utilized for system-level simulation. System-level hardware parameters of a convolutional neural network (CNN) for inference applications are evaluated and compared to a static random-access memory (SRAM) device and charge-trapping memory. The results confirm that the Si-nanowire transistor with better gate controllability has a high retention time for LTP states, consumes low power, and archives better accuracy (91.27%). These results make the device suitable for low-power neuromorphic applications.

FIG: Schematic representation of biological and Si-nanowire charge trapping memory as an artificial synapse

[chapter] GAA Transistors

Srivastava, Shobhit, and Abhishek Acharya

Challenges and future scope of gate-all-around (GAA) transistors

in "Device Circuit Co-Design Issues in FETs"; 

Shubham Tayal et al. (Editors)

231 CRC Press, 22 Aug 2023 - Technology & Engineering

Introduction: No doubt, FinFET technology is the slogger of today's semiconductor world. But as demand for further scaling with a desire for ultra-low-power and high-speed applications results in undesired short-channel effects, a new transistor is required. This is where gate-all-around (GAA) devices come into being. The GAA structure helps to mitigate unwanted short-channel effects by enhancing channel controllability. In GAAFETS, the channel surrounds all of its sides through a high-K and interfacial oxide layer. Thanks to science and technological innovation, the GAAFET family brings together different transistors and their competitive benefits. This chapter tries to answer why and how 3D devices emerge. In addition to the limitation of FinFET (a 3D device, gate surrounded by three sides), it further talks about the scope and challenges of different competitive GAAFET members (nanowire FET, nanosheet FET, junctionless nanosheet FET, complementary PET, and forksheet FET) of the GAAFET family. It is worth mentioning that a smaller benefit of the device performance exerts a massive performance enhancement on circuit-level applications. However, the advantages of device enhancement concurrently exaggerate the limitation of devices at circuit-level applications. So, an elaborated idea of GAAFETs holding the benefits and challenges at the circuit is also discussed here.

FIG: Structural evolution of transistors from planar to 3D forksheet FET technology

[paper] Compact Model of JLNGAA MOSFET in Verilog-A

Billel Smaani^1,2, Shiromani Balmukund Rahi³ and Samir Labiod⁴

Analytical Compact Model of Nanowire Junctionless Gate-All-Around MOSFET

Implemented in Verilog-A for Circuit Simulation. 

Silicon (2022)

DOI: 10.1007/s12633-022-01847-9

   

1 Centre Universitaire Abdelhafid Boussouf, Mila, Algeria

2 Electronique Department, Constantine I University, Algeria

3 Department of Electrical Engineering, IIT Kanpur, India

4 Department of Physics, Skikda University, Algeria

Abstract: In the present research article, we have proposed an analytical compact model for Nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor’s operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (ΦS), obtained from approximated solutions of Poisson’s equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (Nd) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator.

Fig: Transient simulation of the implemented Colpitts oscillator using SMASH, where Vout is the output voltage. R = 4 nm, tox = 2 nm, L = 1 μm and Nd = 1E19/cm^3

Acknowledgments: Dr. S. B. Rahi (Indian Institute of Technology, Kanpur, India) for their useful suggestions

[paper] Compact Model for Electrostatics of III–V GAA Transistors

Mohit D. Ganeriwala, Francisco G. Ruiz*, Enrique G. Marin* and Nihar R. Mohapatra

A unified compact model for electrostatics of III–V GAA transistors with different geometries

Journal of Computational Electronics (2021)

Published: 07 August 2021

DOI: 10.1007/s10825-021-01751-2

 
Department of Electrical Engineering, Indian Institute of Technology Gandhinagar, Gandhinagar, Gujarat, 382355, India
*Department of Electronics, University of Granada, Granada, Spain

Abstract: In this work, a physics-based unified compact model for III-V GAA FET electrostatics is proposed. The model considers arbitrary cross-sectional geometry of GAA FETs viz. rectangular, circular and elliptical. A comprehensive model for cuboid GAA FETs is developed first using the constant charge density approximation. The model is then combined with the earlier developed model for cylindrical GAA FETs to have a unified representation. The efficacy of the model is validated by comparing it with simulation data from a 2D coupled Poisson-Schrödinger solver. The proposed model is found to be accurate for GAA FETs with different geometries, dimensions and channel materials and computationally efficient.

Fig: III–V GAA transistors with different geometries

Acknowledgements: This work is supported by the Visvesvaraya PhD scheme by MeitY, Gover nment of India Enrique G. Marin gratefully acknowledges Juan de la Cierva Incorporation IJCI-2017-32297 (MINECO/AEI).

[paper] Nanosheet field effect transistors

J. Ajayan^a, D. Nirmal^b, Shubham Tayal^a, Sandip Bhattacharya^a, L. Arivazhagan^c, A.S. Augustine Fletcher^b, P. Murugapandiyan^d, D. Ajitha^e

Nanosheet field effect transistors - A next generation device to keep Moore’s law alive:
An intensive study

Microelectronics Journal 114 (2021) 105141

DOI: 10.1016/j.mejo.2021.105141

a SR University, Warangal, Telangana, India
b Karunya Institute of Technology and Sciences, Coimbatore, Tamilnadu, India
c Sri Ramakrishna Engineering College, Coimbatore, Tamilnadu, India
d Anil Neerukonda Institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India
e Sreenidhi Institute of Science and Technology, Hyderabad, Telangana, India

Abstract: Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects (SCEs) and self-heating effects (SHEs) which limits their performance and causes reliability issues. FinFET technology has resulted in a remarkable performance up to a feature size of 7nm. The research community is expecting that GAA NW-FETs will take over FinFET technology from 7nm to 5nm. However, further shrinking of feature size to 3nm will impose severe challenges to the performance of these aforesaid multi-gate devices. Subsequently, the electron device designer community needs to look for alternative device designs like nanosheet FETs (NS-FETs) to overcome the limitations of the FinFET and GAA NW-FETs technologies. The driving force behind the emergence of these NS-FETs is their ability to scale down even below a feature size of 5nm with negligible short channel effects. Therefore, in this review article we have intensively investigated the NS-FETs in terms of impact of geometrical scaling, substrate material effects, parasitic channel effects, thermal effects, compatibility with different metal gates, and source/drain (S/D) metal depth effect. Consequently, it can be concluded that vertically stacked NS-FET is the most promising solution for future digital/analog integrated circuit applications due to their outstanding capability to keep Moore’s Law alive.

Fig: 3-D views of (a) FinFET (b) stacked NW-FET (c) vertically stacked NSFET.

[Review] Nanosheet Transistors Technology

Firas N. A. Hassan Agha¹, Yasir H. Naif², Mohammed N. Shakib³

Review of Nanosheet Transistors Technology

Tikrit Journal of Engineering Sciences (2021) 28 (1): 40-48

ISSN: 1813-162X (Print) ; 2312-7589 (Online)

DOI: http://doi.org/10.25 30/tjes.28.1.05

available online at: http://www.tj-es.com

1Electrical Department/ Engineering College; Mosul University; Mosul, Iraq
2Department of Computer Engineering; Faculty of Engineering, Tishk; International University; Erbil, Iraq
3Faculty of Electrical and Electronics; Engineering Technology, University; Malaysia Pahang; Pekan, Malaysia

Abstract: Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nano-dimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).

Fig: Development of Field Effect Transistor from FinFET to MBCFET [Credit: Samsung]

Acknowledgment: The authors would like to thank University of Mosul for their support.

[paper] Nanowire gate-all-around MOSFETs modeling

Cheng, He, Tiefeng Liu, Chao Zhang, Zhijia Yang, Zhifeng Liu, Kazuo Nakazato

and Zhipeng Zhang

Nanowire gate-all-around MOSFETs modeling:

ballistic transport incorporating the source-to-drain tunneling

Japanese Journal of Applied Physics (2020)

Accepted Manuscript online 5 June 2020

DOI: 10.35848/1347-4065/ab99db

Abstract: Incorporating the source-to-drain tunneling current valid in all operating regions, an analytical compact model is proposed for cylindrical ballistic GAA-nMOSFETs with ultra-short Silicon channel. From taking the DIBL effect into consideration, the potential distribution within the device channel has been modeled based upon a 2-D analysis in our previous work. In this study, by introducing a parabolic function when modeling the potential profile in the channel direction, we found out that the source-to-drain tunneling effect in the subthreshold region could be evaluated analytically by applying WKB approximation. Then, it is practical to estimate the drain current for all operating regions analytically with this compact model considering both the source-to-drain tunneling and thermionic transport. The resulting analytic compact model is tested against NEGF simulation using SILVACO, and good accuracy is demonstrated. Finally, we perform an NMOS inverter circuit simulation using HSPICE, introducing our model to it as a Verilog-A script.

Fig: Rough sketch of the potential energy profile along the channel and illustration of mechanisms governing the carrier transport in ballistic tunneling and thermionic modes.
(a) Representation of energy levels distribution along the z-direction at the channel center (r = 0).
(b) Schematics of confinement potential energy distribution along r-component at the barrier top (z = zMAX) in the cross section. The elementary charge stands for letter e. 

Acknowledgment: The authors would like to thank Prof. S. Uno for his support to this work. This work has been supported by the science and technology program of Liaoning, the major industrial projects (Grant No. 2019JH1/1010022