[paper] Self-Heating Effects in 55-nm SiGe HBTs

Abdelaaziz Boulgheb1, Billel Smaani2, Taha Housseyn Nouibat1

Physics-Based Electro-Thermal Modeling and Analysis 

of Self-Heating Effects in 55-nm SiGe HBTs

physica status solidi (a), 2026; 223:e70563 

https://doi.org/10.1002/pssa.70563

1. USTHB, Bab Ezzouar, Algeria 

2. University of Mila, Mila, Algeria

Abstract: This work investigates spatially resolved electrothermal behavior in scaled SiGe HBTs under self-heating conditions, emphasizing its impact on temperature distribution and RF performance. Unlike conventional lumped thermal resistance approaches assum- ing uniform temperature rise, the present analysis resolves the internal temperature field to capture nonuniform heat propagation effects. A physics-based electrothermal framework combining drift–diffusion transport, temperature-dependent semiconductor properties, and heat conduction equations is used to study hotspot formation and thermal confinement in a 55 nm SiGe HBT structure. Three operating conditions are considered: nominal operation at 300 K, self-heating at 300 K ambient temperature, and elevated ambient temperature of 320 K. The results reveal localized hotspot formation near the base–collector junction due to current crowding and geometrical confinement, leading to RF performance degradation. The cutoff frequency decreases from 320 to 285 GHz, while the maximum oscillation frequency reduces from 486 to 458.5 GHz. The current gain decreases from 2000 to 1500, and the maximum junction temperature reaches 417 K under the highest thermal stress condition. These findings highlight the importance of spatial thermal effects in governing RF limitations of SiGe HBTs and provide insight into the coupling between heat propagation and electrical performance in BiCMOS technologies.

FIG: Device structure of 55 nm SiGe HBT simulated with multiphysics TCAD: (a) log of electron and hole concentration highlighting emitter/base/SIC pedestal (b) TEM cross section of a fabricated BiCMOS 55nm HBT. Impact of self-heating on high-frequency performance of the 55-nm SiGe HBT under three thermal conditions: (c) parasitic delay parasitic (d) forward transit time τF , (e) cutoff frequency fT, and (f) maximum oscillation frequency fmax.

[paper] TCAD for Circuits and Systems

Z. Stanojevic, X. Klemenschits, G. Rzepa, F. Mitterbauer, C. Schleich,

F. Schanovsky, O. Baumgartner, and M. Karner

TCAD for Circuits and Systems: Process Emulation, Parasitics Extraction, Self-Heating

2024 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium

BCICTS, Fort Lauderdale, FL, USA, 2024, pp. 294-297

doi: 10.1109/BCICTS59662.2024.10745677

1 Global TCAD Solutions GmbH., Boesendorferstraße 1/12, 1010 Vienna, Austria

Abstract: We present TCAD-based methodologies that go beyond process and device simulations of single transistors. We show that TCAD solvers can be used as effective tools to resolve the intricacies of current and future technology nodes that are otherwise difficult to access using EDA-level methods alone.

Fig: Single NMOS/PMOS FinFET with the local contacts and their parasitic R/C-components; fitting results for NMOS and PMOS FinFET: gate capacitance, transfer characteristics, output characteristics

[paper] Electrical characterization of advanced MOSFETs

Valeriya Kilchytska, Sergej Makovejev, Babak Kazemi Esfeh, Lucas Nyssens, Arka Halder,

Jean-Pierre Raskin and Denis Flandre

Electrical characterization of advanced MOSFETs towards analog and RF applications

IEEE LAEDC, San Jose, Costa Rica, 2020, 

doi: 10.1109/LAEDC49063.2020.9073536

Abstract - This invited paper reviews main approaches in the electrical characterization of advanced MOSFETs towards their target analog and RF applications. Advantages and necessity of those techniques will be demonstrated on different study cases of various advanced MOSFETs, such as FDSOI, FinFET, NW in a wide temperature range, based on our original research over the last years. 

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9073536&isnumber=9072949

Acknowledgements - This work was partially funded by Eniac “Places2Be”, Ecsel “Waytogofast”, FNRS - FRFC “Towards Highly-efficient 10 nm MOSFETs”, FP7 “Nanosil” and “Nanofunction” projects. The authors thank our colleagues from CEA-Leti, ST and Imec, and particularly, F. Andrieu, O. Faynot, T. Poiroux, S. Barraud, M. Haond, N. Planes, N. Collaert, C. Claeys, M. Jurczak, B. Parvais, R. Rooyackers, for providing UTBB FD SOI, NW and FinFET devices and valuable discussions.

An interesting paper in the Intl. Jornal of Numercal Modelling (vol 22(6))

This is not exactly compact modelling, but it's a nice thing to see:

SPICE-aided modelling of dc characteristics of power bipolar transistors with self-heating taken into account

Janusz Zarbski, Krzysztof Górecki
Department of Marine Electronics, Gdynia Maritime University, Morska 83, 81-225 Gdynia, Poland

Abstract
This paper deals with the problem of calculations of the dc characteristics of power bipolar transistors (BJTs) with self-heating taken into account. The electrothermal model of the considered devices dedicated for PSPICE is presented. The correctness of the model was verified experimentally in all ranges of the BJT operation. Two transistors - BD285 and 2N3055 - were arbitrarily selected for investigation. A good agreement between the measured and calculated characteristics of these transistors was observed.

You can access the online version here.