Showing posts with label ReRAM. Show all posts
Showing posts with label ReRAM. Show all posts

Mar 19, 2024

[Habilitation] Assessment of novel devices in CMOS technology

Assessment of novel devices in CMOS technology
by electrical characterization and physics-based model
Habilitation Presented To Obtain The Authorization 
To Direct Research From Sorbonne University
Lionel Trojman, PhD
Sorbonne Université, 2020
Organization of the thesis
Chapter 1: This chapter extends research work after the author’s PhD study. It focuses on HfO2-based dielectric MOSFETs with sub-1nm EOT. The study explores the impact of transport factors like saturation velocity on planar MOSFETs and the mobility of FDSOI-UTBB MOSFETs. Notably, the back-biased effect is considered, and an inversion charge model is developed for different front and back biases.
Chapter 2: Emphasis the application of the statistical defect-centric model to assess the impact of channel hot carriers on the reliability of low-dimensional MOSFETs.
Chapter 3: This chapter shifts focus to GaN-on-Si wafer devices for power electronic applications. These devices integrate MOS-like structures into III-V material-based devices, specifically MOS-HEMT and GET-SBD.
Chapter 4: Investigates RERAM devices. It stems from cooperative research with UNICAL and a PhD program in collaboration with Aix-Marseille University

FIG: Description of the gate structure (half device) of the studied device including the parasitic capacitance inner fringing (CIF), outer fringe (COF) and Junction overlap capacitance (COV)


 

 

Jun 7, 2021

[paper] JART VCM v1 Verilog-A Compact

Model User Guide
Christopher Bengel, David Kaihua Zhang, Rainer Waser, Stephan Menzel

Electronic Materials Research Laboratory; RWTH Aachen University
Forschungszentrum Jülich

Abstract: The JART VCM v1a model was developed to simulate the switching characteristics of ReRAM devices based on the valence change mechanism. In this model, the ionic defect concentration (oxygen vacancies) in the disc region close to the active electrode (AE) defines the resistance state. The concentration changes due to the drift of the ionic defects. Furthermore, these oxygen vacancies act as mobile donors and modulate the Schottky barrier at the AE/oxide interface. In this model, Joule heating is considered, which significantly accelerates the switching process at high current levels. Since the JART VCM v1b model represents an improvement of the JART VCM v1a model, this user guide will have its focus on the JART VCM v1b model. Here, the equivalent circuit diagram (ECD) as well as some equations have been modified to explain the switching dynamics more accurately  Based on the JART VCM v1b model, a variability model was developed, which includes both device-to-device and cycle-to-cycle variability. In terms of the device-to-device variability, the VCM cells are initiated with statistical distributed parameters: filament lengths, filament radii and maximum and minimum values for the oxygen vacancy concentration in the disc. The cycle-to-cycle variability is achieved by changing the four quantities during SET and RESET. The latest extension of the JART VCM v1b also includes RTN, which is based on statistical jumps of oxygen vacancies into and out of the disc region.

Fig: Equivalent circuit diagram of the JART VCM v1b model (a) 
along with the electrical model in Verilog-A (b).

The Verilog-A code of this model can be downloaded here (Verilog-A file).
The User Guide for this model version can be downloaded here (User Guide PDF).








Mar 31, 2021

[webinar] "More Moore Roadmap" by IRDS and SINANO


IEEE EDS France, IRDS and the SINANO Institute will organize a Webinar 

"More Moore Roadmap"
by Mustafa Badaroglu 
IRDS-IFT More Moore Leader

The webinar will be held on 8th April 2021 at 16:00 Paris time. Interest participants please register via IEEE vTools by the following link: https://events.vtools.ieee.org/event/register/267103

Other Webinars of the IRDS Chapters will be announced in the EDS Newsletters