[paper] La:HfO2 gate stacked ferroelectric tunnel FET

Neha Paras^a, Shiromani Balmukund Rahi^b, Abhishek Kumar Upadhyay^c,
Manisha Bharti^d, Young Suh Song^e

Design and analysis of novel La:HfO2 gate stacked ferroelectric tunnel FET
for non-volatile memory applications

Memories - Materials, Devices, Circuits and Systems

Volume 7, April 2024, 100101

DOI: 10.1016/j.memori.2024.100101

a Jawaharlal Nehru University, New Delhi, India
b Indian Institute of Technology, Kanpur, India
c X-FAB Dresden GmbH & Co. KG, Dresden, Germany
d National Institute of Technology, Delhi, India
e Korea Military Academy, Seoul, Republic of Korea

Abstract : Recent experimental studies have shown lanthanum-doped hafnium oxide (La:HfO2) possessing ferroelectric properties. This material is of special interest since it is based on lead-free, simple binary oxide of HfO2, and has excellent endurance property (1 × 109 field cycles without fatigue. There exists substantial information about the material aspects of La:HfO2 but it lacks proven application potential for CMOS-compatible low-power memory design. In this work, 10 % La metal cation fraction of HfO2 (La:HfO2) is proposed as the gate stack material in tunnel FET (TFET) for its potential as a memory device. 2D device simulations are carried out to show that the proposed ferroelectric TFET (FeTFET) provides the largest memory window (MW) as compared to present perovskite ferroelectric materials such as PZT, SBT (SrBi2Ta2O9) and silicon doped (4.6 % Si in HfO2) hafnium oxide (Si:HfO2). The larger window is attributed to greater polarization, and the calculation of MW is quantified by the shift in threshold voltage (Vth). The simulations carried out in this work suggest that La:HfO2 can be adopted as a potential ferroelectric material to target low-power FeTFET design at significantly reduced ferroelectric layer thickness.

FIG: Polarization phenomena of the proposed 

La:HfO2 gate stacked ferroelectric tunnel FET

[book] Tunneling Field Effect Transistors

Tunneling Field Effect Transistors
Design, Modeling and Applications

Edited By T. S. Arun Samuel, Young Suh Song, Shubham Tayal, P. Vimala, Shiromani Balmukund Rahi

ISBN 9781032348766
1st Edition; 316 Pages; 15 Color & 232 B/W Illustrations
June 8, 2023 by CRC Press

Description: This book will give insight into emerging semiconductor devices from their applications in electronic circuits, which form the backbone of electronic equipment. It provides desired exposure to the ever-growing field of low-power electronic devices and their applications in nanoscale devices, memory design, and biosensing applications.

Tunneling Field Effect Transistors: Design, Modeling and Applications brings researchers and engineers from various disciplines of the VLSI domain to together tackle the emerging challenges in the field of nanoelectronics and applications of advanced low-power devices. The book begins by discussing the challenges of conventional CMOS technology from the perspective of low-power applications, and it also reviews the basic science and developments of subthreshold swing technology and recent advancements in the field. The authors discuss the impact of semiconductor materials and architecture designs on TFET devices and the performance and usage of FET devices in various domains such as nanoelectronics, Memory Devices, and biosensing applications. They also cover a variety of FET devices, such as MOSFETs and TFETs, with various structures based on the tunneling transport phenomenon.

The contents of the book have been designed and arranged in such a way that Electrical Engineering students, researchers in the field of nanodevices and device-circuit codesign, as well as industry professionals working in the domain of semiconductor devices, will find the material useful and easy to follow.

Table of Contents:

Chapter 1. Challenges of Conventional Cmos Technology in Perspective of Low Power Applications

Chapter 2. Basic Science and Development of Subthreshold Swing Technology

Chapter 3. Historical Development of MOS technology to Tunnel FETs

Chapter 4. Modeling of Gate Engineered TFETs: Challenges and Opportunities

Chapter 5. Modeling of Gate Engineered TFET: challenges and Opportunities.

Chapter 6. Evolution of Heterojunction Tunnel Field Effect Transistor and its Advantages

Chapter 7. Analog / RF performance analysis of TFET device

Chapter 8. DC Analysis and Analog/HF Performances of GAA-TFET with Dielectric Pocket

Chapter 9. Investigation on Ambipolar Current Suppression in Tunnel FETs

Chapter 10. Analysis of Channel Doping Variation on Transfer Characteristics to High Frequency performance of F-TFET

Chapter 11. Design of Nanotube TFET Biosensor

Chapter 12. TFET-based Memory Cell Design with Top-down Approach

Chapter 13. Designing of nonvolatile memories utilizing Tunnel Field Effect Transistor

Chapter 14. TFET-based Universal

Chapter 15. TFET-based Level Shifter Circuits for Low Power Applications

[paper] Single Gate Extended Source Tunnel FET

Jagritee Talukdar^a, Gopal Rawat^b, Bijit Choudhuri^a, Kunal Singh^c, Kavicharan Mummaneni^a

Device Physics Based Analytical Modeling for Electrical Characteristics of Single Gate Extended Source Tunnel FET (SG-ESTFET)

Superlattices and Microstructures (2020): 106725

DOI: 10.1016/j.spmi.2020.106725

^aDECE, NIT Silchar, Assam, India
^bDECE, NIT Hamirpur, Himachal Pradesh, India
^cDECE, NIT Jamshedpur, Jharkhand, India

Abstract: In this paper, a 2D analytical model for Single Gate Extended Source Tunnel FET has been developed which is based on the solution of Poisson’s equation simplified using parabolic approximation method. Different electrical characteristics of device physics such as surface potential, drain current, lateral, and vertical electric field of SG-ESTFET are studied incorporating various parameters like mole fraction of SiGe layer, gate dielectric constants, etc. Furthermore, in modeling and simulation, the depletion region of the drain side is included considering the effect of the fringing field. The comercial TCAD device simulator has been used to verify the accuracy and validity of the proposed analytical model for various electrical parameters such as gate to source voltage, mole fraction, and gate dielectric constants. The validity of the proposed model is confirmed by observing a decent agreement between modeling and simulation. The proposed compact model delivers quick and accurate values of various performance parameters.

Fig: 2D schematic device structure of SG-ESTFET

[paper] Electrostatically doped drain engineered DG‐TFET

Shaikh, MRU, Loan, SA, Alshahrani, A.
Electrostatically doped drain engineered DG‐TFET:
Proposal and Analysis
IJNM 2020;e2769
DOI: 10.1002/jnm.2769

Abstract: In this paper, a drain‐engineered double‐gate Tunnel‐FET (DE‐DG‐TFET) to enhance the electrical characteristics and analog parameters of a conventional DG‐TFET is proposed and examined through calibrated TCAD simulations. Unlike DG‐TFET, a constant n‐type doping, N_cd, (5E17 cm⁻³ − 2E18 cm⁻³), in the channel/drain regions of DE‐DG‐TFET is used, resulting in a p+‐n‐n structure instead of conventional p+‐i‐n structure. Further, p+‐n‐n is modified to p+‐n‐n+ using electrostatic doping (ED) method on the drain side with Hafnium (ϕ_m = 3.9 eV) as a lateral (top and bottom) and side metal electrode. A high n+‐drain doping ensures the drain contact remains ohmic. Higher electric field at p+‐n source‐channel junction enhances the ON‐state BTBT current. While the absence of metallurgical junction provides large tunneling width across the channel/drain junction, resulting in suppression of ambipolar current (I_AMB). At N_cd doping of 1E18 cm⁻³, DE‐DG‐TFET demonstrates ~7 times increase in I_ON while I_AMB is suppressed by ~5 orders of magnitude. In addition to this, the proposed device improves analog/RF figures of merit, 45% in voltage gain and ~5 times in peak f_T.

FIG: Key steps for fabrication of the proposed DEDG-TFET

Acknowledgement: This work was supported by Ministry of Electronics & Information Technology (MeitY), Government of India through Visvesvaraya PhD Scheme.

[PhD] Compact DC Modeling of Tunnel-FETs

Compact DC Modeling of Tunnel-FETs

November 2019

PhD Thesis of Fabian Horst 

Doctor Advisor: Profs. Benjamin Iniguez and Alexander Kloes

Abstract - In the last decade, the tunnel field-effect transistor (TFET) has gained a lot of interest and is handled as a possible successor of the conventional MOSFET technology. The current transport of a TFET is based on the band-to-band (B2B) tunneling mechanism and therefore, the subthreshold slope at room temperature can overcome the limit of 60 mV/dec. In order to describe and analyze the TFET behavior in circuit simulations, this dissertation introduces a compact DC model for double-gate TFETs. The modeling approach considers the B2B tunneling and the parasitic effect of trap-assisted tunneling (TAT) in the ON- and AMBIPOLAR-state of the TFET. It includes a 2D compact potential equation package to de-scribe the band diagram of the TFET. Based on the band diagram, the B2B tunneling and TAT current part are derived separately. In order to do so, firstly a compact expression for the tunneling length is found, which is then used together with a numerical robust Wentzel-Kramers-Brillouin (WKB) approach to calculate the tunneling probability. Afterwards, using Landauer’s tunneling equation, the tunneling generation rate is calculated and approximated to come to a closed-form expression for the current density. Further approximation of the current density by a mathematical function, compact expressions for the resulting B2B tun-neling and TAT current are achieved. The verification of the model is done with the help of TCAD Sentaurus simulation data for various simulation setups. Furthermore, the validity of the model is proven by measurements of fabricated complementary TFETs. In order to demonstrate the numerical stability and continuity as well as the flexibility, simulations of TFET-based logic circuits like a single-stage inverter or an SRAM cell are performed and analyzed. The combination of the DC model with an TFET AC model allows for a transient simulation of an 11-stage ring oscillator. 

Fig: 2D sketch of the n-type DG TFET device geometry, showing the channel thickness t ch , the channel length l ch , the gate oxide thickness tox and the length of the S/D region l sd . Source (S) and drain (D) region are highly p/n-doped with a doping concentration N s/d 

URL: http://hdl.handle.net/10803/668957

Digital and analog TFET circuits: Design and benchmark

Solid-State Electronics
Volume 146, August 2018, Pages 50–65
Invited Review

S. Strangio^a,b, F. Settino^a,b, P. Palestri^a, M. Lanuzza^b, F. Crupi^b, D. Esseni^a, L. Selmi^a,c

^aDPIA, Università degli Studi di Udine, Via delle Scienze 206, I-33100 Udine, UD, Italy
^bDIMES, Università della Calabria, Via P. Bucci, 41C, I-87036 Arcavacata di Rende (CS), Italy
^cDipartimento di Ingegneria “Enzo Ferrari”, Università degli Studi di Modena e Reggio Emilia, I-41100 Modena, Italy

ARTICLE INFO: The review of this paper was arranged by Prof. S. Cristoloveanu
https://doi.org/10.1016/j.sse.2018.05.003

HIGHLIGHTS:

• We report simulations of basic analog and digital circuit blocks employing tunnel-FETs.
• Template III-V heterojunction tunnel-FETs are benchmarked against silicon FinFETs for the 10 nm node.
• Performance are evaluated down to VDD = 200 mV.
• Tunnel-FETs result advantageous with respect to silicon FinFET for VDD below approximately 400 mV.

ABSTRACT: In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.

FIG: Sketch of n- and p-type TFET and FinFET device architectures. The red and blue colors indicate the n- and p-doping types, respectively (green: intrinsic semiconductor, transparent-grey: oxide). TFET dimensions are: LG=20nm, nanowire cross section (LS)=7nm, EOT=1nm. FinFET dimensions are: LG=14nm, tfin=8nm, hfin=21nm, EOT=0.88nm. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

[paper] A Novel Reconfigurable sub-0.25V Digital Logic Family Using the Electron-Hole Bilayer TFET

Cem Alper, Jose Luis Padilla, Pierpaolo Palestri, Senior Member, IEEE

and Adrian M. Ionescu, Fellow, IEEE

IEEE Journal of the Electron Devices Society

doi: 10.1109/JEDS.2017.2758018

Abstract: We propose and validate a novel design methodology for logic circuits that exploits the conduction mechanism and the presence of two independently biased gates (”n-gate” and ”p-gate”) of the electron-hole bilayer TFET (EHBTFET). If the device is designed to conduct only under certain conditions e.g. when Vn-gate = VDD and Vp-gate = 0, it then shows an ’XOR-like’ behavior that allows the implementation of certain logic gates with a smaller number of transistors compared to conventional CMOS static logic. This simplifies the design and possibly results in faster operation due to lower node capacitances. We demonstrate the feasibility of the proposed EHBTFET logic for low supply voltage operation using mixed device/circuit simulations including quantum corrections [read more...]

FIG: Sketch of the hetero-gate InGaAs EHBTFET and its circuit symbol.

Devices That You Definitely Will (and Just Might) Use: Emerging Transistor Technologies for the Near-and Long-Term

 WEDNESDAY June 04, 4:00pm - 6:00pm | Room 302 

 TRACK: EDA

 TOPIC AREA: EMERGING TECHNOLOGIES

 SPECIAL DAC SESSION 63: Devices That You Definitely Will (and Just Might) Use: Emerging Transistor Technologies for the Near-and Long-Term

Chair:  Michael Niemier; Univ. of Notre Dame, IN
Organizers:  Michael Niemier; Univ. of Notre Dame, IN
Xiaobo Sharon Hu; Univ. of Notre Dame, IN

Want to learn about the latest developments in FinFET-based processor design? What other transistor technologies might follow FinFETs and would they bring new design and modeling challenges? Come to this session to hear about both near- and long-term transistor technologies and their prospects for continuing Moore’s Law-based performance scaling trends. The session will begin with a discussion of FinFET technology; subsequent presentations will discuss tunnel transistors (TFETs) as well as other emerging FET technologies that could reenable voltage scaling. The session will conclude with a discussion of modeling efforts that consider the impact of new device technologies on von Neumann architectures as well as hybrid analog/digital circuits and architectures.

63.1 FinFET's and Their Implications for Design Now and in the Future

• Speaker: Rob Aitken; ARM Ltd., San Jose, CA
  Greg Yeric; ARM Ltd., Austin, TX
  Brian Cline; ARM Ltd., Austin, TX
  Lucian Shifren; ARM Ltd., San Jose, CA

63.2 Emerging Devices for Logic: Can a Low-Power Switch Be Fast?

• Speaker: Thomas Theis; IBM T.J. Watson Research Center, Yorktown Heights, NY

63.3 Energy Efficient Tunnel-FET Transistors for Beyond CMOS Logic

• Speaker: Uygar Avci; Intel Corp., Portland, OR
  Daniel Morris; Intel Corp., Portland, OR
  Ian Young; Intel Corp., Hillsboro, OR

63.4 Steep Slope Devices: Enabling New Architectural Paradigms

• Speaker: Vijaykrishnan Narayanan; Pennsylvania State Univ., State College, PA
  Karthik Swaminathan; Pennsylvania State Univ., State College, PA
  Huichu Liu; Pennsylvania State Univ., State College, PA
  Moon Seok Kim; Pennsylvania State Univ., State College, PA
  Xueqing Li; Pennsylvania State Univ., State College, PA
  Jack Sampson; Pennsylvania State Univ., University Park, PA

[more about the DAC Conference]

[Final Program] EUROSOI 2014, Tarragona, Catalonia, Spain; January 27-29, 2014

The 10th Workshop of the Thematic Network
on Silicon on Insulator Technology, Devices and Circuits 

(EUROSOI 2014) 

Tarragona, Catalonia, Spain 

January 27-29, 2014 

The EUROSOI Workshop is an international forum to promote interaction and exchangesbetween research groups and industrial partners involved in SOI activities all over the world. Following the lively experience of the previous meetings in Granada (2005), Grenoble (2006), Leuven (2007), Cork (2008), Gšteborg (2009), Grenoble (2010), Granada (2011), Montpellier (2012), Paris (2013), EUROSOI 2014 will be held in Tarragona, Catalonia, Spain, and will include a short course program, oral and poster sessions, outstanding key-note presentations, as well as ample rooms for informal discussions. EUROSOI covers recent progress in SOI technologies and will be of interest to materials and device scientists, as well as to process, circuits and applications oriented engineers.

Monday, January 27, 2014

8:30 REGISTRATION
9:05-9:20 SHORT COURSE OPENING
9:20-11:00 PART 1 - EDS MINI-COLLOQUIUM ON SOI TECHNOLOGY 
9:20-10:10 "Process Challenges for Advanced Ge CMOS Technologies" Cor Claeys (IMEC, Leuven, Belgium)
10:10-11.00 "From Floating-Body Memory to Unified Memory on SOI" Sorin Cristoloveanu (INPG, Grenoble, France)
11:00-11:30 COFFEE BREAK
11:30-12:20 "Fabrication Challenges for sub-10 nm Technology nodes" Michael Ostling (KTH, Stockholm, Sweden)
12:20-13:00 "ESD protection of FD and MuG SOI CMOS Chips" Dimitris Ioannou (George Mason University, Fairfax, VA, USA)
13:00-14:30 LUNCH
14:30-15:50 Part 2 -EUROSOI TUTORIAL 
14:30-15:20 "Advanced SOI MOSFET architectures" Jason Woo (UCLA, CA, USA)
15:20-16:00 "SOI CMOS sensors, transistors and circuits for ultra-low-power and harsh environment applications" Denis Flandre (UCL, Louvain-la-Neuve, Belgium)
16:00-16:30 COFFEE BREAK
16:30-18:00 SOI MOSFET CHARACTERIZATION 
16:30-17:20 "On the threshold voltage and interface coupling in advanced SOI MOSFETs" Tamara Rudenko (ISP, Kyiv, Ukraine)
17:20-18:00 "From SOI MOSFET to Spin MOSFET: a modeling approach" Viktor Sverdlov (Tu-Wien, Austria)
20:30 EUROSOI RECEPTION

Tuesday January 28, 2014 

8:15 REGISTRATION
8:45-9:00 OPENING
9:00-11:00 PLENARY SESSIONS 
9:00-9:40 "Taking the next step on advanced HKMG SOI technologies -from 32 nm PD SOIvolume production to 20/28 FD SOI and beyond" Manfred Horstmann (Globalfoundries, Dresden, Germany) invited talk
9:40-10:20 INVITED TALK 
Heike Riel (IBM Research, Zurich) -invited talk
10:20-11:00 "Beyond Si CMOS: Benefits and Challenges " Rafael Rios (Intel, Portland OR, USA) -invited talk
11:00-11:20 COFFEE BREAK
11:20-13:00 SOI MATERIALS TECHNOLOGY AND CHARACTERIZATION 
11:20-11:40 Process and performance of Copper TSVs Lado Filipovic et al.
11:40-12:00 Increasing mobility and spin lifetime with shear strain in thin silicon films Dmitri Osintsev et al.
12:00-12:20 A Comparative Study of Variability of RTN Power Spectral Densities in Bulk and SOIMOSFETs  Louis Gerrer et al.
12:20-12:40 Low temperature noise spectroscopy of p-channel SOI FinFETs Bogdan Cretu et al.
12:40-13:00 Channel Length Influence on the Low-Frequency Noise of Strained 45o Rotated Triple Gate SOI nFinFETs Marcio Alves Sodre de Souza et al.
13:20-14:10 LUNCH
14:10-15:50 SOI MOSFET TECHNOLOGY 
14:10-14:30 Impact of S/D doping profile into electrical properties in nanoscaled UTB2SOI  devices Carlos Sampdero et al.
14:30-14:50 TCAD investigation on a formal Neuron device in 28nm UTBB FDSOI technology Philippe Galy et al.
14:50-15-10 Dual ground plane for high-voltage MOSFET in UTBB FDSOI Technology Antoine Litty et al.
15:10-15:30 Trigate NanoWire MOSFETs Analog Figures of Merit Kilchytska, Valeriya et al.
15:30-15:50 Electrostatically-doped SL FET optimized to meet all the ITRS power targetsat V_DD=0.4 V Elena Gnani et al.
15:50-16:00 COFFEE BREAK
16:00-17:20 SOI MOSFET CHARACTERIZATION 
16:00-16:20 Enhanced Dynamic Threshold Voltage UTBB SOI nMOSFETs Katia Sasaki et al.
16:20-16:40 Parasitic bipolar effect in advanced FD SOI MOSFETs: experimental evidence andgain extraction Fanyu Liu et al.
16:40-17:00 Impact of Lateral Fin-Width Non-Uniformity of FinFETs Clarissa Prawoto et al.
17:00-17:20 Surface effects on split C-V measurements on SOI wafers Luca Pirro et al.
17:20-17:40 Impact of Self-Heating on UTB MOSFET ParametersS ergej Makovejev at al.
17:40-18:00 POSTER BRIEFING (3 MIN EACH) 
18:00-19:40 POSTER SESSION 
Subthreshold Behavior of the PD SOI NMOS Device Considering BJT and DIBL Effects James Kuo et al.
Investigation of Statistical Effects on Reliability of SOI FinFETs Including Sidewall Crystal Orientation Salvatore Amoroso et al.
Powering the More than Moore Electronics with i-MOSLining Zhang et al.
Analysis of Short-Channel Effect in SOTB-MOSFET for Ultra-Low Power Applications Hidenori Miyamoto et al.
2D Analytical Modeling of the Trap-Assisted-Tunneling Current in Double-GateTunnel-FETs Michael Graef et al.
Improved Compact Current Model for FinFETs Based in a New Geometric Approach Arianne Pereira et al.
Capability of the IDS Analytical Model on Predicting the Diamond Variability by Usingthe F-Test Statistic Evaluation Salvador Gimenez et al.
An appraise of the sources of electrical parameters variation in DGMOS Rodrigo Picos et al.
An analytical model for the inversion charge distribution in GAA MOSFETs with rounded corners Francisco Ruiz et al.
The Negative World-line Holding Bias Effect on the Retention Time in FBRAMs Sara Santos et al.
20:30 GALA DINNER

Wednesday January 29, 2014 

8:30-10:30 SOI MOSFET MODELLING 
8:30-8:50 Comprehensive Low-Field Mobility Modeling in Nano-Scaled SOI Channels Zlatan Stanojevic et al.
8:50-9:10 A comprehensive DC current model to describe FinFET self-heating effects Benito Gonz‡lez et al.
9:10-9:30 Channel-Length Impact on Supercoupling Effect in FD-MOSFETs Carlos Navarro et al.
9:30-9:50 Substrate Effect on Threshold Voltage of long and short channel UTBB SOI nMOSFETs Joao Martino et al.
9:50-10:10 In depth characterization of electron transport in 14nm FD-SOI nMOS devices Minju Shin et al.
10:10-10:30 Role of the gate in ballistic nanowire SOI MOSFET Anurag Mangla et al.
10:30-10:50 COFFEE BREAK
10:50-13:10 CIRCUITS, MEMORIES AND SENSORS 
10:50-11:30 "Future of Multi-gate CMOS Technology" Hiroshi Iwai (University of Tokyo, Japan)
11:30-11:50 Impact of SEU on Bulk and FDSOI CMOS SRAM Walter Enrique Calienes Bartra et al.
11:50-12:10 Mechanical Characterization and Modelling of Lorentz Force Based MEMS Magnetic Field Sensors Petros Gkotsis et al.
12:10-12:30 Performance of Source-Follower Buffers Implemented with Junctionless Nanowire nMOS Transistors Michelly Souza et al.
12:30-12.50 PMOSFET-based Pressure Sensors in FD SOI Technology Benoit Olbrechts et al.
12:50-13:10 Performance of Common-Source current mirrors with asymmetric self-cascode SOInMOSFETs  Rafael Assalti et al.
13:10-14:20 LUNCH
14:20-16:10 BEYOND CMOS: NANOWIRES AND JUNCTIONLESS TRANSISTORS 
14:20-15:00 "2D semiconductor channels for ultimate thickness scaling and other versatile applications" Athanasios Dimoulas (IMS, Demokritos, Athens, Greece)
15:00-15:20 A way to solve Poisson equation en cylindrical coordinates to obtain a compact model for Junctionless Gate All Around MOSFET Franois Lime et al.
15:20-15:40 Explicit analytical charge and capacitance models for Junctionless Surrounding GateTransistors  Oana Moldovan et al.
15:40-16:00 Performance Evaluation of Stacked Gate-All-Around MOSFETs Meng-Hsueh Chiang et al.
16:00-16:20 Modeling of Quantization Effects in Nanoscale DG Junctionless MOSFETs Thomas Holtij et al.
16:20-16:30 COFFEE BREAK
16:30-16:50 BEYOND CMOS (TFETs) 
16:30-16:50 Heterojunction TFET inverters providing better performance than multi-gate CMOS at sub 0.3V Vdd Elena Gnani et al.
16:50-17:10 Transport mechanism influence on Vertical Nanowire-TFET analog performance as a function of temperature Paula Agopian et al.
17:10-17:30 3D Modeling of Direct Band-to-Band Tunneling in Nanowire TFETs. Lidija Filipovic et al.
17:30-17:50 Influence of the gate oxide thickness on the Analog Performance of vertical Nanowire-Tunnel FETs with Ge Source Felipe Neves et al.
17:50-18:10 Influence of a precisely positioned channel dopant on the performance of gate-allaround Si nanowire transistor: a full 3D NEGF simulation study Vihar Georgiev et al.
18:10-18:20 CONCLUSIONS AND ANNOUNCEMENTS 

[Final Program] 11th International Workshop on Compact Modeling

11th International Workshop on Compact Modeling (IWCM 14)

January 23 (Thursday), 2014

Suntec Singapore Convention and Exhibition Centre (Room 309)

Workshop Program

9:00-9:10am Welcome address
Mansun Chan (workshop chair)

Session I: Modeling for Compact Semiconductor
Session Chair: Lining Zhang

9:10-9:35am Challenges and Prospects of Compact Modeling for Future Generation III-V/Si Co-integrated ULSI Circuit Design
Xing Zhou, Siau Ben Chiah, Binit Syamal, Hongtao Zhou, Arjun Ajaykumar, and Xu Liu; Nanyang Technological University, Singapore
9:35-10:00am A Large Signal Model for InP/InGaAs Double Heterojunction Bipolar Transistors
Yan Wang and Yuxia Shi; Tsinghua University, China
10:00-10:25am Analytical Modeling for AlGaN/GaN HEMTs
Aixi Zhang, Lining Zhang, Zhikai Tang, Xiaoxu Cheng*, Yan Wang*, Kevin J. Chen, and Mansun Chan; The Hong Kong University of Science and Technology, Hong Kong, China; *Tsinghua University, China

10:25-10:40am Break

Session II: Non-Classical Device Modeling and Platform
Session Chair: Xing Zhou

10:40-11:05am Developing i-MOS as a Compact Model Standardization Platform
Lining Zhang and Mansun Chan; The Hong Kong University of Science and Technology, Hong Kong, China
11:05-11:30am An Analytic Model for Nanowire Tunnel-FETs
Ying Liu, Jin He, Mansun Chan*, Caixia Du**, Yun Ye, Wei Zhao, Wen Wu and Wenping Wang; Peking University Shenzhen SOC Key Laboratory, China; *The Hong Kong University of Science and Technology, Hong Kong, China; **Shenzhen Huayue Teracale Chip Electronic Limited Co., China
11:30-11:55am A Channel Potential Based Model for SiO2- Core Si-Shell SRGMOSFET
Xiangyu Zhang, Jin He, Mansun Chan*, Caixia Du**, Yun Ye, Wei Zhao, Wen Wu and Wenping Wang; Peking University Shenzhen SOC Key Laboratory, China; *The Hong Kong University of Science and Technology, Hong Kong, China; **Shenzhen Huayue Teracale Chip Electronic Limited Co., China

11:55am-2:00pm Lunch

Session III: Power Device Modeling
Session Chair: Young June Park

2:00-2:25pm Compact Modeling of the Reverse Recovery Effect in LDMOS Body Diode (Invited)
M. Miyake; Hiroshima University, Japan
2:25-2:50pm Compact Modeling of the SiC IGBT Including the Switching at High Temperature
K. Matsuura, M. Miura-Mattausch, M. Miyake and H. J. Mattausch; Hiroshima University, Japan
2:50-3:15pm Experimental Verification of Power MOSFET Model under Switching Operations
A. Saito, M. Miura-Mattausch, M. Miyake, T. Umeda and H.J. Mattausch; Hiroshima University, Japan

3:15-3:30pm Break

Session IV: Reliability Modeling
Session Chair: Jin He

3:30-3:55pm 3D Monte Carlo Reaction-Diffusion Simulation Framework to model Time Dependent Dielectric Breakdown in BEOL Oxide
Seong Wook Choi and Young June Park; Seoul National University, Korea
3:55-4:20pm Development of NBTI and Channel Hot Carrier (CHC) Effect Models and their Application for Circuit Aging Simulation
Chenyue Ma, Hans Jürgen Mattausch, Kazuya Matsuzawa*, Seiichiro Yamaguchi*, Teruhiko Hoshida*, Masahiro Imade*, Risho Koh*, Takahiko Arakawa* and Mitiko Miura-Mattausch; Hiroshima University, Japan; * Semiconductor Technology Academic Research Center, Japan
4:20-4:45pm Modeling of the Surface Charges on Au Electrode Including Pseudocapacitance
Jooseong Kwon, Intae Jeong, Sungwook Choi and Young June Park; Seoul
National University, Korea

4:45-4:55pm Closing Remarks
Hans Juergen Mattausch (workshop co-chair)