Showing posts with label Parasitic capacitance. Show all posts
Showing posts with label Parasitic capacitance. Show all posts

Oct 4, 2021

[paper] Flexible Megahertz Organic Transistors

Jakob Leise1,4, Jakob Pruefer1,4, Ghader Darbandy1, Aristeidis Nikolaou1,4, Michele Giorgio2, Mario Caironi2, Ute Zschieschang3, Hagen Klauk3, Alexander Kloes1, Benjamin Iñiguez4
and James W. Borchert5
Flexible megahertz organic transistors and the critical role of the device geometry on their dynamic performance
Journal of Applied Physics 130, 125501 (2021); 
DOI: 10.1063/5.0062146
  
1NanoP, TH Mittelhessen University of Applied Sciences, Gießen 35390, Germany
2Center for Nano Science and Technology @PoliMi, Istituto Italiano di Tecnologia, Milano 20133, Italy
3Max Planck Institute for Solid State Research, Stuttgart 70569, Germany
4DEEA, Uniersitat Rovira i Virgili, Tarragona 43007, Spain
5Georg August University of Goettingen, Goettingen 37077, Germany

  
Abstract: The development of organic thin-film transistors (TFTs) for high-frequency applications requires a detailed understanding of the intrinsic and extrinsic factors that influence their dynamic performance. This includes a wide range of properties, such as the device architecture, the contact resistance, parasitic capacitances, and intentional or unintentional asymmetries of the gate-to-contact overlaps. Here, we present a comprehensive analysis of the dynamic characteristics of the highest-performing flexible organic TFTs reported to date. For this purpose, we have developed the first compact model that provides a complete and accurate closed-form description of the frequency-dependent small-signal gain of organic field-effect transistors. The model properly accounts for all relevant secondary effects, such as the contact resistance, fringe capacitances, the subthreshold regime, charge traps, and non-quasistatic effects. We have analyzed the frequency behavior of low-voltage organic transistors fabricated in both coplanar and staggered device architectures on flexible plastic substrates. We show through S-parameter measurements that coplanar transistors yield more ideal small-signal characteristics with only a weak dependence on the overlap asymmetry. In contrast, the high-frequency behavior of staggered transistors suffers from a more pronounced dependence on the asymmetry. Using our advanced compact model, we elucidate the factors influencing the frequency-dependent small-signal gain and find that even though coplanar transistors have larger capacitances than staggered transistors, they benefit from substantially larger transconductances, which is the main reason for their superior dynamic performance.
Fig: Schematic cross-section of a top-contact (TC) organic TFT. Here, the semiconductor layer separates the source and drain contacts from the gate dielectric and thus from the gate-field-induced charge-carrier channel; hence, these transistors are also referred to as staggered TFTs. The overlap regions are assumed as a series connection of two capacitances. However, when the organic semiconductor (OSC) is operated in accumulation, the accumulation charges change the behavior of the series connection. The charge density at the source end of the channel is assumed to be found in the entire gate-to-source overlap region. 

Acknowledgments: The authors thankfully acknowledge funding for this project from the German Federal Ministry of Education and Research (“SOMOFLEX,” No. 13FH015IX6) and EU H2020 RISE (“DOMINO,” No. 645760), and the German Research Foundation (DFG) under Grant Nos. KL 1042/9-2, KL 2223/6-1, and KL 2223/6-2 (SPP FFlexCom). The authors would like


Jun 24, 2020

[paper] Compact Modeling of Parasitic FET capacitance

Sharma, S. M., Singh, A., Dasgupta, S., & Kartikeyan, M. V. 
A review on the compact modeling of parasitic capacitance: 
from basic to advanced FETs. 
Journal of Computational Electronics
DOI: 10.1007/s10825-020-01515-4

Abstract: This paper presents a review on the development of parasitic-capacitance modeling for metal–oxide–semiconductor feldefect transistors (MOSFETs), covering models developed for the simple parallel-plate capacitance and the nonplanar and coplanar plate capacitances required for the intrinsic and extrinsic part of such devices. A comparative study of various extrinsic capacitance models with respect to a reference model is used to analyze the benefts of the various approaches. Capacitance models for basic MOSFETs and advance multigate FETs with two-dimensional (2D) and three-dimensional (3D) structures are reviewed. It is found that the elliptical feld lines between the gate electrodes and source/drain region are modeled very well, while deviations of ±2% in the orthogonal plate capacitance are observed when the gate electrode thickness is varied from 5 to 20nm.
Fig: The 3D structure of a FinFET

Acknowledgements: The authors would like to thank the Department of Electronics and Communication Engineering, IIT Roorkee, for their valuable support in carrying out this research work.