EKV2.6 conference paper reached 50 reads

W. Grabinski et al., "FOSS EKV2.6 Verilog-A Compact MOSFET Model," 

ESSDERC, Krakow, Poland, 2019, pp. 190-193.

doi: 10.1109/ESSDERC.2019.8901822

article with 700 reads

Wladek Grabinski, Matt Bucher,Jean-Michel Sallese and François Krummenacher

Advanced Compact Modeling of the Deep Submicron Technologies

Journal of Telecommunications and Information Technology (3-4):31-42, March 2000

Article reached 1,000 reads

A. Bazigos, M. Bucher, J. Assenmacher, S. Decker, W. Grabinski and Y. Papananos

An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs

IEEE Transactions on Electron Devices,

vol. 58, no. 11, pp. 3751-3758, Nov. 2011.

doi: 10.1109/TED.2011.2164080

Abstract:

The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implanted devices. The generalized adjusted CC method is based on the theory of the charge-based MOS transistor model. It introduces an adjusted current criterion, depending on VDS , allowing to coherently determine VTH for the entire range of VDS from linear operation to saturation. The method uses commonly available ID versus VG data with focus on moderate inversion. The method is validated with respect to the ideal surface potential model, and its suitability is demonstrated with technology-computer-aided-design data from a 65nm CMOS technology and measured data from a 90nm CMOS technology. Comparison with other widely used threshold voltage extraction methods is provided.

[paper] Novel General Compact Model Approach

A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond

Qiang Huo, Zhenhua Wu, Weixing Huang, Xingsheng Wang, Senior Member, IEEE, Geyu Tang, Jiaxin Yao, Yongpan Liu, Feng Zhang, Ling Li, and Ming Liu, Fellow,IEEE

Abstract: This work presents a novel general compact model for 7nm technology node devices like FinFETs. As an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects, the general compact model combining few TCAD calibrated compact models with statistical methods can eliminate the tedious physical derivations. The general compact model has the advantages of efficient extraction, high accuracy, strong scaling capability and excellent transfer capability. As a demo application, two key design knobs of FinFET and their multiple impacts on RC control ESD power clamp circuit are systematically evaluated with implementation of the newly proposed general compact model, accounting for device design, circuit performance optimization and variation control. The performance of ESD power clamp can be improved extremely. This framework is also suitable for pathfinding researches on 5nm node gate-all-around devices, like nanowire (NW) FETs, nanosheet (NSH) FETs and beyond.

Index Terms: General compact model, FinFET, ESD power clamp, 7 nm technology node and beyond.

Fig. (A) The schematic of partial parameters of FinFET. (B) Key design rules of 7nm node FinFET as according to [1]. 

Access: https://arxiv.org/ftp/arxiv/papers/1905/1905.11207.pdf

REF: [1] S. Narasimha et al.“A 7nm CMOS technology platform for mobile and high performance compute application,” IEEE International Electron Devices Meeting (IEDM), Dec. 2017, pp. 29.5.1-29.5.4, doi: 10.1109/IEDM.2017.8268476.

[paper] Design Strategies for Ultralow Power 10nm FinFETs

Design Strategies for Ultralow Power 10nm FinFETs

Abhijeet Walkea^a, Garrett Schlenvogtb^b, Santosh Kurineca^a

^aDepartment of Electrical & Microelectronic Engineering, RIT, New York, USA

^bTCAD Application Engineer, Silvaco

Received 12 June 2017, Accepted 19 June 2017, Available online 20 June 2017

Abstract: In this work, new design strategies for 10nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20pA/μm< I_OFF <50pA/μm) and ultralow power (ULP) (I_OFF <20pA/μm) requirements using three dimensional (3D) TCAD simulations. The punch-through stop implant, source and drain junction placement and gate workfunction are varied in order to study the impact on the OFF-state current (I_OFF), transconductance (g_m), gate capacitance (C_gg) and intrinsic frequency (f_T). It is shown that the gate length of 20nm for the 10nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction.

[read more https://doi.org/10.1016/j.sse.2017.06.012]