Mixed Signal SoC design Marathon using eSim & SKY130

Marathon Date : 23 Sept. - 8 Oct. 2022

The following submissions are adjudged as Outstanding, Excellent, Very good and Good by the FOSSEE and the VSD teams.

• Outstanding
• Excellent
• Very Good
• Good

List of Outstanding Circuits:

#	Participant	Circuit	Institute	GitHub
1	Milad Vafaieenezhad	Window Comparator Along with MOD-16 Counter for Counting Based Data Line Selection Operation	Shahed University	View Repo
2	Krunal Badlani	Crack Sensing Circuit	Indian Institute of Technology Hyderabad	View Repo
3	Karuppusamy V	Flash Type ADC	Bannari Amman Institute of Technology	View Repo
4	Inderjit Singh Dhanjal	32-bit SRAM implementation in eSim using Skywater 130nm CMOS technology	K. J. Somaiya College of Engineering	View Repo
5	Tanay Das	Design of a Class D Audio Amplifier IC Using Sliding Mode Control and Negative Feedback	Sikkim Manipal Institute of Technology	View Repo
6	Jayanth Nedunuri	Implementation of 4 bit Two Step Flash ADC	Jyothishmathi institute of Technology and Science	View Repo
7	Aishwarya Balkrishna Patil	Design and Implementation of Automatic Security Monitoring System	Kolhapur Institute of Technology’s College of Engineering, Kolhapur	View Repo
8	Swagatika Meher	3-bit CMOS based TIQ comparator Flash ADC	Odisha University of Technology and Research, Bhubaneswar, Odisha	View Repo
9	Surya V	3-bit Flash ADC using ROM-based Encoder	National Institute of Technology, Tiruchirapalli	View Repo
10	Sanket M Mantrashetti	Design of 8x8 SRAM based on 6T SRAM cell	R. V. College of Engineering	View Repo
11	Avishek Choudhary	10-bit C2C DAC	Thapar Institute of Engineering and Technology	View Repo
12	Nalinkumar S	Implementation of Quadruple - Window Comparator Along with Prioritized MOD-16 Counter for Data Line Multiplexing Operation	Madras Institute of Technology Campus, Anna University	View Repo
13	Rubankumar D	Astable Multivibrator Along with MOD-16 Counter for Counting Based Data Line Selection Operation	Madras Institute of Technology Campus, Anna University	View Repo
14	Vanshika Tanwar	Implementation of 3 Bit Flash ADC performed in eSim	Dronacharya Group Of Institutions, Greater Noida	View Repo
15	Ravi Prakash Vishwakarma	8 Bit Counter/Ramp Type ADC	Madan Mohan Malaviya University Of Technology	View Repo
16	E Balakrishna	Implementation of 4 Bit Flash ADC mixed signal circuit using 130nm performed in eSim	Dronacharya Group of Institution, Greater Noida	View Repo

Contact eSim-fossee:
For more information about the marathon, write to us at contact-esim[at]fossee[dot]in

[paper] Roadmapping of Nanoelectronics for the New Electronics Industry

Paolo Gargini¹,Francis Balestra², and Yoshihiro Hayashi³

Roadmapping of Nanoelectronics for the New Electronics Industry

Appl. Sci. 2022, 12(1), 308

DOI: 10.3390/app12010308

Received: 4 November 2021 / Revised: 17 December 2021 

Accepted: 20 December 2021 / Published: 29 December 2021

Academic Editor: Gerard Ghibaudo; This article belongs to the Special Issue Advances in Microelectronic Materials, Processes and Devices

   
1IEEE IRDS, (US)
2 CNRS, Grenoble INP (F)
3 Keio University, Tokyo (J)

Abstract: This paper is dedicated to a review of the international effort to map the future of nanoelectronics from materials to systems for the new electronics industry. The following sections are highlighted: the Roadmap structure with the international teams, the methodology and historical evolution, the various eras of scaling, the new ecosystems and computer industry, the evolving supply chain, the development of SoC and SiP, the advent of the Internet of Everything and the 5G communications, the dramatic increase of data centers, the power challenge, the technology fusion, heterogeneous and system integration, the emerging technologies, devices and computing architectures, and the main challenges for future applications.

FIG: 40 Years of Microprocessor Trend Data

VSD Free Webinar - Mixed-signal RISC-V based SoC on FPGA - 23rd July, 7pm IST

 

This 60-min webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to Verilog language and is a part of a mixed-signal SoC

If you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferred

This single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verification

Stay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board.

Agenda:

1. "FPGA on eSim"
   Guest Speaker - Prof. Kannan M Moudgalya, IIT Bombay
2. "chipIgnite Program"
   Guest Speaker - Mike Wishart, CEO eFabless
3. "Tapeout World Program"
   Guest Speaker - Naveed Sherwani, Chairman, OSFPGA
4. "Mixed-signal RISC-V based SoC on FPGA"
   Webinar Instructor - Shivani Shah

Webinar Curriculum:
1) Introduction
2) RVMYTH RISC-V Core
3) Why FPGAs ?
4) TL - Verilog to RTL verilog using Makerchip
5) Functional Simulation using iverilog
6) FPGA - Steps to create project
7) FPGA - Steps to generate IPs
8) FPGA - RTL simulation
9) FPGA - Synthesis
10) FPGA - Implementation and timing analysis
11) FPGA - Bit-stream generation, FPGA programming and ILA
12) Conclusion

Register here (if you don't see the form, please refresh page):
https://lnkd.in/gByg6fZ

10th All-Russia MES-2021 Conference

10th All-Russia Science and Technology Conference

Problems of Advanced Micro- and Nanoelectronic Systems Development 

MES-2021

March - November 2021

Moscow | Zelenograd

MES-2021 is dedicated to urgent issues of design automation of microelectronic systems, SoC, IP-blocks and a new element base of micro-and nanoelectronics. These issues have been and remain actual to science and technology, as evidenced by the major topics of the Annual International Conference on CAD and the development of micro-and nanoelectronic devices. MES is the largest conference in the field of CAD microelectronics in Russia and CIS countries. Proceedings of the MES conference is included in HAC list (issue 23.03.2021, pos. 2017) of Russian scientific journals, where should be published the main results of the PhD and DSc theses.

The upcoming 10th MES-2021 conference will be held mainly in the correspondence format, starting on March 01, 2021, and it will be concluded with its plenary session in November 2021.

Key discussion topics

1. Theoretical aspects of micro-and nanoelectronic systems (MES).
2. Methods and tools of design automation for micro-and nanoelectronic circuits and systems (VLSI CAD).
3. Experience of development of digital, analog, digital to analog, radio functional blocks of VLSI.
4. Features of VLSI design for nanometer technologies.
5. SoCs for advanced radioelectronic equipment.
6. Exhibition and presentation of commercial products.

Fields of interest of the conference include (but is not limited to) the following topics of relevant studies of VLSI design and VLSI design automation techniques:

Design

1. Circuits and Systems based on nanometer technologies

2. Systems on Chip

3. Digital VLSI Design

4. Design of analog functional blocks and radio VLSI

5. Design of mixed-signal VLSI

6. Methods of structural synthesis of analog, digital and mixed VLSI and complex functional blocks

7. Specialized (resistant to special effects, photosensitivity, etc.) VLSI

Simulation

1. Methods of simulation of digital, analog and mixed circuits and systems

2. Methods for radio VLSI simulation

3. Structural, logical, circuit, mixed and layout simulation

4. Methods for generating models and macromodels for VLSI CAD

5. Device and Technology simulation

6. Behavioral simulation

Information processing methods

1. Information coding

2. Digital data processing

3. Use of artificial intelligence methods, neural networks, etc. in micro- and nanoelectronic system designs

4. Unconventional arithmetic

5. High-performance computers

The development of nanoelectronic systems on new principles

1. Nanomagnetic storage devices

2. Magnetosensor structures

Call for participation in the conference program

I stage - After registration at least one of the co-authors of the report one can send an article. To do this, using their registration data, please log in (see upper right corner of screen). Fill in all required fields. On the website you should send a file containing the main text of the article (in Russian or English) and an extended abstract in English (if the main text is in Russian) or a simple abstract in Russian (if the main text of the article in English). Requirements for the articles sent to MES.

II stage - sending additional documents only for the articles, which have been reviewed and accepted to the conference program.

Visit the 10th MES-2021 conference website at: http://www.mes-conference.ru/index.php

[webinar] "More Moore Roadmap" by IRDS and SINANO

IEEE EDS France, IRDS and the SINANO Institute will organize a Webinar 

"More Moore Roadmap"

by Mustafa Badaroglu 

IRDS-IFT More Moore Leader

The webinar will be held on 8th April 2021 at 16:00 Paris time. Interest participants please register via IEEE vTools by the following link: https://events.vtools.ieee.org/event/register/267103

Other Webinars of the IRDS Chapters will be announced in the EDS Newsletters