[paper] An Accurate Analytical Modeling of Contact Resistances in MOSFETs

G. Bokitko, D. S. Malich, V. O. Turin*, and G. I. Zebrev

An Accurate Analytical Modeling of Contact Resistances in MOSFETs

Preprint · May 7, 2021 DOI: 10.13140/RG.2.2.29348.40321

National Research Nuclear University MEPHI, Moscow, Russia;
*Orel State University, Russia;

Abstract: As the MOSFET channel lengths decrease, the influence of parasitic source-drain resistance on the current characteristics becomes more and more important. The contact resistance is becoming a growing impediment to transistor power and performance scaling. This is a common challenge for SOI FETs, FinFETs and GAAFETs and any other type of transistor. Most of the modern compact models that are used in circuits simulations are too much technology oriented. We find it important to construct an analytical approach that could be served as a basis for compact modeling. This approach is based on analytical solution Kirchhoff’s equations and on the diffusion-drift field effect transistor model.

Fig: Equivalent MOSFET circuit with series resistance

[paper] Symmetric Source and Drain Voltage Clamping Scheme

K. Xia¹ (Senior Member, IEEE)

Symmetric Source and Drain Voltage Clamping Scheme

for Complete Source-Drain Symmetry in Field-Effect Transistor Modeling

in IEEE Transactions on Electron Devices

DOI: 10.1109/TED.2020.3004799

¹NXP Semiconductors N.V., Chandler, AZ 85224 USA

Abstract: For structurally symmetric field-effect transistors with respect to the source and the drain, their models should be electrically symmetric about the source-drain interchange. This article shows that the commonly used drain-source voltage clamping technique breaks such a symmetry. This article then presents a symmetric source and drain voltage clamping scheme to solve the problem. The effectiveness of the new scheme is demonstrated by both the planar MOSFET model PSP and the FinFET model BSIM-CMG.

Fig: Fourth order derivative of I_x with respect to V_x during Gummel symmetry test for an n-MOSFET on a 130nm technology. V_g = 1.15V. Vb = 0V. W/L = 10.02μm/0.15μm. V_d = −V_s = V_x. T=27^◦C. V_x stepsize is 10mV in the measurement and 0.1mV in the simulation, respectively.

[paper] On-Wafer FinFET-Based EUV/eBeam Detector Arrays

Wang, Chien-Ping, Yi-Pei Tsai, Burn Jeng Lin, Zheng-Yong Liang, Po-Wen Chiu, Jiaw-Ren Shih, Chrong Jung Lin, and Ya-Chin King

On-Wafer FinFET-Based EUV/eBeam Detector Arrays for Advanced Lithography Processes

IEEE TED (2020)

Abstract: A novel microdetector array (MDA) for monitoring electron beam (eBeam) and extreme ultraviolet (EUV) lithography processes in 5 nm and beyond FinFET technology is first-time presented. This on-wafer detector array consists of high-density sensing cells which are fully compatible with standard FinFET CMOS processes. Fin coupling structures and energy-sensing pads are first applied in an ultrasmall detector for realizing efficient eBeam and EUV photon detection. In advanced lithography process, eBeam or EUV level projected on the wafer can be precisely recorded on the on-wafer MDA without power or batteries. The distributions and variations on the beam intensities collected by MDA can be electrically measured in real time or inline through wafer level test after eBeam or EUV exposures. The proposed MDA is expected to provide real-time feedback for the optimization and stable maintenance of advanced photolithography processed critical to the development nanometer CMOS technologies.

FIG: (a) Schematic of lithography system and (b) 3-D illustration of unit detector cell of the MDA consisting of ESP and FG on the shallow trench isolation (STI) region.

Acknowledgment: The authors gratefully acknowledge the contributions of Taiwan Semiconductor Manufacturing Company (TSMC) and Ministry of Science and Technology (MOST), Taiwan (Project Number: MOST 108-2622-8-007-017).

[paper] Device Scaling for 3-nm Node and Beyond

Opportunities in Device Scaling for 3-nm Node and Beyond:

FinFET Versus GAA-FET Versus UFET

U. K. Das and T. K. Bhattacharyya

in IEEE TED, vol. 67, no. 6, pp. 2633-2638, June 2020, 

doi: 10.1109/TED.2020.2987139

Abstract: The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet, and U-shaped FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To accommodate a contacted gate pitch (CGP) of 32 nm and below, the gate length is scaled down to 14 nm and beyond. While going from 5-nm node (N5) to 3-nm node (N3) dimensions, the GAA-lateral nanosheet (LNS) shows 8% reduction in the effective drain current (I_eff) due to an enormous rise in short channel effects, such as subthreshold slope (SS) and drain-induced barrier lowering (DIBL). On the other hand, 5-nm diameter-based lateral nanowire shows an 80% rise in I_eff. Therefore, to enable future devices, we explored electrostatics and I_eff in FinFET, GAA-FET, and UFET architectures at a scaled dimension. The performances of both Si- and SiGe-based transistors are compared using an advanced TCAD device simulator.

Fig: Transistor architectures for future technologies. (a) FinFET device

(in {001} substrate plane, and sidewalls are in {110} planes) with crosssectional

fin channel (5 nm thin). (b) Fin is changed into a four-stacked

GAA-LNWs. (c) GAA- LNS having 20-nm width (W). (d) UFET structure.

Acknowledgment: The authors would like to thank Dr. Bidhan Pramanik, IIT Goa, India, Dr. KB Jinesh, IIST, Trivandrum, India, and Dr. Geert Eneman, IMEC, Leuven, Belgium, for their valuable technical support.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9078841&isnumber=9098120

[paper] Electrical characterization of advanced MOSFETs

Valeriya Kilchytska, Sergej Makovejev, Babak Kazemi Esfeh, Lucas Nyssens, Arka Halder,

Jean-Pierre Raskin and Denis Flandre

Electrical characterization of advanced MOSFETs towards analog and RF applications

IEEE LAEDC, San Jose, Costa Rica, 2020, 

doi: 10.1109/LAEDC49063.2020.9073536

Abstract - This invited paper reviews main approaches in the electrical characterization of advanced MOSFETs towards their target analog and RF applications. Advantages and necessity of those techniques will be demonstrated on different study cases of various advanced MOSFETs, such as FDSOI, FinFET, NW in a wide temperature range, based on our original research over the last years. 

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9073536&isnumber=9072949

Acknowledgements - This work was partially funded by Eniac “Places2Be”, Ecsel “Waytogofast”, FNRS - FRFC “Towards Highly-efficient 10 nm MOSFETs”, FP7 “Nanosil” and “Nanofunction” projects. The authors thank our colleagues from CEA-Leti, ST and Imec, and particularly, F. Andrieu, O. Faynot, T. Poiroux, S. Barraud, M. Haond, N. Planes, N. Collaert, C. Claeys, M. Jurczak, B. Parvais, R. Rooyackers, for providing UTBB FD SOI, NW and FinFET devices and valuable discussions.

[paper] III-V Channel Double Gate FETs

Compact Modeling of Charge, Capacitance, and Drain Current
in III-V Channel Double Gate FETs

C. Yadav; M. Agrawal; A. Agarwal; Y. S. Chauhan

in IEEE Transactions on Nanotechnology , vol.PP, no.99, pp.1-1
doi: 10.1109/TNANO.2017.2669092

Abstract: In this paper, we present a surface potential based compact modeling of terminal charge, terminal capacitance, and drain current for III-V channel double gate field effect transistor (DGFET) including the effect of conduction band nonparabolicity. The proposed model is developed accounting for the 2-D density of states and includes the effect of quantum capacitance associated with the low density of states channel material. In addition, model incorporates contribution of the first two subbands and efficiently captures the step like behavior appearing in the gate capacitance and trans-conductance with population of the higher sub-bands. The behavior of bias dependent terminal capacitances and drain current are verified with the numerical simulation data of InGaAs channel DGFET and shows a close agreement with the simulation data [read more...]