[Short Course] Modeling and Simulation of Nano-Transistors

Short Course

Modeling and Simulation of Nano-Transistors

6 - 10 July 2020 at Outreach Auditorium,IIT Kanpur

http://www.iitk.ac.in/nanolab/sc2020/

by Prof. Yogesh S. Chauhan

Nanolab, IIT Kanpur

http://home.iitk.ac.in/~chauhan/

Aim: VLSI design will soon use transistors whose size will be as small as 10nm. The aim of this short course is to educate and train bright minds on different aspects of Nano-transistors. Modeling especially compact modeling is the heart of circuit simulation. TCAD simulations are used for early device design and to understand the internal physics of transistor. Electrical characterization includes current and capacitance voltage measurement of transistor. RF measurement is an exciting area which involves understanding of devices as well as high frequency effects. This short course will cover various topics in modeling, simulation and characterization of transistors especially at nanoscale.

Topics: (1) VLSI design and Nanoelectronics, (2) Physics and Operation of MOSFET, (3) SPICE and Circuit simulation, (4) TCAD simulation: Theory and demonstration, (5) Compact Modeling: Theory and demonstration, (6) Scaling and Moore's Law, (7) Nano-Transistors: FinFET, FDSOI, Negative Capacitance FET, Nanosheet FETs, 2D-FETs etc. (8) Characterization: Current and capacitance measurement, (9) RF CMOS and GaN High Electron Mobility Transistors

Hands-on Sessions: (1) Verilog-A coding, (2) SPICE ckt. Simulation, (3) TCAD Simulation, (4) Parameter Extraction

Coordinator: Prof. Yogesh S. Chauhan Dept. of Electrical Engg., IIT Kanpur

Registration: This short course has been postponed to end of this year or early next year due to ongoing pandemic. New Dates will be announced once normalcy returns in the country.

[paper] Nanoscale MOSFET Modeling

 Nanoscale MOSFET Modeling: 
Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits

C. Enz, F. Chicco and A. Pezzotta

in IEEE Solid-State Circuits Magazine, vol. 9, no. 3, pp. 26-35, Summer 2017

doi: 10.1109/MSSC.2017.2712318

Abstract: This article presents the simplified charge-based Enz-Krummenacher-Vittoz (EKV) [11] metal-oxide-semiconductor field-effect transistor (MOSFET) model and shows that it can be used for advanced complementary metal-oxide-semiconductor (CMOS) processes despite its very few parameters. The concept of an inversion coefficient (IC) is first introduced as an essential design parameter that replaces the overdrive voltage V_G-V_T0 and spans the entire range of operating points from weak via moderate to strong inversion (SI), including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40- and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation, valid from weak to SI and requiring only the VS parameter mc, is described. The normalized transconductance efficiency G_m/I_D, which is a key figure-of-merit (FoM) for the design of low-power analog circuits, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to SI with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance G_ds/I_D follows a similar dependence with IC than the normalized G_m/I_D characteristic but with different parameters accounting for drain induced barrier lowering (DIBL). The methodology for extracting the few parameters from the measured I_D-V_G and I_D-V_D characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted silicon on insulator (FDSOI) and Fin-FET 28-nm processes [read more...]

FIG: The simplified EKV model applied to a 28-nm FDSOI CMOS process: 

G_m n U_T / I_D versus IC for three different transistor channel lengths

References

[1] A. Bahai, “Ultra-low energy systems: Analog to information,” in Proc. European Solid-State Circ. Conf., Sept. 2016, pp. 3–6.

[2] D. Binkley, Tradeoffs and Optimization in Analog CMOS Design. Hoboken, NJ: Wiley, 2008.

[3] W. Sansen, Analog Design Essentials. New York: Springer-Verlag, 2006.

[4] A. Mangla, M. A. Chalkiadaki, F. Fadhuile, T. Taris, Y. Deval, and C. C. Enz, “Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model,” Microelectr. J., vol. 44, no. 7, pp. 570–575, July 2013.

[5] Y. S. Chauhan, S. Venugopalan, M. A. Chalkiadaki, M. A. U. Karim, H. Agarwal, S. Khandelwal, N. Paydavosi, J. P. Duarte, C. C. Enz, A. M. Niknejad, and C. Hu, “BSIM6: Analog and RF compact model for bulk MOSFET,” IEEE Trans. Electron Dev., vol. 61, no. 2, pp. 234–244, Feb. 2014.

[6] C. Enz, M. A. Chalkiadaki, and A. Mangla, “Low-power analog/RF circuit design based on the inversion coefficient,” in Proc. European Solid-State Circ. Conf., Sept. 2015, pp. 202–208.

[7] C. Enz and A. Pezzotta, “Nanoscale MOSFET modeling for the design of low-power analog and RF circuits,” in Proc. Int. Conf. MIXDES, June 2016, pp. 21–26.

[8] W. Sansen, “Analog CMOS from 5 micrometer to 5 nanometer,” in Proc. IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers, Feb. 2015, pp. 1–6.

[9] W. Sansen, “Analog design procedures for channel lengths down to 20 nm,” in Proc. IEEE 20th Int. Conf. Electronics, Circuits, and Systems, Dec. 2013, pp. 337–340.

[10] C. C. Enz and E. A. Vittoz, Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design. Hoboken, NJ: Wiley, 2006.

[11] C. C. Enz, F. Krummenacher, and E. A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications,” Analog Integr. Circuits Signal Process. J., vol. 8, pp. 83–114, July 1995.

[12] P. Heim, S. R. Schultz, and M. A. Jabri, “Technology-independent biasing technique for CMOS analogue micropower implementations of neural networks,” in Proc. Sixth Australian Conf. Neural Networks, Sydney, Australia, 1995, pp. 9–12.

[13] C. C. Enz and E. A. Vittoz, “CMOS low-power analog circuit design,” in EmergingTechnologies: Designing Low Power Digital Systems, R. Cavin and W. Liu, Eds. Piscataway, NJ: IEEE, 1996, pp. 79–133.

[14] E. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operations,” IEEE J. Solid-State Circuits, vol. 12, no. 3, pp. 224–231, June 1977.

[15] A. Mangla, C. C. Enz, and J. M. Sallese, “Figure-of-merit for optimizing the current efficiency of low-power RF circuits,” in Proc. Int. Conf. Mixed Design Integrated Circuits and Systems, June 2011, pp. 85–89.

[16] A. Mangla, “Modeling nanoscale quasi-ballistic MOS transistors,” Ph.D. dissertation, EPFL, Switzerland, Dissertation No. 6385, 2014.

[17] R. R. Troutman and A. G. Fortino, “Simple model for threshold voltage in a short- channel IGFET,” IEEE Trans. Electron. Dev., vol. 24, no. 10, pp. 1266–1268, Oct. 1977.

[18] N. Arora, MOSFET Models for VLSI Circuit Simulation. New York: Springer-Verlag, 1993.

[19] Z. H. Liu, C. Hu, J. H. Huang, T. Y. Chan, M. C. Jeng, P. K. Ko, and Y. C. Cheng, “Threshold voltage model for deep submicrometer MOSFETs,” IEEE Trans. Electron Dev., vol. 40, no. 1, pp. 86–95, Jan. 1993.

[20] M. A. Chalkiadaki, “Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design,” Ph.D. dissertation, EPFL, Switzerland, Dissertation No. 7030, 2016.

National Workshop on Advanced Nanoscale Device Design Using TCAD

The National Workshop on Advanced Nanoscale Device Design Using Technology Computer-Aided Design (TCAD) was organized by the IEEE SolidState Circuits Society (SSCS) College of Engineering Chengannur, India Chapter. The workshop was held 28 December 2015 through 1 January 2016 as a three-day tutorial and two-day handson session. The event was graced with the presence of distinguished lecturers from top institutions in India, including Prof. Yogesh S. Chouhan from IIT Kanpur delivering the keynote talk. The workshop attracted approximately 150 participants from 15 reputable academic institutions. People from industry and also attended the event.

The coordinators were proud to present a successful workshop as one of the first events since the formation of the Chapter. The event was funded by the SSCS extra subsidy program. The feedback received from the attendees was very positive. Each participant received a certificate during the closing ceremony of the event. The five-day workshop came to an end by the heartfelt vote of thanks by Nisha Kuruvilla, with a motto “This is just the beginning.” [read more...]