[C4P] T-ED Special Issue

Call for Papers - Special Issue on "Wide and Ultrawide Band Gap Semiconductor Devices for RF and Power Applications."

The Special Issue of the IEEE Transactions on Electron Devices (T-ED) will report the most advanced and recent results in the field of wide and ultrawide bandgap semiconductor materials and devices, including papers focused on material fabrication, device processing, reliability investigation, device modeling, thermal aspects, and system-related results.

Submission deadline: 31 August 2023
Publication date: February 2024

Submit papers today: https://bit.ly/3fESTgZ

Guest Editors: 

Prof. Matteo Meneghini, University of Padova, Italy 

Prof. Patrick Fay, University of Notre Dame, USA 

Prof. Digbijoy Nath, IISC Bangalore 

Prof. Geok Ing Ng, Nanyang Technical University, Singapore 

Prof. Junxia Shi, University of Illinois, Chicago 

Prof. Shyh-Chiang Shen, Georgia Tech. 

[webinar] Power WBG Semiconductor Technology Opportunities

"Power WBG Semiconductor Technology Opportunities"

webinar hosted by 

Dr. Victor Veliadis, 

Executive Director and CTO of PowerAmerica, 

a WBG semiconductor power electronics consortium

Event by Łukasiewicz - Institute of Microelectronics and Photonics

Register now: https://lukasiewiczimif.clickmeeting.com/poweramerica/register

Silicon power devices have dominated power electronics due to their excellent starting material quality, ease of fabrication, low-cost volume production, and proven reliability. However, they’re approaching their operational limits primarily due to their relatively low bandgap and critical electric field that results in high conduction and switching losses, and poor high-temperature performance. So what can we do? Well, let’s talk about the favorable WBG material properties, their volume application opportunities, and last but not least let's highlight the respective competitive advantages of SiC and GaN.

You will additionally learn about:

• the lateral and vertical power device configurations that will be analyzed in the context of bidirectional switching
• specific applications and needs for bidirectional switches
• key topologies, enabled by bidirectional switches
• PowerAmerica’s work to accelerate WBG power electronics commercialization

About Dr. Veliadis: Dr. Victor Veliadis is Executive Director and CTO of PowerAmerica, a WBG semiconductor power electronics consortium. At PowerAmerica, he has managed a budget of $146 million that he strategically allocated to 200 industrial and University projects to accelerate WBG semiconductor clean energy manufacturing, workforce development, and job creation. His PowerAmerica educational activities have trained 410 University FTE students in applied WBG projects, and engaged 4100 attendees in tutorials, short courses, and webinars. Dr. Veliadis is an ECE Professor at NCSU and an IEEE Fellow and EDS Distinguished Lecturer. He has 27 issued U.S. patents, 6 book chapters, and over 125 peer-reviewed publications. Prior to entering academia and taking an executive position at Power America in 2016, Dr. Veliadis spent 21 years in the semiconductor industry where his work included design, fabrication, and testing of SiC devices, GaN devices for military radar amplifiers, and financial and operations management of a commercial semiconductor fab. He has a Ph.D. degree in Electrical Engineering from John Hopkins University (1995).

[paper] Modeling of SIC VDMOS FET

Anirban Kar∗, Ahtisham Pampori∗, Noriyoshi Hashimoto† and Yogesh Singh Chauhan∗

A Charge-Based Silicon Carbide MOSFET Compact Model for Power Electronics Applications

2021 IEEE 8th Uttar Pradesh Section UPCON)

DOI: 10.1109/UPCON52273.2021.9667643

∗Department of Electrical Engineering, IIT Kanpur (IN)
†Keysight Technologies (J)

Abstract: This paper presents a charge-based compact model for Silicon Carbide (SiC) power MOSFETs, which captures the static characteristics of the device over a wide range of voltages and currents. The drift region resistance and charges in the channel have been formulated to calculate the drain current in a self-consistent manner. The proposed model has been validated against the measured transfer and output characteristics of a commercial 1.2kV power MOSFET (Infineon IMW120R045M1) with a maximum current rating of 52A.

Fig: a) Transfer characteristics of SiC MOSFET with Vd=1 to 20V

b) Transconductance of SiC MOSFET with Vd=1 to 20V 

Acknowledgement: This work was supported in part by the Swarna Jayanti Fellowship under Grant DST/SJF/ETA02/2017-18 and in part by the Department of Science and Technology through the FIST Scheme under Grant SR/FST/ETII-072/2016 and Keysight Technologies, USA. The measurement of the device was carried out at Keysight Technologies, Japan.

[paper] Compact Model for SiC Power MOSFETs

Cristino Salcines¹, Sourabh Khandelwal² and Ingmar Kallfass¹ 

A Compact Model for SiC Power MOSFETs 

for Large Current and High Voltage Operation Conditions 

(2021) arXiv-2104. 

1 University of Stuttgart Stuttgart, Germany

2 Macquarie University Sydney, Australia  

Abstract: This work presents a physics based compact model for SiC power MOSFETs that accurately describes the I-V characteristics up to large voltages and currents. Charge-based formulations accounting for the different physics of SiC power MOSFETs are presented. The formulations account for the effect of the large SiC/SiO2 interface traps density characteristic of SiC MOSFETs and its dependence with temperature. The modeling of interface charge density is found to be necessary to describe the electrostatics of SiC power MOSFETs when operating at simultaneous high current and high voltage regions. The proposed compact model accurately fits the measurement data extracted of a 160 milli ohms, 1200V SiC power MOSFET in the complete IV plane from drain-voltage Vd = 5mV up to 800 V and current ranges from few mA to 30 A.

Fig: Output characteristics up to high current and high voltage in logarithmic scale for VGS = 6V to 20V in steps of 0.5V. Symbols are measurements and solid lines simulations of the proposed model. The logarithmic scale eases the visualization of both low and high VDS voltages in a single graph.

[Si2 CMC] to Standardize SPICE Model for SiC MOSFET

May 03, 2021 // By Peter Clarke [eenewsanalog.com] 

The Compact Model Coalition (CMC) working group of the Silicon Integration Initiative (SI2) has agreed to standardize a model for the behaviour of a silicon-carbide MOSFET.

Silicon-carbide offers higher efficiency and faster operation than silicon and has been adopted for several power applications including photovoltaic inverters and converters, industrial motor drives, electric vehicle powertrain and EV charging, and power supply and distribution. A CMC working group will oversee the model development with Analog Devices, Cadence Design Systems, Infineon, Qualcomm, Siemens EDA, Silvaco and Synopsys set to participate.

"I'd encourage companies with a stake in silicon-carbide devices to join this effort and help guide selection of the model which best represents their intended use," 

advised Peter Lee, chair of the CMC.

Now in its 25th year, the Si2 Compact Model Coalition provides semiconductor manufacturers, designers, and simulation tool providers a means to pool resources to fund standardization and optimization of standard compact SPICE models and standard interfaces to promote simulation tool interoperability [Read more...]

[C4P] ISPS 2021 Prague, August 25–27, 2021

 15th INTERNATIONAL SEMINAR ON POWER SEMICONDUCTORS

ISPS 2021

Prague, 25 August – 27 August 2021

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Organised by	IET Czech Network in co-operation with the IEEE Czechoslovakia Section
Co-sponsored by	Faculty of Electrical Engineering, Department of Electrotechnology, Czech Technical University in Prague
Technical sponsor	ECPE European Center for Power Electronics e.V.
Conference website	http://technology.fel.cvut.cz/ISPS2021

BACKGROUND

The 15th International Seminar on Power Semiconductors (ISPS 2021) provides a forum for technical discussion in the area of power semiconductor devices and their applications. It is a small conference with the special flair of an atmosphere of searching deeper insight and intensive discussion.

AREAS OF INTEREST

• Power semiconductor devices (materials, physics, modelling, technology, diagnostics)
• Packaging, advanced device applications, reliability

Papers oriented in the field of power semiconductors are supposed to be presented in sessions on

• Device Physics and Technology
• Power Bipolar Devices
• Voltage-Controlled Power Devices
• Wide Bandgap Power Devices
• Power Integration
• Advanced Applications
• Packaging, Reliability & Modelling.

A round table discussion oriented on topical problems of research and education in the field of power semiconductors will be organised in the framework of the seminar.

PAPER SUBMISSION

A summary of 300–500 words (maximum two pages including figures and tables) is required for review. It should be uploaded in electronic format (.doc or .pdf files) to the ISPS 2021 easychair conference system:

http://easychair.org/conferences/?conf=isps2021

before April 30, 2021.

PUBLICATION

Presented papers will be published in the seminar proceedings, which will be distributed at the seminar registration. We are delighted to announce that the best papers presented at the conference will be invited for consideration in a special issue of the IET Power Electronics Journal dedicated to the ISPS 2021 seminar.

ORGANISING COMMITTEE

Chairman:	Prof Vítězslav Benda, FIET
Members:	Dr Vítězslav Jeřábek, MIET
	Dr Martin Molhanec
	Dr Ladislava Černá, MIET
	Dr Pavel Hrzina

[paper] Predictive Hot-Carrier Aging Compact Model

Y. Xiang^1,2, S. Tyaginov^1,3,4, M. Vandemaele^1,2, Z. Wu^1,2, J. Franco¹, E. Bury¹, B. Truijen¹, B.Parvais^1,5, D. Linten¹, B. Kaczer¹

A BSIM-Based Predictive Hot-Carrier Aging Compact Model 

4A.4; IRPS March 21- 24 2021 

¹imec, Leuven (B)
²Department of Electrical Engineering (ESAT), KU Leuven, Leuven (B)
³Institute for Microelectronics (IuE), TU Wien, Vienna (A)
⁴Ioffe Physical-Technical Institute of the Russian Academy of Sciences, Saint Petersburg (RU) 
⁵Department of Electronics and Informatics (ETRO/VUB), Brussels (B)

Abstract: The continued challenge of front-end-of-line transistor reliability has long demanded physics-based SPICE compact models, not only for service lifetime estimation, but also for agingaware device pathfinding with technology scaling and innovation. Here, we present a predictive hot-carrier-degradation (HCD) compact model built upon the industry-standard BSIM model, that conveniently embeds the essential HCD physics within common SPICE simulation flows. We leverage and augment the established, scalable electrostatics and transport in BSIM as the input to an analytical HCD interface states generation formalism, the result of which is in turn injected back into BSIM for a selfconsistent estimation of the threshold voltage (VTH) shift and the mobility degradation. Our approach readily exhibits fundamental, non-empirical predictabilities of the stress timeand the sensing bias- dependency of transistor-level degradation, without having to resort to a priori assumptions. This will further accommodate the irregular, arbitrary voltage waveforms in transient circuit operations, thus enabling efficient evaluation of the power-performance degradation at circuit level. The model ultimately aims to lay the groundwork for a reliability-aware design-technology co-optimization in device pathfinding. 

Fig: Schematic of the Pao-Sah DD current integral method used in commercial CMs [a-e] and the extrapolated piecewise Vch(y) by augmenting the BSIM model. In the Pao-Sah DD formalism, the actual Ids is calculated by the difference of the integral Ξ at the source (channel potential Vch=0) and at the “drift-diffusion limit” (at LDD, where channel potential Vch=VDS,eff), with the latter defined by velocity saturation or pinch-off. The Vch(y) is extrapolated by using the implicit assumptions in BSIM-BULK: the quadratic profile under gradual channel approximation (GCA) and the hyperbolic profile under the drain-side field assumption used in substratecurrent body-effect (SCBE). 

References:

[a] C. K. Dabhi. (2017). BSIM4 4.8.1 MOSFET Model: User’s Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsim4/.

[b] H. Agarwal. (2017). BSIM-BULK106.2.0 MOSFET Compact Model: Technical Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsimbulk/. 

[c] S. Khandelwal. (2015). BSIM-CMG 110.0.0 Multi-Gate MOSFET Compact Model: Technical Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsimcmg/. 

[d] P. Kushwaha. (2017). BSIM-IMG 102.9.1 Independent Multi-Gate MOSFET Compact Model: Technical Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsimimg/. 

[e] W. Grabinski et al., (2019) "FOSS EKV2.6 Verilog-A Compact MOSFET Model," ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), Cracow, Poland, 2019, pp. 190-193, doi: 10.1109/ESSDERC.2019.8901822

[Online] Available: https://github.com/ekv26/model

[paper] Compact Model for Power MOSFET

Abdelghafour Galadi

PSPICE compact model for power MOSFET based on manufacturer datasheet

DOI:10.1088/1757-899X/948/1/012007

National School of Applied Sciences of Safi, Cadi Ayyad University, Marrakech (MA)

Abstract: In this paper, large signal model for power MOSFET devices is presented. The proposed model includes quasi-saturation effect and describes accurately the electrical behavior of the power MOSFET devices. The large signal model elements will be provided based on the device structure. Furthermore, the model parameters are extracted from measurements considering the voltages depending effect of the nonlinear gate-source, gate-drain and drain-source interelectrode capacitances. Excellent agreements will be shown between the simulated and the datasheet data. Finally, a description of the model will be provided along with the parameter extraction procedure.

Fig: a) Conventional power MOSFET structure with b) its subcircuit elements. 

[slides] (Ultra-) Wide-Bandgap Devices

(Ultra-) Wide-Bandgap Devices: Reshaping the Power Electronics Landscape

Presenter Dr. Yuhao Zhang, Assistant Professor,
Center for Power Electronics Systems, Virginia Tech

IEEE EDS SCV-SF Seminar 

Friday, June 12, 2020 at 12PM – 1PM PDT

Abstract: Power electronics is the application of solid-state electronics for the control and processing of electrical energy. It is used ubiquitously in consumer electronics, electric vehicles, data centers, renewable energy systems, and smart grid. The power semiconductor device, as the cornerstone technology in power electronics, is key to improving the efficiency, cost and form factor of power electronic systems.  Recently, the power electronics landscape has been significantly reshaped with the production and application of power devices based on wide-bandgap (WBG) semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC). Besides advancing the performance of traditional power systems, WBG devices have also enabled many emerging applications that are beyond the realm of silicon (Si) as well as changed the manufacturing paradigm of power electronics. On the horizon is the power devices based on ultra-wide-bandgap (UWBG) materials, which promises superior performance over GaN and SiC and is at the relatively early stage of research development.  This talk will provide a comprehensive overview of major WBG and UWBG power device technologies, spanning materials, devices, reliability and applications. Some research projects in the PI’s group in collaboration with industry will also be introduced.

FIG: WBG Semiconductor: Superior Power Semiconductor Over Si

The seminar presentation is now available on our IEEE EDS SCV-SF webpage:
http://site.ieee.org/scv-eds/files/2020/06/SCV_SF_EDS_Yuhao_Zhang_excerpt.pdf

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page. Subscribe or Invite your friends to sign up for our mailing list and get to hear about exciting electron-device relevant talks. We, EDS SCV-SF, promise no spam and try to minimize email. You can (un)subscribe easily.

Book Performance Report 2017/18

(as of April 2018)

POWER/HVMOS Devices Compact Modeling
Editors: Grabinski, Wladyslaw, Gneiting, Thomas (Eds.)
ISBN 978-90-481-3046-7 (ebook)
ISBN 978-90-481-3045-0 (print book)

Availability of and results for eBook Since its online publication on February 25, 2010, there has been a total of 5,796 chapter downloads for eBook on SpringerLink. The table to the right shows the download figures for the last year(s). In addition to the collections, Springer eBooks are available for individual use from our web shop. The book can be ordered/downloaded directly from its home page.  MyCopy: book is available as a MyCopy version, which is a unique service that allows library patrons to order a personal, printed-on-demand softcover edition of an eBook for just $/€24.99.  To further widen the distribution of eBook, it has also been made available in the following shop(s): Amazon Kindle Shop Apple iTunes Google play eBooks reach a broad readership and provide global visibility for the book. Spreading the word about the book To present the book POWER/ HVMOS Devices Compact Modeling to its potential readers and make it findable by search engines, it has its own home page, which can be shared through social media and where you can download a flyer for the book! In 2017 this page was visited 112 times.  The book has been announced by the New Book Alert, our largest customer emailing.  Journal editors, journalists or bloggers can request a free Online Review Copy of the book from its home page. This online service makes it especially easy for them to write a review. All potencial, reviews can be an excellent way to boost a book’s visibility in the relevant communities and raise reader interest!

Year Chapter Downloads 2017 766 2016 843 2015 912 2014 1,333 2013 658 2012 420 2011 401 2010 463

[paper] Compact electro-thermal modeling of a SiC MOSFET power module under short-circuit conditions

Proceedings of 43rd Annual Conference of the IEEE Industrial Electronics Society

IECON 2017

Lorenzo Ceccarelli, Paula Diaz Reigosa, Amir Sajjad Bahman, Francesco Iannuzzo,

Frede Blaabjerg

Center of Reliable Power Electronics, Department of Energy Technology Aalborg University,

Pontoppidanstræde 101

9220 Aalborg, Denmark 

ABSTRACT: A novel physics-based, electro-thermal model which is capable of estimating accurately the short-circuit behavior and thermal instabilities of silicon carbide MOSFET multi-chip power modules is proposed in this paper. The model has been implemented in PSpice and describes the internal structure of the module, including stray elements in the multi-chip layout, self-heating effect, drain leakage current and threshold voltage mismatch. A lumped-parameter thermal network is extracted in order to estimate the internal temperature of the chips. The case study is a half-bridge power module from CREE with 1.2 kV breakdown voltage and about 300 A rated current. The short-circuit behavior of the module is investigated experimentally through a non-destructive test setup and the model is validated. The estimation of overcurrent and temperature distribution among the chips can provide useful information for the reliability assessment and fault-mode analysis of a new-generation SiC high-power modules [read more...]

Fig.: SiC MOSFET model structure.