[paper] ACM3 Compact MOSFET Model

Deni Germano Alves Neto; Márcio Cherem Schneider; Manuel J. Barragan; 

Sylvain Bourdel; Carlos Galup-Montoro,

ACM3 - An Advanced Compact MOSFET Model for Analog IC Design and Simulation

in IEEE Access, DOI: 10.1109/ACCESS.2026.3742180

1.) Federal University of Santa Catarina, 88040-900 Florianópolis (BR)

2.) Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA F-38000 Grenoble (F)

Abstract: This paper presents ACM3, an advanced compact MOSFET model that extends the designoriented ACM2 formulation by introducing gate-voltage dependencies for the slope factor n, the draininduced barrier lowering (DIBL) coefficient σ, and inversion charge dependence for the specific current IS. ACM3 preserves a single-piece, charge-based description of the drain current, valid from weak to strong inversion and from the linear to the saturation regions, while relying on an efficient analytical approximation of the Lambert W -function suitable for Verilog-A implementation. A robust yet straightforward parameterextraction flow is proposed, in which all eight DC parameters (VT 0, IS0, Φ, γ, θ, σWI , σSI and ζ) are obtained directly from ID–VGB and ID–VDS curves through a differential evolution (DE) algorithm that minimizes the root-mean-square percentage error between the reference and the modeled drain current. A distinctive feature of this flow is that the reference curves may originate either from silicon measurements or from another compact model, making the extraction equally applicable to measured and simulated data. At the device level, the parameters are extracted from silicon measurements of an open-source 130 nm BiCMOS technology, yielding agreement with the measured data for both short- and long-channel transistors across all regions of operation. At the circuit level, ACM3 is validated through simulations of a common-source amplifier, a self-biased current source, and a CMOS latch in a 180 nm CMOS technology, where the ACM3 parameters are extracted from BSIM4-generated characteristics and the results are compared against the foundry BSIM4 model. Representative process, voltage, and temperature (PVT) robustness is also evaluated against BSIM4. The ACM3 model has been implemented in Verilog-A and integrated into open-source circuit simulators, via OpenVAF, enabling accurate and intuitive analog IC design within fully open design flows.

TAB: Comparison of ACM3 with representative industrial 

and design-oriented compact MOSFET models

Aknowlegements: This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior, (BRAZIL), Conselho Nacional de Desenvolvimento Científico e Tecnológico, (BRAZIL), and TIMA laboratory, Grenoble (FRANCE).

[paper] Symmetric BSIM-SOI

Chetan Kumar Dabhi, Dinesh Rajasekharan, Girish Pahwa, Debashish Nandi, Naveen Karumuri, Sreenidhi Turuvekere, Anupam Dutta, Balaji Swaminathan, Srikanth Srihari, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu

Symmetric BSIM-SOI: A Compact Model for Dynamically Depleted SOI MOSFETs 

 in IEEE TED (2024)

Part I DOI: 10.1109/TED.2024.3363110

Part II DOI: 10.1109/TED.2024.3363117

1 Department of Electrical Engineering and Computer Sciences, UCB, CA, USA

2 Department of Electrical Engineering, IIT Kanpur, India

3 GlobalFoundries, Bengaluru, India

Abstract: In this article, we present a symmetric surface-potential-based model for dynamic depletion (DD) device operation of silicon-on-insulator (SOI) FETs for RF and analog IC design applications. The model accurately captures the device behavior in partial depletion (PD) and full depletion (FD) modes, as well as in the transition from PD to FD, based on device geometry, doping, and bias conditions. The model also exhibits an excellent source–drain symmetry during dc and small-signal simulations, resulting in error-free higher order harmonics. The model is fully scalable with bias, temperature, and geometry and has been validated extensively with real device data from the industry. The symmetric BSIM-SOI model is developed in Verilog-A and compatible with all commercial SPICE simulators.

FIG: (a) Schematic of a typical SOI MOSFET

(b) Cgg versus Vgb for different substrate bias, with the PD-to-FD transition 

Acknowledgment: The authors thanks the members of the Compact Model Coalition (CMC), particularly Geoffrey J. Coram and Jushan Xie, for testing the model and suggesting improvements. The authors appreciate the CMC QA team’s efforts in conducting a model quality check. Caixia Han and Xiao Sun from Cadence provided a few useful test cases. They thank Ananth Sundaram and Anamika Singh Pratiyush from GlobalFoundries India for the help and discussion regarding DDSOI model intricacies and development. Model code is available at BSIM Website <https://bsim.berkeley.edu/models/bsimsoi/>

[paper] Automatic Parameter Extraction of MOSFET Compact Models

Gazmend Alia^1,2, Andi Buzo¹, Hannes Maier-Flaig¹, Klaus-Willi Pieper¹, 

Linus Maurer²  and Georg Pelz¹

Automatic Parameter Extraction of MOSFET Compact Models using Differential Evolution with Population Prediction (DEpred)

6th EDTM; March 6 to 9, 2022 

   
1 Infineon Technologies AG, Munich (D)
2 Bundeswehr University Munich (D)

Abstract: Parameter extraction of MOSFET compact models with hundreds of parameters is not a trivial task. Differential evolution (DE) has proven to be very effective in such highly dimensional parameter spaces. However, DE needs a large number of iterations to converge. This paper proposes a novel method to accelerate the convergence of DE by predicting tens of iterations ahead where the population will be, based on the knowledge from the already finished iterations. The method is validated with BSIM4 and HiSIM-HV compact models, where up to 50% of the iterations are saved.

Fig: DE vs DEpred cost function for BSIM4 and HiSIM-HV models.
DEpred reaches the target 50% faster.

[paper] Predictive Hot-Carrier Aging Compact Model

Y. Xiang^1,2, S. Tyaginov^1,3,4, M. Vandemaele^1,2, Z. Wu^1,2, J. Franco¹, E. Bury¹, B. Truijen¹, B.Parvais^1,5, D. Linten¹, B. Kaczer¹

A BSIM-Based Predictive Hot-Carrier Aging Compact Model 

4A.4; IRPS March 21- 24 2021 

¹imec, Leuven (B)
²Department of Electrical Engineering (ESAT), KU Leuven, Leuven (B)
³Institute for Microelectronics (IuE), TU Wien, Vienna (A)
⁴Ioffe Physical-Technical Institute of the Russian Academy of Sciences, Saint Petersburg (RU) 
⁵Department of Electronics and Informatics (ETRO/VUB), Brussels (B)

Abstract: The continued challenge of front-end-of-line transistor reliability has long demanded physics-based SPICE compact models, not only for service lifetime estimation, but also for agingaware device pathfinding with technology scaling and innovation. Here, we present a predictive hot-carrier-degradation (HCD) compact model built upon the industry-standard BSIM model, that conveniently embeds the essential HCD physics within common SPICE simulation flows. We leverage and augment the established, scalable electrostatics and transport in BSIM as the input to an analytical HCD interface states generation formalism, the result of which is in turn injected back into BSIM for a selfconsistent estimation of the threshold voltage (VTH) shift and the mobility degradation. Our approach readily exhibits fundamental, non-empirical predictabilities of the stress timeand the sensing bias- dependency of transistor-level degradation, without having to resort to a priori assumptions. This will further accommodate the irregular, arbitrary voltage waveforms in transient circuit operations, thus enabling efficient evaluation of the power-performance degradation at circuit level. The model ultimately aims to lay the groundwork for a reliability-aware design-technology co-optimization in device pathfinding. 

Fig: Schematic of the Pao-Sah DD current integral method used in commercial CMs [a-e] and the extrapolated piecewise Vch(y) by augmenting the BSIM model. In the Pao-Sah DD formalism, the actual Ids is calculated by the difference of the integral Ξ at the source (channel potential Vch=0) and at the “drift-diffusion limit” (at LDD, where channel potential Vch=VDS,eff), with the latter defined by velocity saturation or pinch-off. The Vch(y) is extrapolated by using the implicit assumptions in BSIM-BULK: the quadratic profile under gradual channel approximation (GCA) and the hyperbolic profile under the drain-side field assumption used in substratecurrent body-effect (SCBE). 

References:

[a] C. K. Dabhi. (2017). BSIM4 4.8.1 MOSFET Model: User’s Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsim4/.

[b] H. Agarwal. (2017). BSIM-BULK106.2.0 MOSFET Compact Model: Technical Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsimbulk/. 

[c] S. Khandelwal. (2015). BSIM-CMG 110.0.0 Multi-Gate MOSFET Compact Model: Technical Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsimcmg/. 

[d] P. Kushwaha. (2017). BSIM-IMG 102.9.1 Independent Multi-Gate MOSFET Compact Model: Technical Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsimimg/. 

[e] W. Grabinski et al., (2019) "FOSS EKV2.6 Verilog-A Compact MOSFET Model," ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), Cracow, Poland, 2019, pp. 190-193, doi: 10.1109/ESSDERC.2019.8901822

[Online] Available: https://github.com/ekv26/model

Lynguent Debuts Radiation Hardened By Design, BSIM4 Compact Model Toolkits

Lynguent®, Inc., announced two new toolkits for its ModLyng[tm] Integrated Modeling Environment (IME): Radiation Hardened By Design (RHBD) Toolkit and BSIM4 Compact Model Toolkit. The RHBD Toolkit includes models and tools which provide a modeling and analysis capability for Single Event Upset (SEU) behaviors in deep sub-micro processes. The BSIM4 Compact Model Toolkit includes a high fidelity BSIM4 model which provides more flexibility than has ever been available for adding new effects to existing processes built upon the BSIM foundation. These toolkits, when used with the ModLyng IME, enable semiconductor and systems companies to easily enhance their IC design flows with radiation SEU capability and thus save weeks in qualifying their designs and cell libraries for radiation hardness.

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