- European Semiconductor Design Ecosystem (10 min)
- Matthew Xuereb, European Commission
- Open-Source Semiconductor Ecosystem (15 min)
- Luca Alloatti, Free Silicon Foundation (I) ETS
- Open-Source EDA Software and Semiconductor Design (15 min)
- Jean-Paul Chaput, Sorbonne Université, Coriolis Foundation
- European Roadmap on the Advancement of Open-Source EDA Tools, next steps (15 min)
- Rihards Novickis, Latvian Institute of Electronics and Computer Science
- Q&A session / Feedback (up to 1 hour)
Apr 21, 2024
[webinar] Open Source EDA Development of Chips in Europe
Mar 17, 2024
SSCS April Technical Webinar
- https://zerotoasiccourse.com/
- https://tinytapeout.com
Jan 18, 2024
[paper] Open-source design of integrated circuits
* Institute for Integrated Circuits, Johannes Kepler University Linz, Austria
Acknowledgements: The authors thank Johannes Kepler University for funding the open-access publication, Google and SkyWater Technologies for igniting this recent wave of open-source IC design, and the large crowd of enthusiasts spending their time on developing and maintaining an extensive array of exciting open-source EDA projects. Open access funding provided by Johannes Kepler University, Linz.
Jan 5, 2024
ISHI-kai January 2024 event
ープンソースPDKやEDAの状況について、キーマンに語っていただきます
Schedule
Friday, January 26, 2024, 18:00-21:00 (Reception: 18:30)
Venue (onsite)
Google Shibuya Office
3-21-3 Shibuya, Shibuya-ku, Tokyo
Shibuya Stream Google reception meeting
Online Broadcast:
Google Meet: https://meet.google.com/ksa-tjaw-ges
Participation Fee
free
Time | Speaker | Title | Lecture Outline |
---|---|---|---|
Until 18:30 | ISHI-kai | reception | The entrance to the facility closes at this time, so if you are participating locally, please come by this time as much as possible. |
18:00 ~ 18:30 | ISHI-kai | Chat time | - |
18:30 ~ 19:15 (Lecture: 30min, Q&A: 15min) | Takeshi Hamamoto Minimal Fab Propulsion Organization Device Engineer | minimal Fab open PDK | 1) What is a minimal fab 2) openPDK 3) Design Contest at Semicon 2023 |
19:15 ~ 20:00 (Lecture: 30min., Q&A: 15min.) | Junichi Okamura IEEE Senior Member | OpenPDK and the World | - |
20:00 ~ 20:45 (Lecture: 30min., Q&A: 15min.) | @noritsuna | About the upcoming open source PDK shuttle | (To be released at a later date) |
21:00 | ISHI-kai | closing |
Nov 21, 2023
[webinar] Open Source Silicon Landscape
- Policymakers at the regional, national, and European level who want to strengthen their respective semiconductor ecosystem while collaborating and contributing to the Union’s industry as a whole
- Research and academia representatives who are interested in deepening their knowledge or discovering the potential of the Open Source Silicon landscape
- SMEs in the semiconductor industry who aim to expand and innovate their business by using a cutting-edge approach
- Start-ups that are eager to elevate their business to the next level by embracing vanguard strategies
- Citizen scientists and the general public who would like to have a better understanding of the new horizons in the semiconductor landscape
- Experts active in industrial development who are interested in integrating potential new approaches
The event is free of charge, but registration is mandatory. Registrants will receive the link to access the event by email.
11:00 - 11:05 | Welcome |
11:05 - 11:10 | Introducing Open Source Silicon |
11:10 - 11:20 | BACKGROUND Open source silicon between software and hardware Background |
11:20 - 11:40 | POLICY BRIEF PRESENTATION Open source silicon’s position in the semiconductor value chain |
11:40 - 12:35 | PANEL Key opportunities and threats relevant to open source silicon strategies |
12:35 - 12:45 | Q&A and conclusions |
Nov 3, 2023
The first IC designed in B&H has been fabricated
The details of that development are in the following references:
[1] A. Pajkanovic, “On the Application of Free CAD Software to Electronic Circuit Curricula”, 3rd IcETRAN2016, Zlatibor, Serbia, 2016[2] A. Pajkanovic and Z. Ivanovic, “A Report on Recent Development in Application of Free CAD Software to IC Curricula,” 5th IcETRAN2018, Palic, Serbia, 2018.[3] A. Pajkanovic, “Introducing Chisel to IC Design Curriculum at the Faculty of Electrical Engineering in Banja Luka”, 8th RISCV Workshop, Barcelona, Spain, 2018[4] A. Pajkanovic, “CMOS IC Design from Schematic Level to Silicon within IC Curricula Using Free CAD Software”, INDEL2020, Banja Luka, B&H, 2020.[5] A. Pajkanovic, “Free/Open Source EDA Tools Application in Digital IC Design Curricula”, 8th IcETRAN2021, Stanisici, B&H, 2021.[6] A. Pajkanovic, “Open Source CMOS General Purpose Operational Amplifier", MIEL 2021[7] A. Pajkanovic, "Free IC Design in Education", PSSOH 2021
Aug 2, 2023
[video] Interviews from FSiC, Paris, 2023
Interviews with selected Free Silicon Conference Participation by Matt Venn are available online:
00:23 Luca Alloatti, FSiC Organizing Committee
01:59 Thomas Benz, ETH Zurich
06:05 Jørgen Kragh Jakobsen, IC Works - Open Source Chip Design
08:57 Thomas Parry, SPHERICAL
11:05 Rene Scholz, IHP Microelectronics
14:06 Dan Fritchman, UC Berkeley
18:41 Harald Pretl, Johannes Kepler University Linz
All the conference proceedings (slide presentations and prerecorded talks) are also available at the FSiC website.
Jun 9, 2023
[Workshop] Open Source PDKs and EDA
- Makoto Ikeda (The University of Tokyo)
- Mehdi Saligane (University of Michigan)
- Design experience: “The Journey of Two Novice LSI Enthusiasts: Tape-Out of CPU+RAM in Just One Month”, Kazuhide Uchiyama, University of Electro-Communications and Yuki Azuma, University of Tsukuba
- From Zero to 1000 Open Source Custom Designs in Two Years, Mohamed Kassem, Co-founder and CTO, Efabless
- The SKY130 Open Source PDK: Building an Open Source Innovation Ecosystem, Steve Kosier, Skywater technology
- Open Source Chip Design on GF180MCU – A foundry perspective, Karthik Chandrasekaran, Global Foundries
- Japan Foundries' Perspectives on Silicon design democratization, Shiro Hara, Minimal Fab & AIST
- Google's perspective on Open source PDKs, Open source EDA tools, and OpenMPW shuttle program, Johan Euphrosine and Tim Ansell, Google
- The Nanofabrication Accelerator Project, Matthew Daniels, NIST
- Japanese government perspective on Silicon design democratization, Yohei Ogino, The Ministry of Economy, Trade and Industry METI
May 11, 2023
OpenPDK Networking Workshop
Networking Workshop FMD-QNC on 27-28 June 2023
Location:
IHP; Im Technologiepark 25; 15236 Frankfurt (Oder)
Contact:
Sergei Andreev; Phone: +49 335 5625 523
Presentation |
Presenter/Institution |
Timeline |
Day 1 |
||
Welcome by coordinator FMD-QNC |
Dr. Andreas Bruning |
9:00-9:10 |
Introduction FMD-QNC project status and IHP OpenPDK Roadmap |
Dr. Rene Scholz |
9:10-9:30 |
Status OpenPDK and OpenTooling for SG13G2 BiCMOS technology |
Sergei Andreev |
9:30-10:00 |
An Ultra-Low-Power High-Density Wireless Biomedical Sensing System
|
Prof. Harald Pretl |
10:00-10:30 |
Teaching digital design by using open-source EDA tools |
Prof. Steffen Reith |
10:30-11:00 |
Coffee break |
11:00-11:40 |
|
CMOS Rail-to-Rail Operational Amplifier for HPGe Radiation Detector |
Prof. Herman Jalli Ng |
11:40-12:10 |
Design-flow approaches for mmWave and sub-THz integrated transceiver circuits for radar and communication |
Sasha Breun
|
12:10-12:40 |
Lunch break |
12:40-13:40 |
|
TBD |
Dr. Frank K. Gurkaynak |
13:40-14:10 |
TBD |
Joachim Hebeler |
14:10-14:40 |
Coffee break |
14:40-15:10 |
|
TBD |
Prof.
Dietmar Kissinger |
15:10-15:40 |
LibMan - an easy way to manage your open source design flow |
Dr. Anton Datsuk |
15:40-16:10 |
Get together (Barbecue) |
|
17:00-… |
Day 2 |
||
ngspice - status and future developments |
Prof. Holger Vogt |
9:00-9:20 |
DMT - Python Toolkit for Device Modeling |
Mario Krattenmacher |
9:20-9:40 |
OpenVAF - Next Generation Verilog-A Compiler with ngspice integration |
Mario Krattenmacher |
9:40-10:00 |
Coffee break |
10:00-10:40 |
|
Best practices for implementing and optimizing KLayout DRC and LVS decks |
Matthias Köfferlein |
10:40-11:00 |
Generating DRC and LVS Runsets for KLayout |
Dr. Andreas Krinke |
11:00-11:20 |
OpenEMS in open source EDA |
Jan Taro Svejda |
11:20-11:40 |
Lunch break |
11:40-12:40 |
|
Panel discussion on the roadmap – open source tools for IC design Topics:
|
Dr. Norbert Herfurth Panelists: TBD |
12:40-14:10 |
Apr 6, 2023
[Deadline] #TinyTapeout 3
#TinyTapeout and #SiliWiz are online tools you can use to learn how ASICs are designed, made and how they work. You can even get your designs affordably manufactured!
Matt Venn has some free slots for #TinyTapeout 3 for you and your students - just send him a DM to get started!
Deadline is 24th April! Apply today at https://tinytapeout.com/
Mar 22, 2023
[analog-wg] Video of March 21 AWG Meeting
The AWG Video Meeting on March 21, 2023 included two presentations:
- Ken Kundert "Why Fund OpenVAF"
- Pascal Kuthe "OpenVAF: An innovative open-source Verilog-A Compiler"
- 4th April: Update from Tim Edwards: Magic and PEX extraction
- 18th April: Update from Sadayuki Yoshitomi: Ecosystem of compact model development
- 2nd May (tentative): Update from C. Enz,EPFL: test structures measurements
Jan 24, 2023
Mixed Signal SoC design Marathon using eSim & SKY130
Marathon Date : 23 Sept. - 8 Oct. 2022
The following submissions are adjudged as Outstanding, Excellent, Very good and Good by the FOSSEE and the VSD teams.
List of Outstanding Circuits:
# | Participant | Circuit | Institute | GitHub |
---|---|---|---|---|
1 | Milad Vafaieenezhad | Window Comparator Along with MOD-16 Counter for Counting Based Data Line Selection Operation | Shahed University | View Repo |
2 | Krunal Badlani | Crack Sensing Circuit | Indian Institute of Technology Hyderabad | View Repo |
3 | Karuppusamy V | Flash Type ADC | Bannari Amman Institute of Technology | View Repo |
4 | Inderjit Singh Dhanjal | 32-bit SRAM implementation in eSim using Skywater 130nm CMOS technology | K. J. Somaiya College of Engineering | View Repo |
5 | Tanay Das | Design of a Class D Audio Amplifier IC Using Sliding Mode Control and Negative Feedback | Sikkim Manipal Institute of Technology | View Repo |
6 | Jayanth Nedunuri | Implementation of 4 bit Two Step Flash ADC | Jyothishmathi institute of Technology and Science | View Repo |
7 | Aishwarya Balkrishna Patil | Design and Implementation of Automatic Security Monitoring System | Kolhapur Institute of Technology’s College of Engineering, Kolhapur | View Repo |
8 | Swagatika Meher | 3-bit CMOS based TIQ comparator Flash ADC | Odisha University of Technology and Research, Bhubaneswar, Odisha | View Repo |
9 | Surya V | 3-bit Flash ADC using ROM-based Encoder | National Institute of Technology, Tiruchirapalli | View Repo |
10 | Sanket M Mantrashetti | Design of 8x8 SRAM based on 6T SRAM cell | R. V. College of Engineering | View Repo |
11 | Avishek Choudhary | 10-bit C2C DAC | Thapar Institute of Engineering and Technology | View Repo |
12 | Nalinkumar S | Implementation of Quadruple - Window Comparator Along with Prioritized MOD-16 Counter for Data Line Multiplexing Operation | Madras Institute of Technology Campus, Anna University | View Repo |
13 | Rubankumar D | Astable Multivibrator Along with MOD-16 Counter for Counting Based Data Line Selection Operation | Madras Institute of Technology Campus, Anna University | View Repo |
14 | Vanshika Tanwar | Implementation of 3 Bit Flash ADC performed in eSim | Dronacharya Group Of Institutions, Greater Noida | View Repo |
15 | Ravi Prakash Vishwakarma | 8 Bit Counter/Ramp Type ADC | Madan Mohan Malaviya University Of Technology | View Repo |
16 | E Balakrishna | Implementation of 4 Bit Flash ADC mixed signal circuit using 130nm performed in eSim | Dronacharya Group of Institution, Greater Noida | View Repo |
Contact eSim-fossee:
For more information about the marathon, write to us at contact-esim[at]fossee[dot]in
Dec 23, 2021
[Special Issue] ACM Transactions on Machine Learning for CAD / EDA
• Yibo Lin, Peking University• Avi Ziv, IBM Research, Haifa, Israel• Haoxing Ren, NVIDIA Corp.
• ML for system-level design• ML approaches to logic design and synthesis• ML for timing• ML for clock networks and power grids• ML for variation-aware design, analysis and optimization• ML for physical design• ML for analog design• ML for power and thermal management• ML for Design Technology Co-Optimization (DTCO)• ML methods to predict aging and reliability• Labeled and unlabeled data in ML for CAD• ML techniques for resource management in many cores• ML for verification and validation• ML for test• ML for library design and optimization
• Submissions deadline: February 15, 2022• First-round review decisions: April 15, 2022• Deadline for revision submissions: May 15, 2022• Notification of final decisions: June 15, 2022• Tentative publication: Summer 2022
• Yibo Lin• Avi Ziv
Dec 8, 2021
Guardian of Verilog-A Compact Models
Sep 1, 2021
Keep Your Business Running With KiCad EDA
May 8, 2021
10th All-Russia MES-2021 Conference
1. Theoretical aspects of micro-and nanoelectronic systems (MES).
2. Methods and tools of design automation for micro-and nanoelectronic circuits and systems (VLSI CAD).
3. Experience of development of digital, analog, digital to analog, radio functional blocks of VLSI.
4. Features of VLSI design for nanometer technologies.
5. SoCs for advanced radioelectronic equipment.
6. Exhibition and presentation of commercial products.
1. Circuits and Systems based on nanometer technologies2. Systems on Chip3. Digital VLSI Design4. Design of analog functional blocks and radio VLSI5. Design of mixed-signal VLSI6. Methods of structural synthesis of analog, digital and mixed VLSI and complex functional blocks7. Specialized (resistant to special effects, photosensitivity, etc.) VLSI
1. Methods of simulation of digital, analog and mixed circuits and systems2. Methods for radio VLSI simulation3. Structural, logical, circuit, mixed and layout simulation4. Methods for generating models and macromodels for VLSI CAD5. Device and Technology simulation6. Behavioral simulation
1. Information coding2. Digital data processing3. Use of artificial intelligence methods, neural networks, etc. in micro- and nanoelectronic system designs4. Unconventional arithmetic5. High-performance computers
1. Nanomagnetic storage devices2. Magnetosensor structures
Call for participation in the conference program