[paper] PSP RF Model

Xiaonian Liu^{1, 2} and Yansen Liu¹

A Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

DOI :10.2528/PIERL23081405

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China.
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract : An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The RF PSP Model Subcircuit

Acknowledgment : This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

[11k online viewers] 7th Sino MOS-AK/Nanjing

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

7th Sino MOS-AK Workshop in Nanjing (CN)

August 11-13, 2023 (online/onsite)

Recent, consecutive, 7th Sino MOS-AK/Nanjing Workshop discussing the Compact/SPICE modeling and its Verilog-A Standardization reached 11k online viewers. The MOS-AK participants and online attendees have followed one day SiC-related device modeling training on August 11 featured presentations by experts currently working at Robert Bosch GmbH and then two days workshop with 24 R&D Compact/SPICE modeling presentations:

[paper] TMD FETs

Ahmed Mounir^a, Benjamin Iñiguez^a, François Lime^a, Alexander Kloes^b

Theresia Knobloch^c, Tibor Grasser^c

Compact I-V model for back-gated and double-gated TMD FETs

Solid-State Electronics (2023): 108702

DOI: 10.1016/j.sse.2023.108702

a Rovira I Virgili University, Tarragona, Spain
b University of Applied Sciences, Giessen, Germany
c TU Wien, Vienna, Austria

Abstract: A physics-based analytical DC compact model for double and single gate TMD FETs is presented. The model is developed by calculating the charge density inside the 2D layer which is expressed in terms of the Lambert W function that recently has become the standard in SPICE simulators. The current is then calculated in terms of the charge densities at the drain and source ends of the channel. We validate our model against measurement data for different device structures. A superlinear current increase above certain gate voltage has been observed in some MoS2 FET devices, where we present a new mobility model to account for the observed phenomena. Despite the simplicity of the model, it shows very good agreement with the experimental data.

Fig : 2D schematic structure for 2D TMD FETs: (a) a double gated monolayer MoS2 FET. 

(b) a double gated monolayer WSe2 FET. (c)  single back-gated multilayer MoS2 FET. 

(d) single back-gated monolayer FET.

[C4P] FSiC 2023

The 2023 Free Silicon Conference (FSiC)

will take place in Paris (Sorbonne)

on July 10-12, 2023 (Monday to Wednesday)

This event will build on top of the past FSiC2019 and FSiC2022 editions. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere.

Participation to the conference is free of charge, but the attendance must be reserved per email at fsic2023 'at' f-si.org. Details will be announced on this page and over the mastodon channel. The slides and the video recordings of the talks will be published on our website.

Discussion topics of the 2023 Free Silicon Conference (FSiC) 

• High-level design
• Hardware security
• On-going FOSS silicon projects
• Memories
• Foundries and free PDKs
• Transistor Compact/SPICE/Verlog-A modeling
• Place-and-route tools
• Parasitic extraction
• Design rule checking
• Schematic editors
• Photonics
• Sustainability

Submission: For proposing a talk, please submit a title and a short summary at
fsic2023 'at' f-si.org.

FSiC Organizing Committee

[paper] Compact Geiger Counters

E. A. Maurchev, Yu. V. Balabin and A. V. Germanenko

Compact Geiger Counters as Additional Tools for Verifying Models 

of Cosmic Ray Transport through the Earth’s Atmosphere

Bulletin of the Russian Academy of Sciences

Physics volume 85, pages1294–1296 

(Published: 10 December 2021)

DOI: 10.3103/S106287382111023X

   

*Polar Geophysical Institute, Apatity (RU)

Abstract: Descriptions and technical characteristics are given for compact Geiger counters designed to verify calculations of cosmic ray transport through the Earth’s atmosphere. Results are presented in the form of a comparison of the altitude profiles of count rates of charged particles, obtained via modeling and field experiments.

Fig: Comparison of the count rate altitude profiles obtained during the balloon probe launch for different time periods and airborne measurements and results from modeling a GCR proton transit. The triangle on the left is probe measurements for Jan. 4, 2010; the triangle on the right, probe measurements for Jan. 1, 2010. The inverted triangle is probe measurements for Jan. 18, 2010; the upright triangle, probe measurements for Jan. 20, 2010. Crosses are measurements on an Airbus in 2018 (67.95 N and 32.8 E, climbing), and the solid line is calculated data.

[papers] Compact/SPICE Modeling

[1] Wang, Jie; Chen, Zhanfei; You, Shuzhen; Bakeroot, Benoit; Liu, Jun; Decoutere, Stefaan; "Surface-Potential-Based Compact Modeling of p-GaN Gate HEMTs" Micromachines (2021) 12, no. 2: 199; https://doi.org/10.3390/mi12020199

Abstract: We propose a surface potential (SP)-based compact model of p-GaN gate high electron mobility transistors (HEMTs) which solves the Poisson equation. The model includes all possible charges in the GaN channel layer, including the unintended Mg doping density caused by out-diffusion. The SP equation and its analytical approximate solution provide a high degree of accuracy for the SP calculation, from which the closed-form I–V equations are derived. The proposed model uses physical parameters only and is implemented in Verilog-A code.

Fig: The equivalent circuit of the capacitance of field plates (FPs) of a p-GaN gate HEMT.

[2] Chen, H. and He, L.,  The spatial and energy distribution of oxide trap responsible for 1/f noise in 4H-SiC MOSFETs. Journal of Physics Communications, JPCO-101816.R1 (2021)

Abstract: Low-frequency noise is one of the important characteristics of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) that is susceptible to oxide traps. Drain-source voltage noise models of 4H-SiC MOSFETs under low–drain-voltage and inverse condition were proposed by considering the spatial and energy non-uniform distribution of the oxide trap, based on the McWhoter model for uniform trap distribution. This study performed noise experiments on commercial 4H-SiC MOSFETs, and revealed that the non-uniform spatial and non-uniform energy distribution caused new 1/f noise phenomenon, different from that under uniform spatial and energy distribution. By combining experimental data and theoretical models, the spatial and energy distribution of oxide traps of these samples were determined.

Fig: Adaptive circuit for 4H-SiC MOSFET noise measurement

in the frequency 1 Hz-10kHz ranged

[papers] Compact/SPICE Modeling

[1] Kotecha, Ramachandra M., Md Maksudul Hossain, Arman Rashid, Asif Emon, Yuzhi Zhang, and Homer Ei C. Alan Mantooth. "Compact Modeling of High-Voltage Gallium Nitride Power Semiconductor Devices for Advanced Power Electronics Design." IEEE Open Journal of Power Electronics (2021)

Fig: (a) Structure of field-plated GaN transistor (b) Equivalent sub-circuit topology

---

[2] Sengupta, Sarmista, and Soumya Pandit. "A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-Channel EδDC MOS Transistor." (researchsquare.com 2021).

Fig: Schematic diagram of an Epitaxial δ doped n-channel MOS transistor used for design purpose and the graded retrograde approximation of the channel profile of EδDC transistor.

---

[3] Patil, C.V., Suma, M.S. Compact modeling of through silicon vias for thermal analysis in 3-D IC structures. Sādhanā 46, 35 (2021). https://doi.org/10.1007/s12046-020-01549-1

Fig: Through Silicon Via 2D representation and its equivalent subcircuit.

[mos-ak] [on-line publications] Spring MOS-AK Workshop in London

  

Recent, Spring MOS-AK Workshop at the London Metropolitan University was organized to discuss SPICE/compact modeling and its standardization with following Qucs GPL circuit simulation tutorial. The workshop's presentations are available on-line at <http://www.mos-ak.org/london_2014/>.

   

Please also distribute further information about next MOS-AK related events among all who are interested in the SPICE/compact modeling and its Verilog-A standardization:

• 3rd International Training Course on Compact Modelling (TCCM) Lublin (PL) June 18, 2014
• http://compactmodelling.eu/tccm3_about.php
• MIXDES Special Compact Modeling Session, Lublin (PL) June 19-21, 2014
• http://www.mixdes.org/Mixdes3/tekst/view/special
• 12th MOS-AK ESSDERC/ESSCIRC Workshop, Venice (I) Sept. 26, 2014
• http://www.mos-ak.org/venice_2014/
• 7th International MOS-AK Workshop San Francisco (US) Dec. 2014
• http://www.mos-ak.org/

Already now, I am looking forward to meet you at one of our MOS-AK modeling events, soon.

-- with regards - wladek for the Extended MOS-AK/GSA Committee;

--

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

--

Over two decades of Enabling Compact Modeling R&D Exchange

--

http://www.mos-ak.org

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after Analogschaltungen'09 in Hannover

The workshop program included following topics:

• Novel CMOS/BiCMOS circuit architectures for the GHz range applications
  
• Models of semiconductor devices for analog/RF (GHz range) applications
  
• Influences of the system design and optimization on the components in the analog circuit applications
• Classical and quantum mechanical effects in analog/RF nano-silicon circuits at GHz frequencies
  

The workshop has been organized by:

• Prof. Dr. -Ing. Wolfgang Mathis, Leibniz Universität Hannover, Institut für Theoretische Elektrotechnik; Appelstr. 9A, 30167 Hannover

in cooperation with:

• Prof. Dr.rer. nat. Doris Schmitt- Landsiedel, TU München; Lehrstuhl für Technische Elektronik
• Prof. Dr. -Ing. Heinrich Klar, TU Berlin; Institut für Technische Informatik und Mikroelektronik
• Prof. Dr.-Ing. Y. Manoli, Universität Freiburg; IMTEK