Sun, Jing, Daquan Liu, Hang Li, Wensheng Qian, Jiye Yang, Yabin Sun, Bingyi Ye, Yuhang Zhang, Yang Shen, and Xiaojin Li. "A physics-based and accurate STI-LDMOS compact subcircuit model with modified drift region resistance and gate-drain capacitance."
Semiconductor Science and Technology (2026).
Abstract: This paper develops a physics-based and accurate shallow trench isolation lateral double-diffused MOS (STI-LDMOS) compact subcircuit model. In the proposed direct-current (DC) model, the drift-region resistances beneath both the STI region and the drain electrode are incorporated, thereby significantly improving its physical fidelity and predictive accuracy of the DC characteristics. For the proposed alternating-current model, the gate–drain capacitance model is decomposed into two components: a gate–drift-region overlap charge model with modified bias dependence derived from BSIM4.5, and a parallel-plate capacitance model for the gate–STI overlap region. In addition, the gate–source capacitance and drain–source charge models are further extended to match the physical structure and to more accurately capture the dynamic characteristics of an STI-LDMOS device. The model parameters are extracted and calibrated, and the proposed subcircuit model is implemented in Verilog-A. Excellent agreement is achieved between the proposed model and both the technology computer-aided design (TCAD) simulation results and the measured data from a 40 V STI-LDMOS device, demonstrating its accuracy and efficiency for circuit-level simulation of STI-LDMOS devices.
Nakos, Miltiadis Κ., Theodoros Α. Oproglidis, Dimitrios Η. Tassis, Constantinos Τ. Angelis, Charalabos Α. Dimitriadis, and Andreas Tsormpatzoglou. "Symmetric physics-based compact core model for double-gate junctionless transistors with ungated extensions." (2026).
Abstract: This work presents a physics-based compact model for double-gate junctionless field-effect transistors, with emphasis on accurately capturing the impact of ungated source/drain extensions on the drain current characteristics. The model is validated against two-dimensional device simulations performed using Silvaco ATLAS for two channel doping concentrations and a wide range of ungated extension lengths. To isolate the contribution of the access regions and clarify the effective channel length, all mobility degradation models were disabled in the simulations, allowing the observed current degradation to be attributed solely to the series resistance of the ungated extensions. The proposed formulation includes an analytical factor ξ that accounts for the reduced electrostatic influence of the source and drain terminals on the channel potential, as well as a closed-form expression for the fringe capacitance associated with the ungated regions. The resulting drain current model demonstrates very good agreement with numerical simulations across different geometries and doping levels. Model symmetry is further verified through a Gummel symmetry test, confirming the physical consistency of the formulation. Owing to its analytical nature and physical transparency, the proposed model is well suited to serve as a core building block for higher-level compact models of JL devices.
Y. Liu, L. Tian, Y. Niu, Y. Xia and W. Chen, "A SPICE-Compatible High-Efficiency Equivalent Mechanical Circuit Method for Electro-Thermal-Mechanical Coupling Simulation," in IEEE Transactions on Electron Devices
doi: 10.1109/TED.2026.3671249.
Abstract: Accurate and efficient modeling and simulation of electro-thermal-mechanical field coupling is essential for evaluating multiphysics effects on devices/circuits’ performance and reliability, as the multiphysics coupling effects become severe in advanced integrated circuits. In our previous work, we developed the equivalent mechanical circuit (EMC) method, thereby constructing a SPICE-compatible equivalent multiphysics circuit framework to simulate electro-thermal-mechanical coupling processes in advanced integrated circuits. However, the computational efficiency of the previous EMC (pEMC) method remains limited compared with the finite element method (FEM), since the pEMC method requires multiple iterations to simulate thermal expansion, even in linear equation systems. In this article, we develop a novel EMC method by proposing voltage-controlled current sources (VCCSs) into the pEMC. Therefore, the novel EMC method can simulate thermal expansion without iteration in linear equation systems. The results demonstrate that the computational efficiency of the novel EMC method achieves a tenfold improvement compared to the pEMC method and exhibits computational efficiency comparable to the FEM under the same number of nodes.
F. Yu et al., "Precise Surface Potential Modeling for Compact DC Models of a-IGZO Thin Film Transistors," in IEEE Transactions on Electron Devices,
doi: 10.1109/TED.2026.3671772.
Abstract: Many thin film transistor (TFT) models that consider the free and trapped charges, including models for amorphous InGaZnO (a-IGZO) TFTs, rely on the accurate determination of surface potential. In this work, a physically-based initial solution and fast-converging iterative procedure with logarithmic increment are utilized for the precise determination of the surface potential model in TFTs with channels of noncrystalline semiconductors, which have exponentially distributed tails and deep traps in the semiconductors. In particular, the surface potential model does not use special functions, such as the Lambert W function. The precision of the proposed scheme of analytical model and iterative procedure is verified against reference simulations of surface potential, and against measured current–voltage DC characteristics of a-IGZO TFTs, employing a well-established surface-potential-based charge sheet model. The precision of the iterative procedure is in the range of few nV, converging approximately for less than half of the number of iterations of other schemes for the calculation of the surface potential. Accordingly, the proposed analytical model for surface potential and the iterative scheme for the determination of the values of the surface potential are suitable for implementation in TFTs’ circuit simulators.
K. Ohmori and S. Amakawa, "Variable-Temperature Broadband Noise Characterization of MOSFETs for Cryogenic Electronics: From Room Temperature down to 3 K," 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Seoul, Korea, Republic of, 2023, pp. 1-3,
doi: 10.1109/EDTM55494.2023.10103124.
Abstract: A broadband noise measurement system is newly developed and demonstrated at temperatures between 3 K and 300 K. Using the system, wideband noise spectroscopy (WBNS) from 20 kHz to 500 MHz is carried out for the first time, revealing that shot noise is the dominant white noise down to 3 K. The paper also suggests, by means of WBNS, the possibility of extracting the baseline noise characteristics, which do not include the noise component that varies a great deal from device to device.
Jeong, Junhwa, Ilho Myeong, and Ickhyun Song. "Impact of MOSFET source/drain resistance on channel thermal noise calculation and noise performance."
Results in Physics (2026): 108634.
Abstract: For sub-micron metal oxide semiconductor field effect transistors (MOSFETs), parasitic series source/drain resistance has a significant impact on channel thermal noise (Sid) and noise parameters. In this work, we propose an improved analytical channel thermal noise model considering parasitic resistance, based on physical thermal noise models of sub-micron intrinsic MOSFETs. To validate the proposed model, measurements were performed at room temperature (25°C) on nMOSFETs fabricated in a commercial 130-nm (0.13-µm) bulk RF CMOS technology. All RF S-parameter and noise measurements were conducted on-wafer at room temperature, with open/short de-embedding applied to accurately remove pads and interconnect parasitics. The model was calibrated by extracting parameters in a spice with the standard BSIM4 model as a baseline and validated against measured data such as Sid, Rn, NFmin, Gopt, and Bopt. Furthermore, the proposed model is extended to a circuit-level analysis by deriving the noise figure of a high-frequency amplifier (HFA) using Cadence Virtuoso (Spectre). A good agreement between the measurement and the developed model is observed, particularly under high gate bias (Vgs) conditions where the potential drop at the parasitic resistance becomes apparent. The analysis demonstrates that accurate modeling of parasitic resistance is essential for predicting the accurate noise figure of the HFA in high-current regimes. The improved model predicts the thermal noise of both the extrinsic MOS device and the HFA circuit well, thereby supporting accurate noise simulations for high-frequency circuits that operate under a wide range of gate bias conditions.
Fig. (a) 3D image of LDD MOSFET (b) equivalent circuits of (a) where
Rlds + Rss = RS and Rldd + Rdd = RD (c) equivalent circuit of intrinsic MOSFET.
