[paper] Model for Scaled Cryo FETs

Hyewon Park, Dokyoung Lee, Hyeonsik Ahn, Jusung Kim and Sungho Kim

Physics-based model for scaled cryogenic FETs with band-tail-assisted carrier statistics

SciRep (2026)

DOI: 10.1038/s41598-026-65834-5

1. Division of Electronic and Semiconductor Engineering, Ewha Womans University (KR)

2. Institute for Multiscale Matter and Systems (IMMS), Ewha Womans University (KR)

3. Department of Electronic Engineering, Hanbat National University, Daejeon (KR)

Abstract: Accurate transistor models that remain predictive at cryogenic temperatures are essential for developing large-scale cryogenic complementary metal–oxide–semiconductor platforms that support quantum computing and other low-temperature electronic systems. However, existing cryogenic field-effect transistor (cryo-FET) models struggle to simultaneously reproduce threshold-voltage shifts, gradual subthreshold turn-on, and above-threshold transport in scaled devices because these behaviors originate from distinct physical mechanisms. This study presents a physics-based model for scaled cryo-FETs that integrates the temperature-dependent electrostatic alignment, continuous interface-trap energy distribution, band-tail-assisted carrier statistics, and effective field-dependent mobility degradation within a unified charge-based framework. The model explicitly incorporates bandgap widening and incomplete dopant ionization into the metal–semiconductor work-function difference while representing interface traps through a physically consistent continuous energy spectrum. The study further demonstrates that interface-trap electrostatics alone cannot account for the experimentally observed subthreshold broadening at deep cryogenic temperatures owing to the excessively sharp Maxwell–Boltzmann carrier response. To resolve this limitation, a band-tail-assisted statistical carrier formulation that broadens the subthreshold carrier formation while naturally recovering the conventional conduction-band transport in strong inversion is introduced. The model accurately reproduced the transfer characteristics of 65-nm silicon bulk transistors from 250 K to 12 K over multiple decades of drain current, with excellent agreement in both the threshold behavior and the subthreshold slope. These results establish a physically interpretable and quantitatively accurate modeling framework for scaled cryo-FETs, thereby providing a foundation for predictive cryogenic circuit design and future compact-model development.

Fig.1: Physical origin of transfer-characteristic deviations in scaled cryo-FETs and the corresponding model extensions. Schematic of the logarithmic ID–VG characteristics comparing the measured behavioral characteristics with those of the baseline cryo-FET model. At cryogenic temperatures, the baseline model shows three key mismatches: threshold-voltage shift, overly steep subthreshold turn-on, and inaccurate above-threshold current. These arise from distinct mechanisms. The threshold shift is linked to temperature-dependent electrostatics, including bandgap widening and incomplete ionization. The subthreshold mismatch reflects the sharp Maxwell–Boltzmann carrier response at low thermal voltages, motivating a band-tail-assisted formulation. The above-threshold error results from insufficient transport-field coupling, requiring effective-field-dependent mobility.

Acknowledgements: This work was supported by the National Research Foundation of Korea (NRF) grants funded by the Korean government (MSIT and MOE) (RS-2024-00449412 and RS-2025-16063688). Data supporting the findings of this study are available from the corresponding author upon reasonable request.

[paper] SPICE Modeling of a Radiation Sensor

Miloš Marjanović 1, Stefan D. Ilić 2, Sandra Veljković 1, Nikola Mitrović 1, Umutcan Gurer 3, Ozan Yilmaz 3, Aysegul Kahraman 4, Aliekber Aktag 3, Huseyin Karacali 3, Erhan Budak 3, Danijel Danković 1, Goran Ristić 1 and Ercan Yilmaz 3

The SPICE Modeling of a Radiation Sensor Based on a MOSFET

with a Dielectric HfO2/SiO2 Double-Layer

Sensors 2025, 25(2), 546; DOI:10.3390/s25020546

1 Department of Microelectronics, Faculty of Electronic Engineering, University of Niš, Serbia
2 Center of Microelectronic Technologies, Institute of Chemistry, Technology and Metallurgy, University of Belgrade, Serbia
3 Faculty of Arts and Sciences, Bolu Abant Izzet Baysal University, Turkey
4 Department of Physics, Faculty of Arts and Sciences, Bursa Uludag University, Turkey

Abstract: We report on a procedure for extracting the SPICE model parameters of a RADFET sensor with a dielectric HfO2/SiO2 double-layer. RADFETs, traditionally fabricated as PMOS transistors with SiO2, are enhanced by incorporating high-k dielectric materials such as HfO2 to reduce oxide thickness in modern radiation sensors. The fabrication steps of the sensor are outlined, and model parameters, including the threshold voltage and transconductance, are extracted based on experimental data. Experimental setups for measuring electrical characteristics and irradiation are described, and a method for determining model parameters dependent on the accumulated dose is provided. A SPICE model card is proposed, including parameters for two dielectric thicknesses: (30/10) nm and (40/5) nm. The sensitivities of the sensors are 1.685mV/Gy and 0.78mV/Gy, respectively. The model is calibrated for doses up to 20Gy, and good agreement between experimental and simulation results validates the proposed model.

FIG: (a) Block diagram of the radiation source setup; 

(b) radiation setup in the TENMAK lab.

The corresponding SPICE model card is presented below:

.MODEL RADFET PMOS VTO={if(TYPE==1,-0.493-(1.54e-3*DOSE),-0.65433-(7.54E-4*DOSE))}

+KP={if(TYPE==1,8.897e-6-(1.493e-8*DOSE),1.14E-5-(2.511E-9*DOSE))} L=50e-6 W=600e-6

+TPG=0 LAMBDA={if(TYPE==1,3.901E-2-(2.165E-4*DOSE),2.0115E-2-(1.8575E-4*DOSE))}

Acknowledgements: This research was funded by North Atlantic Treaty Organization (NATO) SPS MYP under grant number G5974, by the project “High-k Dielectric RADFET for Detection of RN Treats”, and supported by the Ministry of Science, Technological Development and Innovation of the Republic of Serbia [grant number 451-03-65/2024-03/200102 and grant number 451-03-66/2024-03/200026].

[paper] PSP RF Model

Xiaonian Liu1, 2, and Yansen Liu1, 2

Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract: An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 µm CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The PSP RF subcircuit model and its S-par s fitting

results of NMOS with Wf = 2 µm, Lf = 0.12 µm, nf = 16

Acknowledgment: This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

[paper] PSP RF Model

Xiaonian Liu^{1, 2} and Yansen Liu¹

A Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

DOI :10.2528/PIERL23081405

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China.
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract : An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The RF PSP Model Subcircuit

Acknowledgment : This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

[paper] THz FET Modeling

Adam Gleichman¹, Kindred Griffis¹, and Sergey V. Baryshev^1,2

Useful Circuit Analogies to Model THz Field Effect Transistors

arXiv:2307.07488v1 [physics.app-ph] 14 Jul 2023

1) Department of Electrical and Computer Engineering, Michigan State University, USA
2) Department of Chemical Engineering and Materials Science, Michigan State University, USA

Anstract: The electron fluid model in plasmonic field effect transistor (FET) operation is related to the behavior of a radio-frequency (RF) cavity. This new understanding led to finding the relationships between physical device parameters and equivalent circuit components in traditional parallel resistor, inductor, and capacitor (RLC) and transmission models for cavity structures. Verification of these models is performed using PSpice to simulate the frequency dependent.

FIG: RLC Lumped THz FET Model

[paper] Model for TFT Used in a CMOS Inverter Amplifier

Adelmo Ortiz-Conde^a, CarlosÁvila-Avendaño^b, Jesús A.Caraveo-Frescas^b, Manuel A.Quevedo-López^b and Francisco J.García-Sánchez^a

A polylogarithmic model for thin-film transistors used in a CMOS inverter amplifier

Solid-State Electronics

Volume 188, February 2022, 108218

DOI: 10.1016/j.sse.2021.108218

   
a Solid State Electronics Laboratory, Universidad Simón Bolívar, Caracas 1080, Venezuela
b Materials Science and Engineering Department, University of Texas at Dallas, Richardson, TX 75080, USA

Abstract: This article presents a generalization of a transregional polylogarithmic model, previously proposed for continuously describing the transfer characteristics of polycrystalline and amorphous Thin Film Transistors (TFTs) at all levels of inversion. The present generalization entails including the necessary drain voltage dependencies to be able to describe also the output characteristics. The model is tested by using it in the design and analysis of a CMOS inverter amplifier consisting of poly-Si n- and p-channel TFTs fabricated at low temperature and pressure. The transistors are biased below threshold so that the CMOS amplifier circuit operates in weak conduction, having in mind energy saving considerations. The validity of the proposed model has been ascertained by comparing model simulations to actual measured data from individual poly-Si TFTs and from the CMOS amplifier circuit. The simulations of the CMOS inverter amplifier are compared to the results obtained using look-up table-type simulations.

Fig: Normalized current with respect to its maximum value versus gate bias for two different values of drain bias (top). The curve for the higher drain bias (blue dash line) is shifted to the right of that for the lower drain bias (red continuous line), indicating that VT increases as VDS increases. The corresponding Y function versus gate bias (bottom) illustrates a similar increase of VT with VDS. 

Acknowledgment: The authors would like to thank the reviewers and the editor for their valuable work, which has led to a significant improvement in the quality of this article.

Generalized EKV Compact MOSFET Model

On the Explicit Saturation Drain Current in the Generalized EKV Compact MOSFET Model

Francisco J. García-Sánchez, Life Senior Member, IEEE,

and Adelmo Ortiz-Conde, Senior Member, IEEE

IEEE TED Aug 9. 2021

DOI: 10.1109/TED.2021.3101186

*Solid State Electronics Laboratory, Universidad Simón Bolívar, Caracas 1080, Venezuela

Abstract: We present and discuss explicit closed-form expressions for the saturation drain current of short channel metal-oxide-semiconductorfield-effect transistors (MOSFETs) with gate oxide and interface-trapped charges, and including carrier velocity saturation, according to the generalized Enz-Krummenacher-Vittoz (EKV) MOSFET compact model. The normalized saturation drain current is derived as an explicit function of the normalized terminal voltages by solving the transcendental voltage versus charge equation using the Lambert W function. Because this special function is analytically differentiable, other important quantities, such as the transconductance and the transconductance-to-currentratio, can be readily expressed as explicit functions of the terminal voltages.

Fig: Comparison of simulated transfer characteristics with (red lines and symbols) and another without (black lines and symbols) radiation-induced oxide and interface-trapped charges. Calculation of V_GB versus ID_sat (lines) comes from denormalization and the explicit ID_sat versus V_GB (symbols) comes from denormalization of the proposed explicit expressions

33rd IEEE ICMTS, Edinburgh, Scotland.

IEEE 33rd International Conference on Microelectronic Test Structures April 6-9, 2020, Edinburgh, Scotland

It is our great pleasure to invite you to the 33rd IEEE International Conference on Microelectronic Test Structure (ICMTS) which will be held April 6-9, 2020, in Edinburgh, Scotland.     ICMTS is the leading measurement and characterisation conference for micro- and nano-fabrication processes including integrated circuits, photonics, and micro- and nano-system technologies.   Registration for the conference is now open at the conference website: http://www.icmts.net/conf_reg    For advance prices please register for the conference before the 24th of February.     ICMTS 2020 South Hall Complex The University of Edinburgh Pollock Halls, 18 Holyrood Park Road  Edinburgh, EH16 5AR Scotland, UK   W3W: https://w3w.co/proper.marked.sums     Hotel booking information is also available:  http://www.icmts.net/hotel_reg     Tutorials: April 6, 2020 Conference: April 7 - 9, 2020   Please contact the conference organisers at icmts@ed.ac.uk for more information.   Find the ICMTS group on LinkedIn https://www.linkedin.com/groups/3804498/  Follow us on Twitter at https://twitter.com/IEEE_ICMTS