[paper] SPICE-Q Quantum Chip Production

Ling Qiao Cai1,2, Bin Yang1,2, Fumin Luo1,2, Chang Liu1,2, WeiGui Guo1,2, GuoRong Zhang1,2, XueFei Liu1,2, Qinglang Guo1,2 and Bin Wu

SPICE-Q and Large-Scale Quantum Chip Production

[quant-ph] 16 Jun 2026 

arXiv:2606.17907v1  

1.) Yangtze Delta Industrial Innovation Center of Quantum Science and Technology, Suzhou, (CN)
2.) China Academy of Electronics and Information Technology, No. 11 Shuangyuan Road, Shijingshan District, Beijing, (CN)

Abstract: The historical analogy with SPICE is based on foundational reports, numerical methods, and experience from integrated circuit design. The requirements for quantum computing and scaling refer to established work in the field. The background on superconducting qubits, transmons, circuit quantum electrodynamics, microwave networks, material loss, and three‑dimensional interconnects draw from widely recognized literature. The background on parameter extraction, simulation frameworks, and manufacturability is informed by recent research and practical developments.

Table of Contents (Top‑Level Sections)

1. Abstract ... p. 4
2. The Emergence of SPICE and Large‑Scale Classical Circuits
   and Its Implications for Quantum Chips ... p. 5
3. SPICE‑Q Model Composition ... p. 24
4. SPICE‑Q Device‑Level Models ... p. 40
5. Standardized Manufacturing System ... p. 53
6. Integrating SPICE‑Q with Process Models ... p. 66
7. Design‑Technology Co‑Optimization (DTCO) ... p. 71
8. Large‑Scale Production Examples and Design Scenarios ... p. 75
9. Engineering Transition and Large‑Scale Quantum Chips ... p. 80
10. Summary ... p. 84
11. Acknowledgment ... p. 87
12. Reference ... p. 87
13. Appendix A ... p. 90

Acknowledgment The authors thank Jun Ye for helpful assistance. The authors also acknowledge the use

of AI tools for translation assistance and auxiliary text generation.

[paper] 130-nm CMOS tunnel p-bit cell

Ju-Young Yoon, Nuno Caçoilo, Advait Madhavan, Jabez J. McClelland, Shun Kanai, Hideo Ohno, Shunsuke Fukami, and William A. Borders, 

"130-nm CMOS-integrated superparamagnetic tunnel junction-based p-bit," 

in IEEE Electron Device Letters, 

DOI: 10.1109/LED.2026.3696800

Abstract: Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ’s resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications. 

FIG: (a) Circuit diagram of the spintronic p-bit; b) Schematic cross-sectional structure of the spintronic p-bit. Transistors and lower interconnect layers were fabricated at SkyWater, followed by fabrication of the spintronic devices at Uni. Tohoku. (c,d) Cross-sectional and plan-view electron microscope images of the spintronic device designed to exhibit stochastic fluctuations.

Acknowledgements: This work was made possible by the NIST-led Nanotechnology Xccelerator program that distributes open-source circuit designs for integration of novel technologies on CMOS.

RevEDA v0.9.0 Has Arrived

Revolution EDA v0.9.0 Has Arrived The wait is over. Revolution EDA v0.9.0 is now available, delivering our largest feature update to date and taking another major step toward a complete open-source analog and mixed-signal IC design platform. This release introduces integrated verification workflows, expanded simulation support, AI-assisted design tools, a new plugin ecosystem, and important architectural improvements designed to help engineers move faster from concept to silicon. Why This Release Matters Version 0.9.0 brings together capabilities that traditionally require multiple disconnected tools. By integrating verification, automation, extensibility, and simulation workflows into a unified environment, Revolution EDA continues to make professional IC design more accessible to engineers, researchers, educators, and startups. Highlights of v0.9.0 Integrated LVS Verification Layout-versus-Schematic (LVS) checking is now built directly into Revolution EDA. Users can: Extract hierarchical netlists from layouts and schematics Compare extracted and reference netlists Review detailed mismatch reports Cross-probe errors between schematic and layout views This significantly reduces verification effort and helps catch issues earlier in the design cycle. Expanded Simulation Support Revolution EDA now includes support for Xyce netlist generation, providing greater flexibility for simulation workflows. In addition, support for Spectre and VACASK netlisting is actively under development, bringing us closer to a truly multi-simulator environment. Hierarchical netlisting has also been enhanced with support for buses and instance arrays, enabling more complex and scalable designs. AI-Powered Design Assistance The new AI Terminal allows designers to interact with Revolution EDA using natural language. From automating repetitive tasks to exploring design modifications and workflow assistance, AI capabilities are becoming a native part of the design experience. We're only at the beginning of what's possible, and future releases will continue expanding these capabilities. New Plugin & Library Registry One of the most requested features is finally here. The new Plugin Registry and Library Registry make it simple to discover, install, and manage extensions directly from within Revolution EDA. The underlying architecture has also been redesigned to support clean integration of: Process Design Kits (PDKs) Plugins Custom workflows Third-party extensions without requiring modifications to the core codebase. Foundations for Schematic-Driven Layout Version 0.9.0 introduces the first implementation of Schematic Driven Layout (SDL), creating the foundation for tighter synchronization between circuit intent and physical implementation. Future releases will continue building on this capability to further streamline analog layout development. Coming Soon: Expanded IHP PDK Support We're also excited to share that work on the IHP PDK continues at a rapid pace. New parametric cells (PCells) are currently being added and validated, expanding device coverage and improving layout productivity. These additions are expected to be released shortly, providing designers with a richer and more capable open-source design environment built around the IHP technologies. Stay tuned for a dedicated announcement in the coming weeks. Under the Hood Improvements Alongside the headline features, v0.9.0 includes substantial improvements to performance, stability, and usability: Improved file validation and project security Faster editor responsiveness Better thread management and application stability Enhanced project workflows Numerous bug fixes across netlisting, layout editing, and plugin management MPL-2.0 Licensing Beginning with v0.9.0, Revolution EDA is distributed under the Mozilla Public License 2.0 (MPL-2.0). This change supports broader commercial and academic adoption while preserving the collaborative spirit of open-source development. Download v0.9.0 Today Whether you're designing analog ICs, building custom design flows, developing plugins, or evaluating open-source EDA solutions, Revolution EDA v0.9.0 offers powerful new capabilities ready for exploration. Download the latest release, update your existing installation, and let us know what you build. As always, your feedback, bug reports, feature requests, and contributions help shape the future of Revolution EDA. Contact us! The Revolution EDA Team

ChipFoundry September Shuttle

The commitment deadline for our September shuttle is fast approaching on July 18th.   We want to remind you that this is not the final design submission date. Here is what you need to know to confirm your space:   A 50% payment is required by July 18th to hold your reservation. Your final design files are not due until September 16th. You only need to provide your user project wrapper, and we will handle the integration through our tapeout flow.   Our team is available if you have any questions about the submission process or need help with your invoice. Reserve Now We look forward to confirming your commitment and working with you on your September tapeout!   Best regards,   The ChipFoundry Team

[SwissChips] Annual Event 2026

On 4 June 2026, the SwissChips community gathered for this year’s Annual Event at the SwissTech Convention Center in Lausanne, EPFL. With over 270 attendees, more than 50 posters, and 14 talks, the day was packed with updates, talks, and networking. We heard from across the SwissChips work packages, welcomed contributions from the wider ecosystem, and had the pleasure of having a keynote by Prof. Alberto Sangiovanni-Vincentelli from the University of California, Berkeley. The first half of the keynote from the event is available Download here (PDF, 5.8 MB)

SwissChips program included a keynote by Prof. Alberto Sangiovanni-Vincentelli from the University of California, Berkeley. The first half of the keynote from the event is available  Download here (PDF, 5.8 MB)

Following are the SwissChips presentation highlights showcasing Swiss’ growing engagement and support of the IHP OpenPDK Initiative. It's a fast‑rising, community‑driven effort that is opening real pathways for education, research, and innovation in microelectronics.

Guest Speaker: Thanushan Kugathasan, University of Geneva, presented Pixel Chips for Radiation and Optical Sensing with Tape-out completed in December 2025 and the wafer fabrication at IHP Microelectronics using 130 nm SiGe BiCMOS process.

Pixel Chips for Radiation and Optical Sensing werw implemented using IHP 130 nm BiCMOS technology through Europractice R&D collaboration for process optimization and SiGe HBTs integration within a CMOS platform.

Arianna Rubino, ETHZ, has presented the EZ130V1 open-source standard-cell library, it's available as the improved open library SG13G2 for IHP130 process:

• EZ130V1 has 213 cells - ~3x than SG13G2

• 8-track height - 11% lower height than SG13G2

Some of the standard cells created during VLSI 5 EZ130V1 otimization are eg: 

• AND3X2

• XNOR3X2

• HAX2

Croc SoC-based designs realized through a joined VLSI 2 and VLSI 5 effort are:

• KOOPA EZ130v0 library 39 cells

• SKOLL EZ130v1 library213 cells

[FSiC2026] Open EDA · Open Silicon · Sovereign by Design

FSiC2026

Free Silicon Conference 2026

Open EDA · Open Silicon · Sovereign by Design

What is FSiC? The annual gathering of the free and open-source silicon community building open EDA tools, open PDKs, and free hardware. Three days of talks and tutorials about designing chips with software you can read, share, and modify.

Who should come? Chip designers, EDA developers, researchers, students, and anyone curious about building silicon without proprietary lock-in. All experience levels welcome.

When? 6–8 July 2026

Where? University of Ljubljana, 

Faculty of Electrical Engineering

Tržaška cesta 25

SI-1000 Ljubljana

Registration closes 22 June: https://pretix.eu/FSiC/2026/

FSiC2026 Program: https://wiki.f-si.org/index.php/FSiC2026

[IHP OpenPDK] Analog IC Design Using Open Source Tools

Analog IC Design Using Open Source Tools and IHP-Open-PDK

at TU Poznan prior to MIXDES 2026

June 24, 2026

<https://www.mixdes.org/Mixdes3/tekst/view/openpdk-analog>

It is interactive demonstration workshop format with the possibility to work at stations prepared by the organizer. Personal computers are not required; however, participants may use their own laptops if they wish. with the possibility to work at stations prepared by the organizer. Personal computers are not required; however, participants may use their own laptops if they wish. The workshop is embedded into the IEEE EDS FET100 Anniversary celebration. Our workshop's expected outcome is successful integrated circuits (IC) design, submission, and fabrication (tapeout) of participants created ICs. To recognize excellence in hands‑on integrated‑circuit design, the IEEE EDS will present Student Open Silicon Prizes for outstanding student in IC design. The IEEE Electron Devices Society (EDS), together with other IEEE societies, covers complete flow from the electron devices to IC designs thru CAD/EDA software support:

• Devices (EDS): semiconductor physics, fabrication technologies
• Circuits (SSCS, CASS): analog, digital, mixed-signal, system-level design
• Design Automation (CEDA): CAD tools, verification, open-source flows

AGENDA

Start	End	Topic
8:00	8:30	Participant registration, organizational introduction
8:30	9:00	FET100 Inauguration Speech¹: Prof. K. Detka, IEEE EDS Poland
9:00	10:30	OpenSilicon DIY Integrated Circuits²: Dr. Krzysztof Herman, IHP (D) Introduction to analog design in an open-source environment (Tools overview: Xschem, Ngspice, IHP-Open-PDK, workflow basics)
10:30	10:45	Coffee break
10:45	12:30	Analog schematic design in Xschem best practices, parameterization, DC, AC, and transient simulations (live demo)
12:30	13:30	FET100 Luncheon Talk³: W. Grabinski, IEEE EDS R8 Chair
13:30	15:00	Design of a sample analog circuit operation analysis, Monte Carlo simulations, mismatch analysis, parameter verification (live demo)
15:00	15:15	Coffee break
15:15	17:00	Introduction to layout in KLayout, analog design principles (matching, symmetry, noise minimization), PyCells mask design automation (live demo)
17:00	18:00	Complete design flow: from schematic to verification (LVS/DRC process overview), fillers, chip finishing, sign-off (live demo)
18:00	18:30	Q&A session, workshop summary
18:30	>>	FET100 Celebration Appero

Workshop Tutors:

Dr. Krzysztof Herman, IHP (D); Organizer and Technical Expert Lead

Dr. Wladek Grabinski, IEEE EDS; Technical Assistant

[ICMC] Registration Reminder

Less Than 2 Months Until ICMC 2026 Save $50 if you register before June 30, 2026 Join the global compact modeling community this July at the International Compact Modeling Conference (ICMC 2026), taking place July 30–31, 2026, aboard the historic Queen Mary in Long Beach, California. ICMC brings together leaders in compact modeling, process technology, circuit design, and device development for two days of technical exchange, collaboration, and discussion around the future of semiconductor modeling and simulation. By attending ICMC 2026, participants will have the opportunity to: • Engage in discussions shaping the evolution of compact models • Learn from leading academic researchers and industry experts • Explore technical sessions focused on real-world applications and emerging technologies • Connect with peers across academia, foundries, EDA, and device engineering • Participate in poster sessions, networking opportunities, and collaborative discussions Hosted aboard the iconic Queen Mary in Long Beach, attendees will experience a venue unlike any other conference setting. Once a renowned transatlantic ocean liner and historic World War II troopship, the Queen Mary now serves as a floating hotel and event destination rich in history, architecture, and atmosphere. With less than two months remaining, now is the time to finalize your plans and join the conversations advancing compact modeling technologies and applications. We look forward to welcoming you to Long Beach! View the Program Register Now Conference Sponsors Media Sponsors Industry Sponsors

[Lecture 13-16] supplementary by Prof. Kim

Prof. Kwantae Kim, Analog Integrated Circuits at Aalto University, recorded additional videos that cover walkthroughs of the CAD exercises in his Integrated Analog Systems course. These videos should provide useful guidance for ADC design simulation and verification practice! 

• Integrated Analog Systems D - Lecture 13S CAD (Bootstrapped Sampling Switch)
  https://www.youtube.com/watch?v=VSDzmijax3c
• Integrated Analog Systems D - Lecture 14S CAD (Linearity and FFT)
  https://www.youtube.com/watch?v=qwJ_tlZTaq8
• Integrated Analog Systems D - Lecture 15S CAD (Transient Noise and VerilogA Modeling)
  https://www.youtube.com/watch?v=YW2nnI3DD_c
• Integrated Analog Systems D - Lecture 16S CAD (ADC ENOB Verification)
  https://www.youtube.com/watch?v=BIFXidfTYxE

Visit also webpage: https://kwantaekim.github.io

[PDF Book] FreeCAD Manual

 

FreeCAD Manual - PDF Book by Yorik Van Harve

The Savvy Engineer Academy

May 9, 2026

Reading the FreeCAD Manual is one of the best ways to build a strong foundation in FreeCAD and improve your overall design skills. While video tutorials and quick guides can help with basic tasks, a complete manual provides structured knowledge that helps you understand the software more deeply and use it more effectively.

For students, hobbyists, and future engineers, the manual provides a solid learning path that supports long-term growth. Since FreeCAD is widely used for 3D printing, mechanical design, and open-source engineering projects, mastering it can also open new opportunities for creativity and technical development.

Overall, reading the FreeCAD Manual gives you the knowledge, efficiency, and confidence needed to create professional-quality designs successfully. CLICK HERE to Download this Book!

[QEMU 11.0] Brings New RISC-V Extensions, Fixes

QEMU 11.0 Brings New RISC-V Extensions and Fixes

The latest release of the QEMU emulator, version 11.0, is out and brings with it support for the RISC-V Zilsd, Zclsd, Zalasr, and Smpmpmt extensions, plus various compatibility and security fixes.

“We’d like to announce the availability of the QEMU 11.0.0 release. This release contains 2500+ commits from 237 authors,” the project maintainers write of the new release. “Thank you to everybody who contributed to this release, whether that was by writing code, reporting bugs, improving documentation, testing, or providing the project with CI resources. We couldn’t do these without you!”

The latest QEMU release brings with it support for four new extensions to the free and open RISC-V instruction set architecture: Zilsd and Zclsd, RV32-exclusive extensions to add register pair load and store instructions by reusing existing RV64-only instruction encodings; Zalasr, an atomic load-acquire store-release extension; and Smpmpmt, which provides a memory attribute control mechanism analogous to the RV64-only Rvpmt using PMP registers.

The full changelog is available on the QEMU wiki; releases are available on the project website, with full source code available on GitLab under the reciprocal GNU General Public Licence 2 or later.

Copyright © 2026 The Free and Open Source Silicon Foundation C.I.C., All rights reserved.

 

The Free and Open Source Silicon Foundation C.I.C.

Unit C5 Tenterfields Business Park

Halifax, HX2 6EQ

United Kingdom

[paper] FDSOI Based Cryogenic Circuit

Tapas Dutta, Fikru Adamu-Lema, Djamel Bensouiah, German Cherstvov, Plamen Asenov,

and Asen Asenov

FDSOI Based Cryogenic Circuit Performance Enhancement 

Using Back Biasing and Threshold Voltage Engineering

IEEE Journal of the Electron Devices Society (2026)

DOI 10.1109/JEDS.2026.3691285

Device  Modelling  Group,  University of Glasgow, UK
Pramana  Modelling  Labs,  Glasgow, UK
School of  Engineering,  University of Glasgow, UK
Semiwise  Ltd.,  Glasgow, UK

Synopsys,  Glasgow, UK

Abstract : In this work, we use predictive cryogenic spice based compact models derived using a process design kit re-centering approach for 22 nm FDSOI technology to analyze the impact of back-gate biasing on circuit performance. We focus on analysis of power-delay trade-offs while varying the supply voltage at room and cryogenic temperature (4K). We show that back-biasing is necessary to mitigate the effects of the higher threshold voltages observed at cryogenic temperature. We further show that simple “threshold voltage engineering” has the potential to provide much better performance, compared to room temperature.

Fig : IDS −VGS characteristics for different VBG going to much higher values 

than the previous sections (without applying anyVth shift).

Acknowledgement : We are grateful to GlobalFoundries for providing the 22FDX PDK and allowing us to customize it for cryogenic temperature operation. The device measurements were performed by Incize SRL, Belgium. This work was supported partially by Innovate UK funded project “Development of Cryo-CMOS to enable the next generation of scalable quantum computers” under the grant number of 10006017 and was also partially supported by Semiwise Ltd, UK.