Recent Compact Modeling Papers

[1] Hao Su, Yunfeng Xie, Yuhuan Lin, Haihan Wu, Wenxin Li, Zhizhao Ma, Yiyuan Cai, Xu Si, Shenghua Zhou Guangchong Hu, Yu He Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu, and Kai Chen; "Characterizations and Framework Modeling of Bulk MOSFET Threshold Voltage Based on a Physical Charge-Based Model Down to 4 K." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 733-736. IEEE, 2024. doi: 10.1109/ESSERC62670.2024.10719583

[2] Tung, Chien-Ting, Sayeef Salahuddin, and Chenming Hu; "A SPICE-Compatible Neural Network Compact Model for Efficient IC Simulations." In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04. IEEE, 2024.

[3] Jana, Koustav, Shuhan Liu, Kasidit Toprasertpong, Qi Jiang, Sumaiya Wahid, Jimin Kang, Jian Chen, Eric Pop, and H-S. Philip Wong; "Modeling and Understanding Threshold Voltage and Subthreshold Swing in Ultrathin Channel Oxide Semiconductor Transistors." In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04. IEEE, 2024.

[4] Manganaro, Gabriele. "Rethinking mixed-signal IC design." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 552-556. IEEE, 2024

[5] Wager, John F., Jung Bae Kim, Daniel Severin, Zero Hung, Dong Kil Yim, Soo Young Choi, and Marcus Bender; "Dual-Layer Thin-Film Transistor Analysis and Design." IEEE Open Journal on Immersive Displays (2024).

[C4P] Advanced FETs: Design, Fabrication and Applications

Call for Papers: Special MDPI  Issue 

"Advanced Field Effect Transistors: Design, Fabrication and Applications"

Deadline for manuscript submissions: 31 July 2021.

Dear Colleagues,

Planar MOS Field Effect Transistors (MOSFETs) were invented by Atalla and Kahng in 1959. After a decade, the MOSFETs entered mass production, as basic building blocks of P-, N-, and CMOS integrated circuits (ICs). Until the end of the twentieth century, MOSFET performance was largely improved by the implementation of so-called scaling rules. An exponential growth in the time of the transistor number per chip (observation formulated as Moore law) was achieved. This, together with advantageous characteristics and a nice feature of the planar MOSFETs allowing one to design the ICs by defining a width/length ratio, led to the great success of the CMOS technology on Si and SOI substrates.

However, starting from the 90 nm node, it has been observed that the standard scaling does not sufficiently translate into MOSFET performance improvement. Moreover, some device characteristics become degraded, e.g. gate leakage, channel leakage, variability and reliability. This has led to the development of preventative measures (e.g. high-k dielectrics) or performance boosters (e.g. channel strain engineering and channel materials). Furthermore, 2D and 3D multi-gate FETs were introduced to improve gate control over the channel and increase the channel aspect ratio. Multi-gate FETs are the only option for the 5nm node, which is expected soon, whereas they will have to be replaced by surrounding gate FETs for the 3nm node. For the past few years, the attention of researchers has been attracted by steep-subthreshold slope devices, enabling the reduction of supply voltage. A need for devices for quantum computing has appeared. FETs and HEMTs, for very high frequency applications, GaN, SiC and FETs for high voltage, high power, high temperature applications, and many other FET types, are in use or under development as a micro- and nanoelectronics reply to electronics needs in different domains.

There are many issues regarding the design, fabrication and applications of advanced field effect transistors. It is my pleasure to invite you to share your expertise in this Special Issue. Full papers, communications and reviews are all welcome.

Dr. Daniel Tomaszewski, ITE, Warsaw (PL)
Special Issue Guest Editor

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