[paper] Local Variability Evaluation on Effective Channel Length

Juan Pablo Martinez Brito, Graduate Student Member, IEEE, 

and Sergio Bampi, Senior Member, IEEE

Local Variability Evaluation on Effective Channel Length

Extracted with Shift-and-Ratio Method

IEEE TED, vol. 67, no. 11, pp. 4662-4666, Nov. 2020

doi: 10.1109/TED.2020.3017178

Abstract: In this study, the local variation of the effective channel reduction parameter (ΔL=Lm−Leff) of a MOSFET is extracted by means of the traditional shift-and-ratio (SAR) method. ΔL is then correlated with the threshold voltage difference (ΔVTH) between the device under test (DUT) and the reference device. It is demonstrated that there exists an optimal VG range for extracting reliable values of L through the SAR method. Statistical data analysis shows that for R≈ (Llong/Lshort)≈25, better results are achieved since the value of σ(ΔL) varies typically as the reciprocal 1/√ W. The test structure used in this work is a Kelvin-based 2-D addressable MOSFET matrix implemented in 180-nm bulk CMOS technology. The sample space is of 2304 devices divided into nine subgroups of 256 same size closely placed nMOSFETs.

Fig: (a) Full circuit micrograph (b) MOSFET Matrix structure (c) Zoomed-in view at DUTs 

Acknowledgment: The authors would like to thank and acknowledge the Brazilian public company CEITEC S.A. Semiconductors for the measurement infrastructure, the CAD Support Center (NSCAD) at Federal University of Rio Grande do Sul (UFRGS) for electronic design automation (EDA) support, and Silterra Inc. for the silicon prototyping services.

[paper] GCC Method for Determining MOSFET VTH

Matthias Bucher¹, Nikolaos Makris¹, Loukas Chevas¹

Generalized Constant Current Method for Determining MOSFET Threshold Voltage

arXiv:2008.00576v1 (2 Aug 202) 

has been submitted to the IEEE for possible publication

¹ School of Electrical and Computer Engineering, Technical University of Crete

Abstract: A novel method for extracting threshold voltage (VTH) and substrate effect parameters of MOSFETs with constant current bias at all levels of inversion is presented. This generalized constant-current (GCC) method exploits the charge-based model of MOSFETs to extract threshold voltage and other substrate-effect related parameters. The method is applicable over a wide range of current throughout weak and moderate inversion and to some extent in strong inversion. This method is particularly useful when applied for MOSFETs presenting edge conduction effect (subthreshold hump) in CMOS processes using Shallow Trench Isolation (STI).

Fig:  Application of the GCC method in presence of edge conduction phenomenon in STI MOSFETs. A constant current is applied to determine pinchoff voltage for the center transistor in moderate inversion at IC=2. To characterize the edge transistor, imposing a current criterion IC=1E−4 corresponds to ICe≈0.02. Pinchoff voltage (VP) and slope factor n characteristics illustrate the determination of parameters for center and edge transistors.

Acknowledgment: This work was partly supported under Project INNOVATION-EL-Crete

(MIS 5002772).

Article reached 1,000 reads

A. Bazigos, M. Bucher, J. Assenmacher, S. Decker, W. Grabinski and Y. Papananos

An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs

IEEE Transactions on Electron Devices,

vol. 58, no. 11, pp. 3751-3758, Nov. 2011.

doi: 10.1109/TED.2011.2164080

Abstract:

The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implanted devices. The generalized adjusted CC method is based on the theory of the charge-based MOS transistor model. It introduces an adjusted current criterion, depending on VDS , allowing to coherently determine VTH for the entire range of VDS from linear operation to saturation. The method uses commonly available ID versus VG data with focus on moderate inversion. The method is validated with respect to the ideal surface potential model, and its suitability is demonstrated with technology-computer-aided-design data from a 65nm CMOS technology and measured data from a 90nm CMOS technology. Comparison with other widely used threshold voltage extraction methods is provided.

[SSE Paper] Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements

Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements 

Daniel Tomaszewski^a, Grzegorz Głuszko^a, Lidia Łukasiak^b,
Krzysztof Kucharski^a, Jolanta Malesinska^b

^aDivision of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), ul. Okulickiego 5E, 05-500 Piaseczno, Poland 

^bInstitute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warsaw, Poland

Abstract: An alternative method for an extraction of the MOSFET threshold voltage has been proposed. It is based on an analysis of the MOSFET source-bulk junction capacitance behavior as a function of the gate-source voltage. The effect of the channel current on the threshold voltage extraction is fully eliminated. For the threshold voltage and junction capacitance model parameters non-iterative methods have been used. The proposed method has been demonstrated using a series of MOS transistors manufactured using a standard CMOS technology.

Keywords: MOSFET CMOS Threshold voltage Junction capacitance Parameter extraction

Cite: Tomaszewski D et al. Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements. Solid State Electron (2016), http://dx.doi.org/10.1016/j.sse.2016.10.006