K. Xia1 (Senior Member, IEEE)
Symmetric Source and Drain Voltage Clamping Scheme
for Complete Source-Drain Symmetry in Field-Effect Transistor Modeling
in IEEE Transactions on Electron Devices
DOI: 10.1109/TED.2020.3004799
1NXP Semiconductors N.V., Chandler, AZ 85224 USA
Abstract: For structurally symmetric field-effect transistors with respect to the source and the drain, their models should be electrically symmetric about the source-drain interchange. This article shows that the commonly used drain-source voltage clamping technique breaks such a symmetry. This article then presents a symmetric source and drain voltage clamping scheme to solve the problem. The effectiveness of the new scheme is demonstrated by both the planar MOSFET model PSP and the FinFET model BSIM-CMG.
Fig: Fourth order derivative of Ix with respect to Vx during Gummel symmetry test for an n-MOSFET on a 130nm technology. Vg = 1.15V. Vb = 0V. W/L = 10.02μm/0.15μm. Vd = −Vs = Vx. T=27◦C. Vx stepsize is 10mV in the measurement and 0.1mV in the simulation, respectively.