[paper] Printed OTFTs

Non-Quasi-Static modeling of printed OTFTs

Antonio Valletta^1,2, Matteo Rapisarda^1,2, Mattia Scagliotti¹, Guglielmo Fortunato¹, Luigi Mariucci^1,2, Andrea Fabbri², Paolo Branchini² and Sabrina Calvi^1,2,3,4

IEEE J-EDS, 2023, Jul 7

 
1 CNR - Institute for Microelectronics and Microsystems (IMM), via del Fosso del Cavaliere, 100, 00133 Rome, Italy
2 INFN, Sezione di RomaTre, via della Vasca Navale, 00146 Rome, Italy
3 CNR-SPIN UoS di Napoli, Università degli Studi di Napoli Federico II, Dipartimento di Fisica, piazzale Tecchio, 80, 80125, Napoli, Italy
4 Department of Physics University of “Tor Vergata”, via della Ricerca Scientifica 1, 00133, Rome, Italy

Abstract: A non-quasi-static compact model well suited for the simulation of the electrical behavior of printed organic thin-film transistors (OTFTs) is proposed and validated. The model is based on the discretization of the current continuity equation by using a spline collocation approach, while the electrical transport in the organic semiconductor is described by the variable range hopping theory. The model accounts for the presence of parasitic regions that are often found in the layouts of printed OTFTs due to large process tolerances. The model has been implemented in the Verilog-A language and has been validated by a comparison with the capacitance vs. voltage (small signal) characteristics of the devices and measurements made on OTFT-based common-source amplifiers (large signal). A comparison with a quasi-static version of the model is reported. 

FIG: Typical device layout (in scale) of the printed OTFTs and its DC (static) characterization: transfer and output characteristics of an L=100µm W=400µm device measured after light exposure

Aknowledgements: This work has been funded by the Italian National Institute of Nuclear Physics – INFN -5th commission, under the “FIRE” project (2019-2022) and from INFN-CNR national project (PREMIALE 2012) EOS “Organic Electronics for Innovative research instrumentation”.

[paper] SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

Tianshi Liu¹, Hua Zhang¹, Sundar Babu Isukapati², Emran Ashik³, Adam J. Morgan², Bongmook Lee³, Woongje Sung², Ayman Fayed¹, Marvin H. White¹, and Anant K. Agarwal¹

SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

IEEE Journal of the Electron Devices Society, vol. 10, pp. 129-138, 2022, 

DOI: 10.1109/JEDS.2022.315036

   
1 Department of Electrical & Computer Engineering, The Ohio State University, Columbus, OH 43210, USA
2 College of Nanoscale Science and Engineering, State University of New York Polytechnic Institute, Albany, NY 12309, USA
3 Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, NC 27695, USA

Abstract: Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600 V lateral SiC power MOSFETs and low-voltage SiC CMOS devices. It enables application-specific SiC ICs with high power output and work under harsh (high-temperature and radioactive) environments compared to Si power ICs. This work presents the device characteristics, SPICE modeling, and SiC CMOS circuit demonstrations of the first two lots of the proposed SiC power IC technology. Level 3 SPICE models are created for the high-voltage lateral power MOSFETs and low-voltage CMOS devices. SiC ICs, such as the SiC CMOS inverter and ring oscillator, have been designed, packaged, and characterized. Proper operations of the circuits are demonstrated. The effects of the trapped interface charges on the characteristics of SiC MOSFETs and SiC ICs are also discussed.

FIG: Cross-sectional view of the SiC MOSFETs (lot2)

Acknowledgment The authors would like to thank the team at Analog Devices (ADI), Hillview facility for the fabrication of devices and Advanced Research Projects Agency-Energy (ARPA-E). The authors also thank D. Xing for providing the customized gate driver for the dynamic characterizations of the circuits

[paper] SiC MOSFET SPICE Model

Lefdal Hove, Haavard, Ole Christian Spro, Giuseppe Guidi

and Dimosthenis Peftitsis

Improved SiC MOSFET SPICE Model to Avoid Convergence Errors

Materials Science Forum 1004 (July 2020): 856–64

DOI: 10.4028/www.scientific.net/msf.1004.856

Abstract: This paper presents improvements to a SPICE model for a commercially available SiC MOSFET to avoid convergence errors while still providing reliable simulation results. Functionality in the internal part of the model that shapes the transconductance of the device according to its junction temperature and gate-source voltage dependency has been improved to provide a continuous characteristic rather than the initial discontinuous performance. Furthermore, the output characteristics from the initial and the proposed model have been compared to lab measurements of an actual device. The results show that the proposed and initial model provide equally reliable simulation results. However, the proposed model does not run into convergence problems.

References 

[1] X. She, A. Huang, O. Lucia, and B. Ozpineci, Review of Silicon Carbide Power Devices and Their Applications, IEEE Transactions on Industrial Electronics, vol. 64, no. 10, p.8193–8205, (2017).

[2] J. Rabkowski, D. Peftitsis, and H. P. Nee, Silicon carbide power transistors: A new era in power electronics is initiated, IEEE Industrial Electronics Magazine, vol. 6, no. 2, p.17–26, (2012).

[3] A. Stefanskyi, L. Starzak, A. Napieralski, and M. Lobur, Analysis of SPICE models for SiC MOSFET power devices,, 2017 14th CADSM 2017 - Proceedings, p.79–81, (2017).

[4] H. L. Hove, O. C. Spro, D. Peftitsis, G. Guidi, and K. Ljøkelsøy, Minimization of dead time effect on bridge converter output voltage quality by use of advanced gate drivers, 2019 10th ICPE 2019 ECCE Asia, (2019).

[5] N. Mohan, T. Undeland, and W. Robbins, Power Electronics; Converters, Applications, and Design, third ed., Wiley, (2003).

[6] C. Enz, F. Krummenacher, and E. Vittoz, An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Application, Analog Integrated Circuits and Signal Processing, vol. 8, p.83–114, (1995).

[7] M. Bucher, C. Lallement, C. Enz, F. Théodoloz, and F. Krummenacher, The EPFL-EKV MOSFET Model Equations for Simulation Technical Report V2.6,, EPFL, Lausanne, Switzerland, (1999).

[8] B. N. Pushpakaran, S. B. Bayne, G. Wang, and J. Mookken, Fast and accurate electro-thermal behavioral model of a commercial SiC 1200V, 80 mΩ power MOSFET,, Digest of Technical Papers IEEE IPPC, vol. 2015-Octob, p.1–5, (2015).

[paper] Carbon Nanotube Detectors and Spectrometers for the Terahertz Range

Junsung Park¹, Xueqing Liu¹, Trond Ytterdal²

and Michael Shur^1,3 

Carbon Nanotube Detectors and Spectrometers for the Terahertz Range 

Crystals 2020, 10, 601

DOI:10.3390/cryst10070601

¹Department of Electrical, Computer, and Systems Engineering, RPI  Troy, NY 12180, USA
²Department of Electronic Systems, NUST, O.S. Bragstads plass 2a, 7034 Trondheim, N
⁴Electronics of the Future, Inc., Vienna, VA 22181, USA

Abstract: We present the compact unified charge control model (UCCM) for carbon nanotube field-effect  transistors  (CNTFETs)  to  enable the accurate  simulation  of  the  DC  characteristics  and plasmonic terahertz (THz) response  in the  CNTFETs. Accounting for  the ambipolar  nature of the carrier transport (n-type and p-type conductivity at positive and negative gate biases, respectively), we use n-type and p-type CNTFET non-linear equivalent circuits connected in parallel, representing the ambipolar  conduction in the  CNTFETs.  This allows us to present a realistic non-linear  model that is valid across the  entire voltage  range  and is therefore suitable  for  the  CNTFET design. The important  feature  of  the  model  is that  explicit equations for gate  bias,  current,  mobility,  and capacitance with smoothing parameters accurately describe the device operation near the transition from above- to below-threshold regimes, with scalability in device geometry. The DC performance in  the proposed  compact CNTFET  model  is  validated  by  the  comparison between  the  SPICE simulation and the experimental DC characteristics. The simulated THz response resulted from the validated CNTFET model is found to be in good agreement with the analytically calculated response and  also  reveals  the  bias  and  power  dependent  sub-THz  response  and  relatively  wide  dynamic range   for   detection   that   could   be   suitable   for   THz   detectors.   The   operation   of   CNTFET spectrometers  in the THz  frequency  range  is  further  demonstrated  using  the  present  model.  The simulation exhibits that the CNT-based spectrometers can cover a broad THz frequency band from 0.1 to 3.08 THz. The model that has been incorporated into the circuit simulators enables the accurate assessment  of  DC  performance  and  THz  operation.  Therefore,  it  can  be  used  for the design  and performance estimation of the CNTFETs and their integrated circuits operating in the THz regime.  

Fig: Schematic illustration of the simulation circuit for the CNTFET THz detection

with the open boundary condition at the drain.

Funding: This  work  at  RPI  was  supported  by  the  U.S.  Army  Research  Laboratory  under  the  Cooperative Research Agreement (Project Monitor Dr. Meredith Reed) and by the US ONR (Project Monitor Dr. Paul Maki). 

IEEE EDS Delhi Chapter DL: FOSS TCAD/EDA tools for Compact/SPICE Modeling

The IEEE EDS Delhi Chapter, New Delhi, India is conducting a series of the IEEE EDS DL Talks with coming one on June 03, 2020 at 06:00 pm (GMT+05:30, IST)  with following topic:

FOSS TCAD/EDA tools for Compact/SPICE Modeling

Wladek Grabinski 

Senior Member-IEEE MOS-AK Association (EU)

Abstract: Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the MOSFET, FDSOI, FinFET and TFET compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends on the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization to encourage development FOSS CAD tools. 

And the webinar has drawn attention of 150+ online participants

The series of the IEEE EDS DLs are coordinated by:

Professor Mridula Gupta

Chairperson-IEEE EDS Delhi Chapter

Professor & Head of Department of Electronic Science 

University of Delhi South Campus

New Delhi 110021INDIA

Professor  Manoj Saxena

Regional Editor for South Asia, IEEE EDS Newsletter

EDS Distinguished Lecturer and Fellow-IETE, India

Associate Professor, Department of Electronics 

Deen Dayal Upadhyaya College, University of Delhi 

Dwarka Sector-3, New Delhi-110078, India