IEEE 5NANO2024 Conference 25-26th April, 2024

IEEE 5NANO2024

2024 IEEE International Conference on Nanoelectronics, Nanophotonics,
Nanomaterials, Nanobioscience & Nanotechnology

25th & 26th April 2024

VISAT Engineering College

Elanji, Ernakulam, Kerala, India - 686 665.

The IEEE 5NANO2024 International Conference is going to be dynamic and informative as it provides the premier interdisciplinary forum for researchers, practitioners and educators to present and discuss the most recent innovations, trends, practical challenges encountered, and the solutions adopted in the field of Nanotechnology. The theme of the conference is: “Future Challenges and Advanced Innovations in Nanotechnology”

Contact 5NANO2024:

Dr. T.D.Subash, Conference Organizing Chair - 5NANO2024,
VISAT Engineering College,
Elanji, Ernakulam, Kerala, India - 686 665

Tel: +91 9447691397, +91 9486881397.
E-mail: deanresearch@visat.ac.in, tdsubash2007@gmail.com, 5nano2k24@gmail.com

Website: https://www.5nano2024.com

[C4P] MIXDES 2024

The MIXDES conference series started in Dębe near Warsaw in 1994 and has been organized yearly in the most interesting Polish cities. In 2024 we would like to continue the tradition of inviting you to the most attractive places in Poland and the conference will take place in Gdańsk between June 27-29, 2024

In short period of time the conference has become an important event in the Central Europe allowing to discuss the recent research progress in the field of design, modelling, simulation, testing and manufacturing in various areas such as micro- and nanoelectronics, semiconductors, sensors, actuators and power devices as well as their interdisciplinary applications.

The topics of the MIXDES 2024 Conference include:

• Design of Integrated Circuits and Microsystems
  Design methodologies. Digital and analog synthesis. Hardware-software co-design. Reconfigurable hardware. Hardware description languages. Intellectual property-based design. Design reuse.
• Thermal Issues in Microelectronics
  Thermal and electro-thermal modelling, simulation methods and tools. Thermal mapping. Thermal protection circuits. 
• Analysis and Modelling of ICs and Microsystems
  Simulation methods and algorithms. Behavioral modelling with VHDL-AMS and other advanced modelling languages. Microsystems modelling. Model reduction. Parameter identification.
• Microelectronics Technology and Packaging
  New microelectronic technologies. Packaging. Sensors and actuators.
• Testing and Reliability
  Design for testability and manufacturability. Measurement instruments and techniques. 
• Power Electronics
  Design, manufacturing, and simulation of power semiconductor devices. Hybrid and monolithic Smart Power circuits. Power integration.
• Signal Processing
  Digital and analogue filters, telecommunication circuits. Neural networks. Artificial intelligence. Fuzzy logic. Low voltage and low power solutions.
• Embedded Systems
  Design, verification and applications.
• Medical Applications
  Medical and biotechnology applications. Biometrics. Thermography in medicine

Call for Papers and Contributions

A call is made for papers, contributions and other conference activities on the topics mentioned above. Full papers should be submitted till March 1, 2024 - only in electronic form (MS Word, RTF, Open Office Writer, LaTeX, together with a generated PDF file).

The paper submission form and required format is available on our Web page. Authors are asked to indicate the topic into which their papers fall. The papers will be reviewed by at least two referees from the International Programme Committee. The papers will be published in the proceedings from the author's electronic submission.

Tutorials and Special Sessions - Call for Proposals

Several tutorials/special sessions will be held prior to the conference. Authors willing to propose a tutorial at MIXDES 2024 are invited to send a proposal to the Organizing Committee. The proposal should consist of a three-page summary including tutorial title, name and affiliation of the lecturer(s), tutorial objectives and audience, topical outline and provisional schedule of the tutorial.

INUP-i2i - Idea to Innovation

INUP-i2i

Indian Nanoelectronics Users’ Programme

Idea to Innovation

Ministry of Electronics and Information Technology – MeitY, with the long-term vision of improving skilled manpower in the areas of micro and nanoelectronics had established the Indian Nanoelectronics Users’ Programme (INUP) about a decade back. The initiative enabled the researchers to travel from the country's remotest locations and implement their ideas at the state-of-art nanofabrication and characterization facilities available at Centres of Excellence established at the Indian Institute of Science Bangalore and Indian Institute of Technology Bombay. Over the years, the brand INUP has caught the imaginations of the scholars from numerous technical colleges and universities who could not afford to have such facilities to perform research. The user base grew from the first (2008-2014) to the second 2014-2019) phases of implementation. Thousands of researchers have received hands-on training at various levels in such state-of-art facilities in the multi-disciplinary areas of micro/nanoelectronics. Hundreds of them could implement their research ideas and produce scientific and technological outputs. The initiative resulted in unprecedented benefits to the budding scholars in developing cutting-edge research prototypes, which was found to be way beyond the traditional soft-teaching pathways through textbook knowledge. The initiative also helped the participants write and submit research proposals, budget the same, implement ideas at the ground level, schedule project work, submit project reports, prepare scientific manuscripts, and develop the devices.

INUP-i2i OBJECTIVES

• Enhance R&D ecosystem in the area of nanoelectronics by leveraging the Nano centres established by MeitY.
• Conduct training/workshops in the field of Nanoelectronics for wider dissemination of knowledge.
• Support the exploratory and innovative research for development of technologies in Nanoelectronics
• Mentor startups for commercialization of nanotechnologies.
• Conduct Hackathons/Grand Challenge targeting societal applications to develop Nano engineered solutions.

Hands-on training workshop are organized on the following different themes:

• Sensors and Microfluidics
• Organic Electronics
• 2D materials and devices
• Logic & Memory Devices
• Spintronics
• Compound Semiconductor Devices
• Photovoltaics
• MEMS

[read more...]

[Proceedings] MNDCS 2023

Micro and Nanoelectronics Devices, Circuits and Systems

Select Proceedings of MNDCS 2023

Part of the book series: Lecture Notes in Electrical Engineering (LNEE, volume 1067) DOI: 10.1007/978-981-99-4495-8

Editors: Trupti Ranjan Lenka, Samar K. Saha, Lan Fu

This book presents select proceedings of the International Conference on Micro and Nanoelectronics Devices, Circuits and Systems (MNDCS-2023). The book includes cutting-edge research papers in the emerging fields of micro and nanoelectronics devices, circuits, and systems from experts working in these fields over the last decade. The book is a unique collection of chapters from different areas with a common theme and is immensely useful to academic researchers and practitioners in the industry who work in this field.

[book] Tunneling Field Effect Transistors

Tunneling Field Effect Transistors
Design, Modeling and Applications

Edited By T. S. Arun Samuel, Young Suh Song, Shubham Tayal, P. Vimala, Shiromani Balmukund Rahi

ISBN 9781032348766
1st Edition; 316 Pages; 15 Color & 232 B/W Illustrations
June 8, 2023 by CRC Press

Description: This book will give insight into emerging semiconductor devices from their applications in electronic circuits, which form the backbone of electronic equipment. It provides desired exposure to the ever-growing field of low-power electronic devices and their applications in nanoscale devices, memory design, and biosensing applications.

Tunneling Field Effect Transistors: Design, Modeling and Applications brings researchers and engineers from various disciplines of the VLSI domain to together tackle the emerging challenges in the field of nanoelectronics and applications of advanced low-power devices. The book begins by discussing the challenges of conventional CMOS technology from the perspective of low-power applications, and it also reviews the basic science and developments of subthreshold swing technology and recent advancements in the field. The authors discuss the impact of semiconductor materials and architecture designs on TFET devices and the performance and usage of FET devices in various domains such as nanoelectronics, Memory Devices, and biosensing applications. They also cover a variety of FET devices, such as MOSFETs and TFETs, with various structures based on the tunneling transport phenomenon.

The contents of the book have been designed and arranged in such a way that Electrical Engineering students, researchers in the field of nanodevices and device-circuit codesign, as well as industry professionals working in the domain of semiconductor devices, will find the material useful and easy to follow.

Table of Contents:

Chapter 1. Challenges of Conventional Cmos Technology in Perspective of Low Power Applications

Chapter 2. Basic Science and Development of Subthreshold Swing Technology

Chapter 3. Historical Development of MOS technology to Tunnel FETs

Chapter 4. Modeling of Gate Engineered TFETs: Challenges and Opportunities

Chapter 5. Modeling of Gate Engineered TFET: challenges and Opportunities.

Chapter 6. Evolution of Heterojunction Tunnel Field Effect Transistor and its Advantages

Chapter 7. Analog / RF performance analysis of TFET device

Chapter 8. DC Analysis and Analog/HF Performances of GAA-TFET with Dielectric Pocket

Chapter 9. Investigation on Ambipolar Current Suppression in Tunnel FETs

Chapter 10. Analysis of Channel Doping Variation on Transfer Characteristics to High Frequency performance of F-TFET

Chapter 11. Design of Nanotube TFET Biosensor

Chapter 12. TFET-based Memory Cell Design with Top-down Approach

Chapter 13. Designing of nonvolatile memories utilizing Tunnel Field Effect Transistor

Chapter 14. TFET-based Universal

Chapter 15. TFET-based Level Shifter Circuits for Low Power Applications

[paper] p-Type Doped Silicene-based

Mu Wen Chuan, Munawar Agus Riyadi, Afiq Hamzah, Nurul Ezaila Alias, Suhana Mohamed Sultan, Cheng Siong Lim, Michael Loong Peng Tan

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

PLoS ONE 17(3): e0264483.: March 3, 2022

DOI: 10.1371/journal.pone.0264483

   
Universiti Teknologi Malaysia, Skudai, Johor, Malaysia
Diponegoro University, Semarang, Indonesia

Abstract: Moore’s Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.

Fig: Schematic diagrams of AlSi3 FET: (a) the structure and 

(b) the ToB nanotransistor circuit model. 

Acknowledgements: 1.) Michael Tan Loong Peng - Ministry of Higher Education (MOHE) of Malaysia through the Fundamental Research Grant Scheme(FRGS/1/2021/ STG07/ UTM/02/3); The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript. 2.) Munawar Agus Riyadi - World Class Research Universitas Diponegoro (WCRU) 2021 Grant no. 118-16/UN7.6.1/PP/2021; The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.

[paper] A Review of Sharp-Switching Band-Modulation Devices

Sorin Cristoloveanu¹, Joris Lacord², Sébastien Martinie², Carlos Navarro³, Francisco Gamiz³, Jing Wan⁴, Hassan El Dirani¹, Kyunghwa Lee¹ and Alexander Zaslavsky⁵

A Review of Sharp-Switching Band-Modulation Devices

Micromachines 2021, 12, 1540.

DOI: 10.3390/mi12121540

   
1 IMEP-LAHC, Université Grenoble Alpes (F)
2 CEA, LETI, MINATEC Campus (F)
3 CITIC-UGR, University of Granada (SP)
4 Fudan University, Shanghai (CN)
5 Brown University, Providence (US)

Abstract: This paper reviews the recently-developed class of band-modulation devices, born from the recent progress in fully-depleted silicon-on-insulator (FD-SOI) and other ultrathin-body technologies, which have enabled the concept of gate-controlled electrostatic doping. In a lateral PIN diode, two additional gates can construct a reconfigurable PNPN structure with unrivalled sharp-switching capability. We describe the implementation, operation, and various applications of these band-modulation devices. Physical and compact models are presented to explain the output and transfer characteristics in both steady-state and transient modes. Not only can band-modulation devices be used for quasi-vertical current switching, but they also show promise for compact capacitorless memories, electrostatic discharge (ESD) protection, sensing, and reconfigurable circuits, while retaining full compatibility with modern silicon processing and standard room-temperature low-voltage operation.

Fig: Average subthreshold swing SS vs. normalized ION plot. 

Green points indicate CMOS-compatible materials.

Acknowledgements: The European authors are grateful for support from the EU project REMINDER (H2020-687931). Alexander Zaslavsky acknowledges the support of the U.S. National Science Foundation (award QII-TACS-1936221).

10th All-Russia MES-2021 Conference

10th All-Russia Science and Technology Conference

Problems of Advanced Micro- and Nanoelectronic Systems Development 

MES-2021

March - November 2021

Moscow | Zelenograd

MES-2021 is dedicated to urgent issues of design automation of microelectronic systems, SoC, IP-blocks and a new element base of micro-and nanoelectronics. These issues have been and remain actual to science and technology, as evidenced by the major topics of the Annual International Conference on CAD and the development of micro-and nanoelectronic devices. MES is the largest conference in the field of CAD microelectronics in Russia and CIS countries. Proceedings of the MES conference is included in HAC list (issue 23.03.2021, pos. 2017) of Russian scientific journals, where should be published the main results of the PhD and DSc theses.

The upcoming 10th MES-2021 conference will be held mainly in the correspondence format, starting on March 01, 2021, and it will be concluded with its plenary session in November 2021.

Key discussion topics

1. Theoretical aspects of micro-and nanoelectronic systems (MES).
2. Methods and tools of design automation for micro-and nanoelectronic circuits and systems (VLSI CAD).
3. Experience of development of digital, analog, digital to analog, radio functional blocks of VLSI.
4. Features of VLSI design for nanometer technologies.
5. SoCs for advanced radioelectronic equipment.
6. Exhibition and presentation of commercial products.

Fields of interest of the conference include (but is not limited to) the following topics of relevant studies of VLSI design and VLSI design automation techniques:

Design

1. Circuits and Systems based on nanometer technologies

2. Systems on Chip

3. Digital VLSI Design

4. Design of analog functional blocks and radio VLSI

5. Design of mixed-signal VLSI

6. Methods of structural synthesis of analog, digital and mixed VLSI and complex functional blocks

7. Specialized (resistant to special effects, photosensitivity, etc.) VLSI

Simulation

1. Methods of simulation of digital, analog and mixed circuits and systems

2. Methods for radio VLSI simulation

3. Structural, logical, circuit, mixed and layout simulation

4. Methods for generating models and macromodels for VLSI CAD

5. Device and Technology simulation

6. Behavioral simulation

Information processing methods

1. Information coding

2. Digital data processing

3. Use of artificial intelligence methods, neural networks, etc. in micro- and nanoelectronic system designs

4. Unconventional arithmetic

5. High-performance computers

The development of nanoelectronic systems on new principles

1. Nanomagnetic storage devices

2. Magnetosensor structures

Call for participation in the conference program

I stage - After registration at least one of the co-authors of the report one can send an article. To do this, using their registration data, please log in (see upper right corner of screen). Fill in all required fields. On the website you should send a file containing the main text of the article (in Russian or English) and an extended abstract in English (if the main text is in Russian) or a simple abstract in Russian (if the main text of the article in English). Requirements for the articles sent to MES.

II stage - sending additional documents only for the articles, which have been reviewed and accepted to the conference program.

Visit the 10th MES-2021 conference website at: http://www.mes-conference.ru/index.php

[Workshop] The Future of Nanoelectronics Devices and Systems Beyond Moore

“The Future of Nanoelectronics Devices and Systems Beyond Moore” 

Workshop on August 31, 2021

This one-day Workshop, supported; IEEE, will be devoted to the update of the European contribution to the IRDS Roadmap in the field of More than Moore, Beyond CMOS and Emerging Materials. The main challenges, most promising technologies, needed research efforts and possible applications will be presented in the following sessions; renown EU experts:

• Beyond CMOS and Emerging Materials
• Trends in Beyond CMOS
  Clivia Sotomayor-Torres; ICN2 and Jouni Ahopelto; VTT
• 2D semi-metal to semiconductor transition devices and/or doping of 2D materials
  Farzan Gity; Tyndall
• GeSn/Ge vertical nanowire GAA FETs
  Qing-Tai Zhao; FZJ
• Flexible electronics with 2D materials
  Zhenxing Wang; AMO
• Presentation of the new IRDS More than Moore Roadmap
  Mart Graef; TU Delft
• Energy Harvesting for Autonomous Systems
• Summary of the IRDS Energy Harvesting for Autonomous Systems White Paper
  Gustavo Ardila; UGA
• Energy sustainability problems of IoT networks
  Thomas Skotnicki; CEZAMAT
• Contribution of triboelectricity for kinetic energy harvesting using electrostatic transduction
  Philippe BASSET; ESIEE, Paris
• Smart Sensors
• Summary of the IRDS Smart Sensors White Paper
  Alan O’Riordan; Tyndall
• Sensing at the Edge: Challenges and Opportunities
  Adrian Ionescu; EPFL
• Smart Sensors and Systems for environment and human exposure monitoring
  Carmen Moldovan; IMT
• Smart Energy
• Summary of the IRDS Smart Energy White Paper
  Mikael Ostling; KTH
• Smart power devices based Wide Bandgap semiconductors
  William Vandendaele; CEA LETI
• Materials and substrates for future power devices
  Joff Derluyn; Soitec BU EpiGaN
• Flexible/Wearable Electronics
• Roadmap of Flexible Electronics: Challenges and Possible Solutions; Summary of the IRDS White Paper
  Benjamin Iñiguez; URV
• Schottky barrier and organic devices for neuromorphic circuits
  Laurie Calvet; CNRS; Université Paris Saclay
• New strategies for sustainable electronics
  Elvira Fortunato; UNL

Program: will be available soon

Location information

Registration: free of charge but mandatory; More information: 

contact@sinano.eu and https://eurosoiulis2021.sciencesconf.org/

[paper] 2D Charge Density Wave Phases

Machine-Intelligence-Driven High-Throughput Prediction of 2D Charge Density Wave Phases

Arnab Kabiraj and Santanu Mahapatra*

J. Phys. Chem. Lett. 2020, 11, 15, 6291–6298

Publication Date:July 22, 2020

DOI: 10.1021/acs.jpclett.0c01846

*Nano-Scale Device Research Laboratory, IISc Bangalore, India

Abstract: Charge density wave (CDW) materials are an important subclass of two-dimensional materials exhibiting significant resistivity switching with the application of external energy. However, the scarcity of such materials impedes their practical applications in nanoelectronics. Here we combine a first-principles-based structure-searching technique and unsupervised machine learning to develop a fully automated high-throughput computational framework, which identifies CDW phases from a unit cell with inherited Kohn anomaly. The proposed methodology not only rediscovers the known CDW phases but also predicts a host of easily exfoliable CDW materials (30 materials and 114 phases) along with associated electronic structures. Among many promising candidates, we pay special attention to ZrTiSe4 and conduct a comprehensive analysis to gain insight into the Fermi surface nesting, which causes significant semiconducting gap opening in its CDW phase. Our findings could provide useful guidelines for experimentalists.

Fig: Top view of TaSe₂-H 3×3_ɸ-1.

Mini-Colloquium (MQ) on Nanoelectronics

AGENDA
DATE: Saturday Aug. 26, 2016

VENUE: IIT Kanpur L16

This Mini-Colloquium (MQ) on Nanoelectronics is being hosted by the IEEE Electron Device Society UP Chapter in collaboration with the Department of Electrical Engineering at IIT Kanpur. Distinguished speakers from renowned universities will be presenting on wide range of topics in Nanoelectronics. The MQ will be organized into 1 hour talks by the speakers. The agenda would be as follows:

Time	Topic	Speaker
9:00 - 9:15	Inauguration
9:15 - 9:30	High Tea
9:30 - 10:30	Nanotransistors with 2D materials: Opportunities and Challenges	Prof. Navkanta Bhat IISc
10:30 - 11:30	Revisiting gate C-V characterization for high mobility semiconductor MOS devices	Prof. Anisul Haque East West Univ.
11:30 - 11:45	Tea
11:45 - 12:45		Prof. V. Ramgopal Rao IIT Delhi
12:45 - 14:15	Lunch
14:15 - 15:15	ASM-HEMT - First Industry Standard Compact Model for GaN HEMTs	Prof. Yogesh Singh Chauhan IIT Kanpur
15:15 - 16:15	Spintronics - Perspectives and Challenges	Prof. Brajesh Kumar Kaushik IIT Roorkee
16:15 - 16:30	Tea
16:30 - 17:30	Advanced Hetero structure based Nano Scale MOSFETs	Prof. Chandan Kumar Sarkar Jadavpur Univ.

Coordinator: Dr. Yogesh S.Chauhan IIT Kanpur, India
Website: http://www.iitk.ac.in/nanolab/MQ/index.html