[paper] Logarithmic Power Detector

Patrick Fath and Harald Pretl

A 44-GHz Logarithmic Power Detector with 62 dB Dynamic Range and –56 dBm Sensitivity 

in 130-nm SiGe BiCMOS Using Open-Source EDA

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 

Fukuoka, Japan, October 2026

 

Institute for Integrated Circuits and Quantum Computing, JKU Linz, Austria

 

Abstract: This paper presents a 44-GHz logarithmic RF power detector implemented in the open-source IHP SG13G2 130nm SiGe BiCMOS OpenPDK using exclusively open-source EDA tools. The proposed detector is based on a six-stage successive detection logarithmic video amplifier architecture with integrated square-law detectors, followed by a transimpedance amplifier and an output buffer. To achieve both low noise and high speed, two different limiting-amplifier topologies are employed within the successive detection logarithmic video amplifier, namely a low-noise differential common-emitter input stage and high-speed Cherry-Hooper stages. A tunable proportional-to-absolute-temperature constant-gm bias generator is used to reduce the temperature dependency of the amplifier gain, while duty-cycled operation is supported to lower the average power consumption. Post-layout simulations show a passband gain of 64 dB, a frequency range from 0.15 GHz to 44.7 GHz, a sensitivity of-56 dBm, and a dynamic range of 62 dB. In addition, RF stability is verified over the investigated frequency range, and the detector achieves an estimated video bandwidth of 114 MHz. The total power consumption is 95.7 mW in continuous operation and is reduced to 48.1 mW in duty-cycled operation. The active area is 0.43 mm^2, while the die size including pads is 1.4×1.2 mm^2. These results demonstrate that competitive wideband logarithmic RF power detectors extending into the mm-wave range can be realized using open-source design infrastructure.

Fig. (a) Transient response of the detector under duty-cycled operation, showing pon (dashed gray) and Vlog, out (solid blue). (b) Layout of the detector (1.4×1.2 mm^2) with the individual building blocks outlined 

[paper] Cryo 1T1R HfO2-Based RRAM

Emilio Pérez-Bosch Quesada, Alberto Mistroni, Ruolan Jia, Keerthi Dorai Swamy Reddy, Markus Fritscher, Felix Reichmann, Oliver Skibitzki, Juan Bautista Roldán, Helena Castán, Salvador Dueñas, Christian Wenger, Eduardo Pérez

Enabling Quantum-Compatible Nonvolatile Memory: Cryogenic Evaluation 

of 1T1R HfO2-Based RRAM From 300 to 1.5K

Advanced Electronic Materials 12, no. 19 (2026): e00798

DOI: 10.1002/aelm.202500798

ABSTRACT: To enable compact quantum computing systems, cryogenically compatible CMOS-based non-volatile memories are required. In this work, we investigate 1-transistor–1-resistor (1T1R) resistive random-access memory (RRAM) devices over an extended temperature range, including previously unexplored cryogenic regimes. To enhance storage density, we explore a multilevel-cell approach via multilevel programming. As temperature decreases, the low-resistance state (LRS) effective conductance increases, improving state separation but also leading to higher LRS currents and increased reset voltages required for reliable switching to the high-resistance state (HRS), resulting in incomplete filament rupture and a broader HRS distribution. Through independent characterization of the access nMOS transistor, we identify transistor temperature dependence as the dominant factor governing LRS evolution, while extraction of the intrinsic metal–insulator–metal (MIM) behavior reveals an opposite trend, with decreasing conductivity at lower temperatures. Based on these insights, we implement an optimized programming strategy for cryogenic operation by tuning the nMOS gate bias during set, reducing LRS currents, particularly in intermediate and high conductance states, while preserving state separation, narrowing the HRS distribution, and lowering reset voltages. Overall, this work establishes a robust and scalable approach for reliable 1T1R operation at cryogenic temperatures and provides a key step toward nonvolatile memory integration in quantum computing architectures.

FIG: a) Cryogenic setup used to characterize the RRAM devices under study, b) RRAM array containing a total of 32 1T1R devices individually addressable, and c) schematic description of the forming, set, and reset operations carried out during this work.

Acknowledgments: This work was financially supported by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Project 551916740.

[Innovation Showcase] European Reference Fab Blueprint at SEMICON Europa 2026

N. Herfurth, S. Reith, R. Scholz

From Pilot-Line Readiness to Trusted Deployment: A Cloneable Manufacturing Blueprint 

for European Semiconductor Resilience

SEMICON Europa 2026

Innovation Showcase (pre-recorded talk), Executive Forum, Hall C1

Friday, 13 November 2026, 11:15

1) IHP GmbH - Leibniz Institute for High Performance Microelectronics, Technology, Frankfurt/Oder, (D)
2) Hochschule Rhein Main, University of Applied Sciences and Arts, Wiesbaden (D)

 

The talk is presented by Anna Herfurth on behalf of the authors: Norbert Herfurth, Arnd Weber, Steffen Reith, Anna Herfurth, Rene Scholz, Wladek Grabinski and Torsten Grawunder. It is an independent concept, published through the HEP Alliance and supported by Swissbit AG and Hochschule RheinMain (RheinMain University of Applied Sciences). Version 1 (concept paper, executive summary and Q&A) is online, and Version 2 is in preparation, coming in the next weeks

Abstract: Europe’s semiconductor ecosystem faces a deployment gap. RTOs and pilot lines are essential for developing new technologies, but many security-, safety- and long-lifecycle applications require something different: stable, auditable and repeatable manufacturing capacity at mature nodes, combined with advanced packaging, test and traceability. This contribution presents the European Reference Fab concept as a non-commercial manufacturing blueprint to close that gap: a cloneable 300-mm infrastructure model for 130 nm with an optional evolution path to 65 nm, integrating front-end manufacturing, packaging, chiplet integration, test, open design enablement and auditable process and data flows.The news is not another pilot line or a single national flagship fab. The proposed Reference Fab is an industrial deployment architecture. It defines how mature process modules, open PDKs/ADKs, documented tool flows, traceability mechanisms, MPW and small-series access, and packaging/test capabilities can be combined into a governed manufacturing environment. Clone sites could be implemented as front-end lines, assembly/test hubs or combined facilities, depending on regional and sectoral needs.The concept addresses several bottlenecks in semiconductor adoption. First, it provides a trusted manufacturing route for defence, critical infrastructure, automotive, industrial, med-tech and aerospace applications that do not necessarily require leading-edge nodes but do require long-term availability, provenance and auditability. Second, it creates an industrial endpoint for RTO and pilot-line results, helping promising technologies move from readiness to deployment. Third, it lowers access barriers for SMEs, start-ups and system integrators through open design kits, harmonised design interfaces and fair MPW/small-series schemes. Fourth, it embeds smart-manufacturing principles such as MES-based traceability, inline metrology, SPC/ML-assisted control, documented audit trails and secure data flows from design through manufacturing and final test.The presentation will outline the core architecture of the Reference Fab, the rationale for the 130 nm to 65 nm pathway, the role of packaging-first system integration, and the mechanisms by which open design enablement, auditable manufacturing and workforce development can support trusted electronics, supply-chain resilience and European semiconductor competitiveness.

Biography: Dr.-Ing. Norbert Herfurth is a research group leader, programme coordinator and semiconductor technologist with more than ten years of experience at the interface of microelectronics research, collaborative R&D programmes, open-source chip design, failure analysis and semiconductor strategy. He currently leads the Diagnostics, Sensors & Emerging Modules group at IHP – Leibniz Institute for High Performance Microelectronics in Frankfurt (Oder), Germany, where he is responsible for building and managing a newly established interdisciplinary unit with activities in diagnostics, sensors, photonic and emerging module technologies.His work combines technical depth in semiconductor devices and failure analysis with strategic programme leadership. Before taking on his current group-leader role, he initiated, structured and coordinated several publicly funded collaborative R&D projects in the field of open-source microelectronics, open PDKs and trusted electronics. He has contributed to the development and positioning of Europe’s open-source chip-design ecosystem, including work around IHP’s open 130 nm PDK activities and European discussions on open-source EDA, design access and semiconductor sovereignty. Norbert Herfurth earned his doctorate in electrical engineering from Technische Universität Berlin, where his research focused on semiconductor devices and silicon-level failure analysis. During his academic work, he operated and developed advanced diagnostic and failure-analysis methods, including photon-emission microscopy, thermal and optical techniques, probing methods and cleanroom-based experimental workflows. Since 2024, he has also been a lecturer at Technische Universität Berlin for the course “Debug of Integrated Circuits on Silicon Level”, which combines IC debug, failure analysis and hands-on diagnostic methods. In addition to his technical work, he has extensive experience in consortium building, project governance and strategic technology communication. He has led or coordinated multiple BMBF-funded collaborative projects, developed R&D work programmes, managed milestone- and review-driven project structures and worked with partners from research organisations, SMEs, industry, funding bodies and public-sector stakeholders. His current activities include the development of strategic concepts for open and trustworthy semiconductor ecosystems, especially where design enablement, manufacturing access, packaging, test, traceability and trusted electronics intersect. Norbert Herfurth is one of the contributors to the European Reference Fab / Transparent Reference Fab concept, a proposed open, cloneable manufacturing blueprint for trustworthy mature-node semiconductor production in Europe. In this context, he focuses on the connection between open design enablement, auditable manufacturing, trusted electronics, chiplet-aware system integration and the transition from pilot-line readiness to industrial deployment. He is also a founding member of the VDE ITG expert group on trustworthy electronics. His professional interest lies in translating complex semiconductor technology topics into actionable strategies for research, industry and policy stakeholders. This includes open PDKs and open EDA, trusted manufacturing, semiconductor resilience, system-level integration, failure analysis, photonic and electronic diagnostics, and the role of public-interest infrastructure in strengthening Europe’s semiconductor ecosystem.

[workshop] Open Source Analog Chip Design

AT-C³ Training: Introduction to Open Source Analog Chip Design

SILICON ALPS Cluster

24-25 November 2026 

TU Graz, Campus Inffeldgasse

Inffeldgasse 33, 8010 Graz, Austria

This workshop is an excellent opportunity for engineers, researchers, and students who want to gain practical experience in open-source analog chip design and contribute to the emerging open-source semiconductor ecosystem.

About the Training

AT-C³ is launching one of its first hands-on training events, focused on a question that many electronic engineers are asking today: Can an analog integrated circuit be designed, simulated, laid out, and verified using only open-source EDA tools? During this two-day workshop, hosted by Symbiotic EDA, participants will answer this question through practical, hands-on experience. The training guides attendees through the complete analog IC design flow, from schematic capture to a verified physical layout, using modern open-source design tools.

Why Attend?

• Learn the complete open-source analog IC design workflow
• Gain hands-on experience with professional-grade EDA tools
• Explore schematic design, simulation, layout, and verification
• Network with engineers, researchers, and students interested in open-source chip design
• Discover the growing ecosystem around open-source silicon development

Registration Free of Charge

Organizer: SILICON ALPS Cluster

[paper] Cryo MOSFET Gate Capacitance

Sadık İlik, Masoud Babaie, Andrei Vladimirescu and Fabio Sebastiano

Characterization and Modeling of MOSFET Gate Capacitance Under Cryogenic Operation

IEEE Journal of the Electron Devices Society (2026)

DOI 10.1109/JEDS.2026.3745897

1 Delft University of Technology, 2628 CJ Delft (NL)

2 Qutech, 2628 CJ Delft (NL)

3 University of California at Berkeley, CA (US)

Abstract—The modeling of incomplete ionization is a key element for a reliable and scalable cryogenic transistor model. Despite the increasing interest in cryo-CMOS modeling, capacitance–voltage (CV) characteristics remain relatively unexplored, even though they are less sensitive to secondary effects, such as mobility variations, than DC measurements. While the experimental data in the literature are few and limited, a clear discrepancy is observed between model predictions and capacitance–voltage (CV) measurements. To address these limitations, this paper presents a new, accurate, and scalable capacitance model including an incomplete ionization model that predicts cryogenic behavior more accurately than existing models, along with a corresponding charge model derived from the proposed formulation. The model accurately reproduces all CV features, including the field-dependent ionization–induced flatband voltage dip, the depletion-region capacitance, the trap related threshold voltage humps, and the inversion region. Extensive CV characterizations over multiple device geometries, frequencies, AC excitation voltages, and temperatures are finally used to validate the model.

Fig: Inversion capacitance at 4.2 K for PMOS (a)–(d) and NMOS (e)–(h) devices with varying geometries. In (a), (b), (d), (e), (f), and (h), identical small-sized devices are connected in parallel to enable characterization with sufficient SNR.

[Open Hardware] CfP: FOSDEM 2027 Open Hardware and CAD/CAM Devroom

The Open Hardware and CAD/CAM "devroom" at FOSDEM 2027

is an opportunity for developers of Open Hardware projects and related software tools to gather and share their work, meet developers from other projects, network, and learn from one another.The 2027 devroom is once again being coordinated by Chris Hennes (@chennes, chennes@freecad.org) and Jo Hinchliffe (@concretedog, jo@concretedog.xyz). We carry on the tradition developed over the many years of this DevRoom's existence of a dynamic, interactive room full of interesting presentations and projects.

Call for Participation 

 We are pleased to announce the CfP for the Open Hardware and CAD/CAM devroom at FOSDEM 2027, 30 & 31 January 2027 in Brussels, Belgium. The devroom will take place on Sunday 09:00–13:00, 31 January 2027 at [ULB (Campus Solbosch)]. We hope you'll join us for a half day of talks, demos and interesting discussions on designing, modeling and testing hardware using Open Source tools. We welcome any talk proposals about the design and creation of physical objects. Topics of interest include, but are not limited to: 

- Open Hardware Projects 

* Open circuits 

* Product design 

* The business of open hardware 

- Circuit Design

* Printed circuit board design tools 

* Circuit simulation 

- 3D modeling and analysis

* Solid modeling tools

* Meshing, modeling and transforming physical representations

* Finite element analysis 

- 3D printing

* 3d slicing tools 

* Motor control 

- Machine design and integration

* Open Hardware projects

* ECAD/MCAD integration

* Thermal analysis

* Wire modeling 

- Physical Model Data storage

* Data representation and optimization

* Version control in hardware data storage

* Collaborative and team-based hardware design techniques 

Talk slots will be 20 minutes **total**, inclusive of time for questions. Presenters are encouraged to plan to speak for about 15 minutes, to ensure enough time for what is often a very lively Q&A segment. Note that this is shorter than previous years, since the 2027 edition is only a half day: talk fast! 

Important Dates 

* Submission deadline: 4 December 2026 

* Acceptance notifications: 11 December 2026 

* Final schedule announcement: 14 December 2026 

* Devroom: Sunday 31 January 2027 ## The submission process 

Please submit your proposal at the FOSDEM pretalx site before 4 Dec 2026. Select the "Open Hardware and CAD/CAM" session. Please note that the "Open Source Design" track, while a lovely group of wonderful hackers, is not the same. 

Please include the following information with your submission: 

- Abstract 

- Speaker bio 

- Link to any hardware / code /slides for the talk 

 

Fill in at least a title and abstract for the proposed talk. Keep in mind that much of the value in these meetings comes from the discussions, so please allot at least 20% of the talk time for questions and answers. 

Questions? 

If you have any questions or need guidance on any aspect of submitting, preparing or presenting, please e-mail channels at freecad.org. 

Volunteering 

If you are interested in helping the devroom run smoothly, please reach out to Chris Hennes (@chennes) or Jo Hinchliffe (@concretedog) and we'll be very happy to have your assistance! 

Recordings 

The talks will be recorded and live-streamed during FOSDEM'27. The recordings will be
published under the same licence as all FOSDEM content (CC-BY-4.0). Only presentations and
Q&A will be recorded, not informal discussions and whatever happens during breaks between
presentations. We require affirmative consent to this license. 

Please include the following statement in your submission notes: `

`` If my presentation is accepted for FOSDEM, I hereby agree to license all recordings, slides, and other associated materials under the Creative Commons Attribution Share-Alike 4.0 International License. Sincerely, <NAME> ``` 

Chris Hennes (@chennes)
The FreeCAD Project Association AISBL
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To unsubscribe send an email to open-hardware-devroom-leave@lists.fosdem.org
https://lists.fosdem.org/postorius/lists/open-hardware-devroom.lists.fosdem.org/

TSMC Europe OIP Ecosystem Workshop

Meet Dolphin Semiconductor at  TSMC Europe OIP Ecosystem Workshop Book a meeting! 📅 November 24, 2026 📍 Booth, Hilton Munich Airport, Germany   Come to our booth to learn how our TSMC-based, ultra-low-power, and smart IP solutions can shorten your design cycle and thus accelerate your Time-to-Market.   Book a meeting with us now to secure a dedicated slot before the show fills up. We look forward to seeing you at TSMC Open Innovation Platform Ecosystem Forum and sharing a glimpse into the future of our technology with you!

[chipfoundry] December Shuttle (CI2612)

Commitment and 50% payment due November 4. Tapeout December 7. Plus new drop-in analog IP for your design.‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­

Hello , A quick reminder that the December 2026 chipIgnite shuttle (CI2612) is coming up fast, and the commitment deadline is now about two weeks away.   Key dates November 4, 2026: Commitment deadline (50% payment due) December 7, 2026: Tapeout submission   If you already have a reservation, now is the time to lock in your spot. If you are still deciding, get in touch and we will help you scope your design for this run. Secure Your December Spot New: Commercial IPs now available on the marketplace The commercial analog and mixed-signal blocks we previewed in August are now live on the ChipFoundry marketplace for SkyWater 130nm. You can install them with ipm and drop them straight into your December design.   Highlights include: Data converters: 12-bit SAR ADC, delta-sigma modulator ADC, 8-bit voltage/current DAC Clocking: 100 MHz system PLL, 24 MHz RC oscillator, crystal oscillator interface Power and reference: 1.8 V LDO, bandgap reference, voltage monitor, POR sequencer Signal chain: Class AB amplifier, continuous-time comparator, high-Z input buffer, analog mux, switched-capacitor filter   Each block comes with abstract views for place-and-route, and ChipFoundry substitutes the full protected layout at tapeout, so you integrate it like any other macro. Browse the IP Catalog Questions about adding an IP to your December tapeout? Just reply to this email or contact us at info@chipfoundry.io. We are here to help.   Best regards, The ChipFoundry Team ChipFoundry You've received it because you've subscribed to our newsletter. Unsubscribe

[paper] ACM3 Compact MOSFET Model

Deni Germano Alves Neto; Márcio Cherem Schneider; Manuel J. Barragan; 

Sylvain Bourdel; Carlos Galup-Montoro,

ACM3 - An Advanced Compact MOSFET Model for Analog IC Design and Simulation

in IEEE Access, DOI: 10.1109/ACCESS.2026.3742180

1.) Federal University of Santa Catarina, 88040-900 Florianópolis (BR)

2.) Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA F-38000 Grenoble (F)

Abstract: This paper presents ACM3, an advanced compact MOSFET model that extends the designoriented ACM2 formulation by introducing gate-voltage dependencies for the slope factor n, the draininduced barrier lowering (DIBL) coefficient σ, and inversion charge dependence for the specific current IS. ACM3 preserves a single-piece, charge-based description of the drain current, valid from weak to strong inversion and from the linear to the saturation regions, while relying on an efficient analytical approximation of the Lambert W -function suitable for Verilog-A implementation. A robust yet straightforward parameterextraction flow is proposed, in which all eight DC parameters (VT 0, IS0, Φ, γ, θ, σWI , σSI and ζ) are obtained directly from ID–VGB and ID–VDS curves through a differential evolution (DE) algorithm that minimizes the root-mean-square percentage error between the reference and the modeled drain current. A distinctive feature of this flow is that the reference curves may originate either from silicon measurements or from another compact model, making the extraction equally applicable to measured and simulated data. At the device level, the parameters are extracted from silicon measurements of an open-source 130 nm BiCMOS technology, yielding agreement with the measured data for both short- and long-channel transistors across all regions of operation. At the circuit level, ACM3 is validated through simulations of a common-source amplifier, a self-biased current source, and a CMOS latch in a 180 nm CMOS technology, where the ACM3 parameters are extracted from BSIM4-generated characteristics and the results are compared against the foundry BSIM4 model. Representative process, voltage, and temperature (PVT) robustness is also evaluated against BSIM4. The ACM3 model has been implemented in Verilog-A and integrated into open-source circuit simulators, via OpenVAF, enabling accurate and intuitive analog IC design within fully open design flows.

TAB: Comparison of ACM3 with representative industrial 

and design-oriented compact MOSFET models

Aknowlegements: This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior, (BRAZIL), Conselho Nacional de Desenvolvimento Científico e Tecnológico, (BRAZIL), and TIMA laboratory, Grenoble (FRANCE).

eSim 2.6 Release

A Big Milestone for FOSSEE eSim - eSim 2.6 IS HERE!

The release of eSim 2.6 is bringing exciting improvements, enhanced workflows, and new capabilities to our open-source Electronic Design Automation (EDA) tool developed by the FOSSEE Project, IIT Bombay.

Download eSim 2.6: https://esim.fossee.in/downloads
Explore eSim 2.6 Release Notes: https://github.com/FOSSEE/eSim/releases/tag/v2.6

What's New in eSim 2.6?

• Refreshed User Interface
• Enhanced Simulation and Waveform Analysis
• Improved HDL Workflows and Icarus Verilog Support
• Compatibility with Newer KiCad Versions
• IHP OpenPDK Support
• Native Windows Installer
• Reduced Installer Size
• OpenROAD Integration (Work in Progress)

Celebrating the Team Behind the Release:

A special shout-out to Varadha RS, Akshat Sharma, and more than 100 hardworking interns for their dedication and contributions to eSim 2.6. From implementing new features and resolving issues to testing workflows and improving usability, their efforts have helped bring this release to life.

A heartfelt thank you to all eSim and FOSSEE team members for their invaluable contributions, technical expertise, guidance, and continued support. Every contribution matter, and milestones like this are the result of collaboration, persistence, and teamwork.

Acknowledging Our Supporters

Our sincere gratitude goes to the FOSSEE Project, Indian Institute of Technology Bombay, National Mission on Education Through ICT (NMEICT), and the Ministry of Education, Government of India, New Delhi, for their continued support in advancing open-source engineering tools and education.

Building the Future of Open-Source EDA

At FOSSEE, IIT Bombay, we are committed to making circuit design, simulation, PCB design, and semiconductor design more accessible through open-source technologies.

Thank you to everyone who has been part of this journey. Special thanks to our collaborators and the wider open-source community:

• Wladek Grabinski, 
• Steve Hoover, 
• Indira Iyer Almeida
• OpenPDK IHP - Leibniz Institute for High-Performance Microelectronics
• The OpenROAD Project

[paper] Self-Heating Effects in 55-nm SiGe HBTs

Abdelaaziz Boulgheb1, Billel Smaani2, Taha Housseyn Nouibat1

Physics-Based Electro-Thermal Modeling and Analysis 

of Self-Heating Effects in 55-nm SiGe HBTs

physica status solidi (a), 2026; 223:e70563 

https://doi.org/10.1002/pssa.70563

1. USTHB, Bab Ezzouar, Algeria 

2. University of Mila, Mila, Algeria

Abstract: This work investigates spatially resolved electrothermal behavior in scaled SiGe HBTs under self-heating conditions, emphasizing its impact on temperature distribution and RF performance. Unlike conventional lumped thermal resistance approaches assum- ing uniform temperature rise, the present analysis resolves the internal temperature field to capture nonuniform heat propagation effects. A physics-based electrothermal framework combining drift–diffusion transport, temperature-dependent semiconductor properties, and heat conduction equations is used to study hotspot formation and thermal confinement in a 55 nm SiGe HBT structure. Three operating conditions are considered: nominal operation at 300 K, self-heating at 300 K ambient temperature, and elevated ambient temperature of 320 K. The results reveal localized hotspot formation near the base–collector junction due to current crowding and geometrical confinement, leading to RF performance degradation. The cutoff frequency decreases from 320 to 285 GHz, while the maximum oscillation frequency reduces from 486 to 458.5 GHz. The current gain decreases from 2000 to 1500, and the maximum junction temperature reaches 417 K under the highest thermal stress condition. These findings highlight the importance of spatial thermal effects in governing RF limitations of SiGe HBTs and provide insight into the coupling between heat propagation and electrical performance in BiCMOS technologies.

FIG: Device structure of 55 nm SiGe HBT simulated with multiphysics TCAD: (a) log of electron and hole concentration highlighting emitter/base/SIC pedestal (b) TEM cross section of a fabricated BiCMOS 55nm HBT. Impact of self-heating on high-frequency performance of the 55-nm SiGe HBT under three thermal conditions: (c) parasitic delay parasitic (d) forward transit time τF , (e) cutoff frequency fT, and (f) maximum oscillation frequency fmax.

[paper] BSIM4 CryoModel-4K

Mohammed Saleh Alshaikh

CryoModel-4K: physics-based BSIM4 extension for28 nm bulk CMOS compact modeling at 4K

Nature Scientific Reports (Article in Press) DOI: 10.1038/s41598-026-69962-w

* Device Simulation Laboratory, Department of Electrical Engineering, College of Engineering and Architecture, Umm Al-Qura University, Makkah (SA)

Abstract: Accurate compact transistor models for 28nm bulk CMOS at cryogenic temperatures are essential for reli-able quantum computing interface circuit design. Existing room-temperature BSIM4 models fail to capture carrier mobility freeze-out, subthreshold swing saturation, current kink effects, and threshold voltage shifts at 4K. These failures produce post-fabrication performance deviations exceeding 300% in cryo-CMOS circuits designed using room-temperature models. This paper presents CryoModel-4K, a physics-based compact model that extends BSIM4 to accurately capture 28nm bulk CMOS behavior from 300 to 4K through three integrated correction modules. The Phonon Freeze-Out Mobility Enhancement Module (PFMEM) models the 3 to 8× car-rier mobility enhancement at liquid helium temperatures through a Matthiessen’s-rule combination of phonon, impurity, and surface roughness scattering. It is validated against published 4 K Hall effect measurements. The Cryogenic Subthreshold Swing Saturation Model (CSSM) replaces the classical kT/q thermal voltage with aband-tail tunneling-corrected expression. It accurately reproduces the observed 15 to 25 mV/dec subthreshold swing plateau below 30K. The Impurity Band Transport Kink Model (IBTK) captures the characteristic drain current kink arising from impact ionization triggered floating body effects in the partially frozen bulk substrate. Validation against published wafer-level characterization data for TSMC 28 nm bulk CMOS spanning 300 to 4K across 380 devices on three wafer splits demonstrates less than 5% RMS prediction error for all DC char-acteristics and less than 8% for RF S-parameters up to 10 GHz. Ring oscillator frequency is predicted within6.2% of measured values at 4K, compared to 312.5% error for standard BSIM4. The total SPICE simulation overhead relative to standard BSIM4 is approximately 25%.

FIG: a) Fig. 5 Complete small-signal equivalent circuit of CryoModel-4K for RF simulation, showing the intrinsic MOSFET withPFMEM-modified transconductance, CSSM-corrected output conductance, IBTK kink current source, temperature-depen-dent gate and substrate resistances, and parasitic interconnect elements. Small-signal equivalent circuit valid for operation from 100 MHz to 10 GHz at temperatures from 300 to 4 K. All substrate network elements are temperature-dependent 

b) Output characteristics (𝐼𝐷𝑉D) of a 28 nm NMOS device at 4 K for multiple 𝑉𝐺 values: measured data (symbols) ,CryoModel-4K with IBTK (solid lines), and BSIM4 without kink correction (dashed lines). Device: NMOS Lg = 28 nm, W =  um at T = 4K. VGS stepped from Vth to Vth + 0.5V in 0.1V increments. VDS swept from 0 V to 1.0 V in 25 mV steps. The IBTK captures the characteristic current kink at 𝑉𝐷≈0.5–0.7V

Acknowledgements: The author extends his sincere gratitude to the Umm Al-Qura University, for the invaluable resources and sup-portive environment that made this research possible.

Open Access: This article is licensed under a Creative Commons Attribution 4.0 International License

APCI Program: SBMicro Projects

APCI Program

Support for SBMicro Integrated Circuit Projects

TAB: Universities Involved in IC Design and EDA/CAD Tool Development

University	#Profs	#PhDs	#MSCs
CEFET-MG - Centro Federal de Educação Tecnológica de Minas Gerais	8	0	3
CEFET-RJ - Federal Center for Technological Education Celso Suckow da Fonseca	2	1	0
FEI - Centro Universitário da FEI	2	0	3
FURG - Universidade Federal do Rio Grande	3	1	1
IFSP - Instituto Federal de São Paulo	5	0	0
ITA - Instituto Tecnológico de Aeronáutica	10	0	5
PUCRS - Pontifícia Universidade Católica do Rio Grande Do Sul	8	15	9
UCPEL - Universidade Católica de Pelotas	3	0	6
UEA - Universidade do Estado do Amazonas	1	0	0
UERGS - State University of Rio Grande do Sul	5	0	0
UFABC - Federal University of ABC	6	0	2
UFAM - Universidade Federal de Manaus	4	4	0
UFBA - Universidade Federal da Bahia	5	13	8
UFC - Universidade Federal do Ceará	3	5	3
UFERSA - Mossoró	1	0	4
UFERSA - Pau dos Ferros	5	1	3
UFG - Federal University of Goiás	8	1	0
UFMG - Universidade Federal de Minas Gerais	6	3	9
UFPB - Universidade Federal da Paraíba	1	1	2
UFPEL - Universidade Federal de Pelotas	13	13	2
UFPR - Universidade Federal do Paraná	7	2	5
UFRGS - Universidade Federal do Rio Grande do Sul	17	32	45
UFRJ - Federal University of Rio de Janeiro	6	2	4
UFRN - Federal University of Rio Grande do Norte	4	3	2
UFS - Universidade Federal do Sergipe	3	0	1
UFSC - Universidade Federal de Santa Catarina	11	12	11
UFSM - Universidade Federal de Santa Maria	8	0	5
UFV - Universidade Federal de Viçosa	2	3	3
UNB - Universidade de Brasília	9	3	9
UNESP - Universidade Estadual Paulista	4	0	1
UNICAMP - Universidade Estadual de Campinas	8	16	21
UNIFEI - Universidade Federal de Itajubá	7	2	3
UNIFEI - Itabira	3	0	3
UNIPAMPA - Universidade Federal do Pampa	4	0	2
UNISANTOS - Universidade Católica de Santos	1	0	0
UNISINOS - Universidade do Vale do Rio dos Sinos	3	0	3
UNIVALI - Universidade do Vale do Itajaí	3	0	3
USP - Universidade de São Paulo	8	1	12
USP-EESC - Escola de Engenharia de São Carlos	3	1	2
UTFPR - Universidade Tecnológica Federal do Paraná	1	0	0

[REF] Report: Strengthening EU-Brazil bilateral know-how of semiconductor sector technologyand possibilities for cooperation on trade and R&D (July 2023)

[OpenSUSI] First Tyepout

J. I. Okamura

New Semiconductor Design Programs with Japan’s Open Source Ecosystem

[Society News] in IEEE Solid-State Circuits Magazine, vol. 18, no. 3, pp. 87-88, Summer 2026, 

doi: 10.1109/MSSC.2026.3708432

Abstract: Open Source Utilized Silicon Initiatives (OpenSUSI), founded in April 2024 as a nonprofit organization, has been working closely with two Japanese legacy foundries to foster an open source silicon ecosystem in Japan. On 19 September 2025, TOKAI RIKA Co., Ltd., a 6-inch legacy foundry in Japan, announced the release of a non-disclosure-free process design kit (PDK) as an open source platform [1]. This new open source PDK, called TR-1um [2], was released via the OpenSUSI GitHub repository, and, since last October, we have been cleaning up and maintaining it alongside our collaborators.

Fig. First Tapeout application form on the OpenSUSI homepage.

[OpenPDK] GT2N

This the initial release for the GT2N PDK with 72 standard cells: <https://github.com/azadnaeemi/GT2N>.

It is based on 2nm GAAFET with BSPDN. All the device models are based on 3-stack nanosheets

Standard cell layouts can also be imported using the .gds file: GT2N/gds/gt2_6t_std_cells.gdsLVS and DRC rulesets for icvalidator are present in "GT2N/icv_runset".
Libraries are composed of 3 process corners (under development), 2 nanosheet width (W) flavors, and 5 threshold voltage (VT) flavors. (In the order of decreasing VT, HVT > SVT > LVT > ULVT > ELVT)

The collaterals required for synthesis and PnR are (depending on the process corner and W/VT flavor):

LIB: GT2N/lib/tt/gt2_6t_w31_lvt_tt_0p7v25c.lib
LEF: GT2N/lef/tt/gt2_6t_w31_lvt.lef
Techlef: GT2N/techlib/gt2_tech.lef
ICT: GT2N/qrc/GT2.ict
QRCTech: GT2N/qrc/GT2_qrc.tch
ITF: GT2N/nxtgrd/GT2.itf
NXTGRD: GT2N/nxtgrd/GT2.nxtgrd

The thermal-calibrated GAAFET (3-stack nanosheet) model card is (depending on the process corner and W/VT flavor):

GT2N/device/tt/gt2_w31_lvt_tt.sp

[ref] D. Jang, P. Kumar, M. N. H. Shazon, S. J. Ram, A. Svizhenko, V. Moroz, A. Ceyhan, N. A. Radhakrishn, and A. Naeemi, "GT2N: An Open-Source 2nm Nanosheet PDK Enabling Multi-Width/VT Benchmarking" in IEEE International Symposium on Circuits and Systems (ISCAS) 2026  

[ICTA2026 ] Special OpenPDK Session

IEEE International Conference on Integrated Circuits, Technologies & Applications

ICTA 2026 Special Session “OpenPDK - Global FOSS Scholar Platform"

21st - 24th (Wed - Sat) October 2026

Grand Copthorne Waterfront Hotel, Singapore

The OpenPDK initiative delivers a global FOSS Scholar Platform supporting analog/RF, mixed‑signal, and digital IC design. Central to this effort are accurate SPICE models for low‑power sensing MOSFETs, RF HBTs, and emerging RRAM devices, validated across cryogenic temperatures for space and quantum‑computing applications. The initiative also advances Verilog‑A compact‑model standardization, ensuring result reproducibility and seamless integration into open‑source design flows. Supported by the EU Chips JU, OpenPDK fosters collaboration among academia, startups, and industry, while providing FOSS IC‑design tools covering schematic capture, simulation, layout, and verification up to tape‑out. Similar to the EU Chips JU program, Zhejiang CoreXin in China offers an open‑source PDK together with tape‑out services for its 55nm CMOS process. To accelerate the semiconductor‑industry development across the Asia‑Pacific and Southeast‑Asia regions, semiconductor model development and parameter extraction techniques should be pursued in a more focused manner. This special session brings together experts to present and discuss advances in device characterization, compact modeling, simulation methodologies, and validation techniques for a broad range of solid‑state devices, including Si, III/V semiconductors, power devices, nanoscale structures, and emerging 2.5D/3D advanced packaging technologies [ read more...]

ICTA 2026 Special OpenPDK Session Presenters

• SPICE/Verilog-A standard models and OpenPDK practice
  Wladek Grabinski, GMC Consulting, Switzerland
• Open-Source Ecosystem Updates and Semiconductor Design Development Programs in Japan
  Jun-ichi Okamura, AIST Solutions, OpenSUSI, Japan
• Open-Source EDA Meets Industrial IC Design
  Ehrenfried Seebacher, ams-OSRAM AG, Austria
• Building an Open-Source Process Platform, Empowering VLSI Innovation and Development
  Da Zhang, Zhejiang University/CTO, Zhejiang Chuangxin Integrated Process Platform, China
• From Silicon to Design: Intelligent Measurement and Modeling for DTCO
  Yutao Ma, VP of R&D, Primarius Technologies. Ltd. China
• Beyond Moore, Application-Driven IC Innovation International Cooperation Opportunities at NICE
  Alex Gu, National Innovation Center Par Excellence (NICE), China
• 2.5D/3D IC: AI+EDA Reshaping the System-Design-Technology Co0ptimization (STCO) Paradigm for Advanced Packaging
  Alex Zhao, Founder/CEO Zhuhai SiChip Technology Co., Ltd., China
• Modelling of semiconductor devices: the heart of innovation bridging academia and industrial applications
  Fujiang Lin, University of Science and Technology of China (USTC), China

Special OpenPDK Session progeam include the panel discussion: 

How to have a close loop for PDK, EDA, PDA and ICS simulation?

[ read more...]

[conference] ELECTRONICS 2026 at KTU Kaunas

International Conference ELECTRONICS 2026

From SMT to Advanced Packaging – Manufacturing Meets Microinterconnects

KTU Kaunas, Lithuania

12–13 November 2026

Conference Vision : A joint platform connecting SMT engineers, advanced packaging researchers, reliability specialists, and industry to build a shared technical language, bridge research and manufacturing, and grow German-Baltic collaboration around heterogeneous integration and microinterconnects. Organized by Kaunas University of Technology, the conference serves as a platform for collaboration and discussion among representatives from academy, industry, and business.

Partners:
TUD IAFT (Dresden University of Technology, Institute of Electronic Packaging Technology)
IHP (IHP GmbH, Leibniz Institute for High Performance Microelectronics)
Industry Partners: FINETECH, TELTONIKA, etc.

Conference Program Online <https://eef.ktu.edu/events/electronics2026/>

Conference Organzation Committee:

General Chair

Prof., Dr. Mindaugas ŽILYS, KTU Kaunas

Executive Chair

Dr. Agata ROMANOVA, KTU Kaunas

Co-Chairs

Prof., Dr. Algimantas VALINEVIČIUS, KTU Kaunas

Prof., Dr. Darius ANDRIUKAITIS, KTU Kaunas

Prof., Dr. Dangirutis NAVIKAS, KTU Kaunas

Schematic to Silicon with Mini MOSbius

Zero To ASIC Course and Tiny Tapeout by Matt Venn

Schematic to Silicon with Mini MOSbius 

https://www.youtube.com/watch?v=NM5cLWYWqG0

Take Matt Venn TT course: 

https://www.zerotoasiccourse.com/

Buy a copy of Mini MOSbius, part of the TT IP library, here: 

https://store.tinytapeout.com/products/TTSKY25b-Development-Kit-p849160072

Check the configurator: 

https://github.com/mattvenn/mini-mosbius-configurator

Mini MOSbius is available on these chips

• [OK] TTSKY25a - delivered July 2026 - available in the store
• [OK] TTSKY25b - delivered August 2026 - available in the store
• TTSKY26b - tapeout May 2026
• TTSKY26c - tapeout September 2026
• GF180 - will be taped out December 2026

and finally check out the original MOSBius: https://mosbius.org/ If you are interested to acquire MOSbius kits, review the express license and email Peter Kinget for kit availability before placing an order.

[poster] Active Cantilever with Dual Actuator

Bartosz Pruchnik1, Fabian Dietrich2, Richard Subianto2, Katerina Ivanova2, Athulya K. Muraleedharan Bindu2, Hans-Georg Pietscher2, Javad Basseri2, Muralikrishnan Brajesh Kaimal2, Władysław Kopczyński1, Wojciech Godlewski1, Dominik Badura1, Piotr Putek1, Krzysztof Kwoka1, Piotr Smagowski1, Andrew Yacoot3, Tomasz Piasecki1, Fangzhou Xia4, Ivo W. Rangelow2 

Active Cantilever with Dual Actuator

52nd International Micro and Nano Engineering Conference

Sep. 21-24, 2026 Interlaken (CH)

MEN2026 Poster S05A-T2-P-5

1. Wrocław University of Science and Technology,

2. nano analytik GmbH, 

3. National Physical Laboratory

4. University of Texas at Austin

Abstract: Atomic Force Microscopy (AFM) is often limited by the speed and bandwidth of three main components: the cantilever, the scanner, and the controller. Recent microelectromechanical systems (MEMS) have improved the performance of the cantilever and scanner by combining high-speed active cantilevers with low-latency scanners. In this work, we present a standardized active cantilever design. The system combines a large cantilever that acts as a Z-axis actuator with a smaller active cantilever sensor that provides a bandwidth greater than 400kHz. The smaller cantilever is integrated into the larger structure, creating a compact and highly responsive device. We introduce a new active cantilever architecture that uses two integrated electrothermal actuators. One actuator is used for cantilever operation, while the second provides vertical (Z-axis) movement for surface tracking. This design allows AFM measurements to be performed without the need for an external piezoelectric z-actuator.

Acknowledgements: This work was supported by the European Union's Horizon Europe research and innovation program under the Marie Sklodowska-Curie grant agreement No 101072775, and by the National Science Centre, Poland (grant No. 2021/41/B/ST7/03144).