Showing posts with label Mobility freeze-out. Show all posts
Showing posts with label Mobility freeze-out. Show all posts

Oct 12, 2026

[paper] BSIM4 CryoModel-4K

Mohammed Saleh Alshaikh
CryoModel-4K: physics-based BSIM4 extension for28 nm bulk CMOS compact modeling at 4K
Nature Scientific Reports (Article in Press) DOI: 10.1038/s41598-026-69962-w

* Device Simulation Laboratory, Department of Electrical Engineering, College of Engineering and Architecture, Umm Al-Qura University, Makkah (SA)

Abstract: Accurate compact transistor models for 28nm bulk CMOS at cryogenic temperatures are essential for reli-able quantum computing interface circuit design. Existing room-temperature BSIM4 models fail to capture carrier mobility freeze-out, subthreshold swing saturation, current kink effects, and threshold voltage shifts at 4K. These failures produce post-fabrication performance deviations exceeding 300% in cryo-CMOS circuits designed using room-temperature models. This paper presents CryoModel-4K, a physics-based compact model that extends BSIM4 to accurately capture 28nm bulk CMOS behavior from 300 to 4K through three integrated correction modules. The Phonon Freeze-Out Mobility Enhancement Module (PFMEM) models the 3 to 8× car-rier mobility enhancement at liquid helium temperatures through a Matthiessen’s-rule combination of phonon, impurity, and surface roughness scattering. It is validated against published 4 K Hall effect measurements. The Cryogenic Subthreshold Swing Saturation Model (CSSM) replaces the classical kT/q thermal voltage with aband-tail tunneling-corrected expression. It accurately reproduces the observed 15 to 25 mV/dec subthreshold swing plateau below 30K. The Impurity Band Transport Kink Model (IBTK) captures the characteristic drain current kink arising from impact ionization triggered floating body effects in the partially frozen bulk substrate. Validation against published wafer-level characterization data for TSMC 28 nm bulk CMOS spanning 300 to 4K across 380 devices on three wafer splits demonstrates less than 5% RMS prediction error for all DC char-acteristics and less than 8% for RF S-parameters up to 10 GHz. Ring oscillator frequency is predicted within6.2% of measured values at 4K, compared to 312.5% error for standard BSIM4. The total SPICE simulation overhead relative to standard BSIM4 is approximately 25%.

FIG: a) Fig. 5 Complete small-signal equivalent circuit of CryoModel-4K for RF simulation, showing the intrinsic MOSFET withPFMEM-modified transconductance, CSSM-corrected output conductance, IBTK kink current source, temperature-depen-dent gate and substrate resistances, and parasitic interconnect elements. Small-signal equivalent circuit valid for operation from 100 MHz to 10 GHz at temperatures from 300 to 4 K. All substrate network elements are temperature-dependent 
b) Output characteristics (𝐼𝐷𝑉D) of a 28 nm NMOS device at 4 K for multiple 𝑉𝐺 values: measured data (symbols) ,CryoModel-4K with IBTK (solid lines), and BSIM4 without kink correction (dashed lines). Device: NMOS Lg = 28 nm, W =  um at T = 4K. VGS stepped from Vth to Vth + 0.5V in 0.1V increments. VDS swept from 0 V to 1.0 V in 25 mV steps. The IBTK captures the characteristic current kink at 𝑉𝐷≈0.5–0.7V

Acknowledgements: The author extends his sincere gratitude to the Umm Al-Qura University, for the invaluable resources and sup-portive environment that made this research possible.

Open Access: This article is licensed under a Creative Commons Attribution 4.0 International License