[paper] Cryo 1T1R HfO2-Based RRAM

Emilio Pérez-Bosch Quesada, Alberto Mistroni, Ruolan Jia, Keerthi Dorai Swamy Reddy, Markus Fritscher, Felix Reichmann, Oliver Skibitzki, Juan Bautista Roldán, Helena Castán, Salvador Dueñas, Christian Wenger, Eduardo Pérez

Enabling Quantum-Compatible Nonvolatile Memory: Cryogenic Evaluation 

of 1T1R HfO2-Based RRAM From 300 to 1.5K

Advanced Electronic Materials 12, no. 19 (2026): e00798

DOI: 10.1002/aelm.202500798

ABSTRACT: To enable compact quantum computing systems, cryogenically compatible CMOS-based non-volatile memories are required. In this work, we investigate 1-transistor–1-resistor (1T1R) resistive random-access memory (RRAM) devices over an extended temperature range, including previously unexplored cryogenic regimes. To enhance storage density, we explore a multilevel-cell approach via multilevel programming. As temperature decreases, the low-resistance state (LRS) effective conductance increases, improving state separation but also leading to higher LRS currents and increased reset voltages required for reliable switching to the high-resistance state (HRS), resulting in incomplete filament rupture and a broader HRS distribution. Through independent characterization of the access nMOS transistor, we identify transistor temperature dependence as the dominant factor governing LRS evolution, while extraction of the intrinsic metal–insulator–metal (MIM) behavior reveals an opposite trend, with decreasing conductivity at lower temperatures. Based on these insights, we implement an optimized programming strategy for cryogenic operation by tuning the nMOS gate bias during set, reducing LRS currents, particularly in intermediate and high conductance states, while preserving state separation, narrowing the HRS distribution, and lowering reset voltages. Overall, this work establishes a robust and scalable approach for reliable 1T1R operation at cryogenic temperatures and provides a key step toward nonvolatile memory integration in quantum computing architectures.

FIG: a) Cryogenic setup used to characterize the RRAM devices under study, b) RRAM array containing a total of 32 1T1R devices individually addressable, and c) schematic description of the forming, set, and reset operations carried out during this work.

Acknowledgments: This work was financially supported by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Project 551916740.

[Habilitation] Assessment of novel devices in CMOS technology

Assessment of novel devices in CMOS technology

by electrical characterization and physics-based model

Habilitation Presented To Obtain The Authorization 

To Direct Research From Sorbonne University

Lionel Trojman, PhD

Sorbonne Université, 2020

Organization of the thesis

Chapter 1: This chapter extends research work after the author’s PhD study. It focuses on HfO2-based dielectric MOSFETs with sub-1nm EOT. The study explores the impact of transport factors like saturation velocity on planar MOSFETs and the mobility of FDSOI-UTBB MOSFETs. Notably, the back-biased effect is considered, and an inversion charge model is developed for different front and back biases.

Chapter 2: Emphasis the application of the statistical defect-centric model to assess the impact of channel hot carriers on the reliability of low-dimensional MOSFETs.

Chapter 3: This chapter shifts focus to GaN-on-Si wafer devices for power electronic applications. These devices integrate MOS-like structures into III-V material-based devices, specifically MOS-HEMT and GET-SBD.

Chapter 4: Investigates RERAM devices. It stems from cooperative research with UNICAL and a PhD program in collaboration with Aix-Marseille University

FIG: Description of the gate structure (half device) of the studied device including the parasitic capacitance inner fringing (CIF), outer fringe (COF) and Junction overlap capacitance (COV)