[paper] ULTRARAM Memory on Silicon

Peter D. Hodgson, Dominic Lane, Peter J. Carrington, Evangelia Delli, 

Richard Beanland and Manus Hayne

ULTRARAM: A Low-Energy, High-Endurance, Compound-Semiconductor Memory 

on Silicon

First published: 05 January 2022

Adv. Electron. Mater. 2022, 8, 2101103

DOI: 10.1002/aelm.202101103

Abstract: ULTRARAM is a nonvolatile memory with the potential to achieve fast, ultralow-energy electron storage in a floating gate accessed through a triple-barrier resonant tunneling heterostructure. Here its implementation is reported on a Si substrate; a vital step toward cost-effective mass production. Sample growth using molecular beam epitaxy commences with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III–V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10ms duration program/erase pulses of ≈2.5V, a remarkably fast switching speed for 10 and 20µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices reveals retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.

FIG: a) Schematic cross-section of ULTRARAM device concept with corresponding material layers. The floating gate (1: FG), triple-barrier resonant-tunneling structure (2: TBRT), and readout channel (3) are highlighted. Arrows indicate the direction of electron flow during program/erase operations; b) Scanning electron micrograph of a fabricated device of 10 µm gate length. 

Acknowledgements: P.D.H. and D.L. contributed equally to this work. This work was supported by the Engineering and Physical Sciences Research Council, UK, via the 2017–2020 Impact Acceleration Account funding allocation to Lancaster University under grant EP/R511560/1, a scholarship under grant EP/N509504/1, equipment funding under grant EP/T023260/1, and the Future Compound Semiconductor Manufacturing Hub grant EP/P006973/1, by the ATTRACT project funded by the EC under Grant Agreement 777222 and by the Joy Welch Educational Charitable Trust.

[paper] Compound-Semiconductor Memory on Silicon

Peter D. Hodgson, Dominic Lane, Peter J. Carrington, Evangelia Delli,
Richard Beanland, and Manus Hayne

ULTRARAM: A Low-Energy, High-Endurance, 

Compound-Semiconductor Memory on Silicon 

Adv. Electron. Mater. 2022, 2101103

DOI: 10.1002/aelm.202101103

  
Department of Physics, University of Warwick (UK)

Abstract: ULTRARAM is a nonvolatile memory with the potential to achieve fast, ultralow-energy electron storage in a floating gate accessed through a triple-barrier resonant tunneling heterostructure. Here its implementation is reported on a Si substrate; a vital step toward cost-effective mass production. Sample growth using molecular beam epitaxy commences with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III–V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10 ms duration program/erase pulses of ≈2.5 V, a remarkably fast switching speed for 10 and 20 µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices reveals retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.

Fig: ULTRARAM device concept. a) Schematic cross-section of a device with corresponding material layers. The floating gate (FG), triple-barrier resonant-tunneling structure (TBRT), and readout channel are highlighted. Arrows indicate the direction of electron flow during program/ erase operations. b) Scanning electron micrograph of a fabricated device of 10 µm gate length. 

Acknowledgements: P.D.H. and D.L. contributed equally to this work. This work was supported by the Engineering and Physical Sciences Research Council, UK, via the 2017–2020 Impact Acceleration Account funding allocation to Lancaster University under grant EP/R511560/1, a scholarship under grant EP/N509504/1, equipment funding under grant EP/T023260/1, and the Future Compound Semiconductor Manufacturing Hub grant EP/P006973/1, by the ATTRACT project funded by the EC under Grant Agreement 777222 and by the Joy Welch Educational Charitable Trust.

[paper] A Review of Sharp-Switching Band-Modulation Devices

Sorin Cristoloveanu¹, Joris Lacord², Sébastien Martinie², Carlos Navarro³, Francisco Gamiz³, Jing Wan⁴, Hassan El Dirani¹, Kyunghwa Lee¹ and Alexander Zaslavsky⁵

A Review of Sharp-Switching Band-Modulation Devices

Micromachines 2021, 12, 1540.

DOI: 10.3390/mi12121540

   
1 IMEP-LAHC, Université Grenoble Alpes (F)
2 CEA, LETI, MINATEC Campus (F)
3 CITIC-UGR, University of Granada (SP)
4 Fudan University, Shanghai (CN)
5 Brown University, Providence (US)

Abstract: This paper reviews the recently-developed class of band-modulation devices, born from the recent progress in fully-depleted silicon-on-insulator (FD-SOI) and other ultrathin-body technologies, which have enabled the concept of gate-controlled electrostatic doping. In a lateral PIN diode, two additional gates can construct a reconfigurable PNPN structure with unrivalled sharp-switching capability. We describe the implementation, operation, and various applications of these band-modulation devices. Physical and compact models are presented to explain the output and transfer characteristics in both steady-state and transient modes. Not only can band-modulation devices be used for quasi-vertical current switching, but they also show promise for compact capacitorless memories, electrostatic discharge (ESD) protection, sensing, and reconfigurable circuits, while retaining full compatibility with modern silicon processing and standard room-temperature low-voltage operation.

Fig: Average subthreshold swing SS vs. normalized ION plot. 

Green points indicate CMOS-compatible materials.

Acknowledgements: The European authors are grateful for support from the EU project REMINDER (H2020-687931). Alexander Zaslavsky acknowledges the support of the U.S. National Science Foundation (award QII-TACS-1936221).

[paper] CMOS floating-gate device for quantum control hardware

Michele Castriotta¹, Enrico Prati², Giorgio Ferrari¹

Cryogenic characterization and modeling of a CMOS floating-gate device 

for quantum control hardware

preprint arXiv:2110.02315, 2021

1 Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano (I)
2 Istituto di Fotonica e Nanotecnologie, Consiglio Nazionale delle Ricerche (I)

Abstract - We perform the characterization and modeling of a floating gate device realized with a commercial 350-nm CMOS technology at cryogenic temperature. The programmability of the device offers a solution in the realization of a precise and flexible cryogenic system for qubits control in large-scale quantum computers. The device stores onto a floating-gate node a non-volatile charge, which can be bidirectionally modified by Fowler-Nordheim tunneling and impact-ionized hot electron injection. These two injection mechanisms are characterized and modeled in compact equations both at 300 K and 15 K. At cryogenic temperature, we show a fine-tuning of the stored charge compatible with the operation of a precise analog memory. Moreover, we developed accurate simulation models of the proposed floating-gate device that set the stage for designing a programmable analog circuit with better performances and accuracy at a few Kelvin. This work offers a solution in the design of configurable analog electronics to be employed for accurately read out the qubit state at deep-cryogenic temperature.

Fig: Simplified layout of the p-type floating-gate device under test. The capacitive coupling to the floating-gate node  is realized with the poly 2 control gate.

Acknowledgments: This work was supported by QUASIX Grant from  Italian Space Agency. This work was partially performed at Polifab, the  micro- and nanofabrication facility of Politecnico di Milano

4th International DevIC 2021 Conference

DevIC 2021

Conference Date: 19-20 May, 2021

(New date after Postponement due to COVID-19 and W.B. State General Election)

Click here to download the program Schedule of DevIC 2021

We are pleased to announce the upcoming 4th International Conference “2021 Devices for Integrated Circuit (DevIC)”, to be held at Kalyani Government Engineering College from March 24-25 May 19-20, 2021, organized by IEEE KGEC Student Branch Chapter in association with Department of ECE, KGEC and technically co-sponsored by IEEE EDS Kolkata Chapter. There will be keynote lectures, talks, tutorials, and oral presentations  by eminent researchers. We solicit original research and technical papers not published elsewhere.

DevIC 2021 Conference committee appeals ALL to contribute in West Bengal State Emergency Relief Fund and assist the State in prevention and control of situation arising out of unforeseen emergencies like COVID-19 (CORONA)

• IEEE EDS Kalyani Government Engineering College Student Branch Chapter has decided to contribute to the West Bengal State Emergency Relief Fund to combat the coronavirus outbreak.

• IEEE EDS Kalyani Government Engineering College Student Branch Chapter  thanks Dr. Wladek Grabinski (Senior IEEE EDS Member, MOS-AK (EU)) for coming forward to contribute to fight the Corona Virus outbreak.

Due to rapid increase in COVID affected people, request to Kindly join our hands and support us by donating to West Bengal State Emergency relief Fund

• We must act immediately to take on the second, more severe wave of COVID-19.
• Your support is vital and critical!
• NO amount is small!!!
• Your contribution will truly create an impact!!!
• Kindly motivate others to donate!!!
• Donate in West Bengal State Emergency Relief Fund to collectively fight against unprecedented COVID-19 pandemic.

DevIC 2021 is appealing all the participants to help fight the pandemic and saving lives.

Click here to donate in West Bengal State Emergency Relief Fund

Due to COVID-19, the conference will be organized in the online mode. 

DevIC 2021 Conference Committee

DevIC 2021 Registration

DevIC 2021 Plenary Talk

Kalyani Government Engineering College (KGEC) Website

[paper] 2D-SFET Based SRAMs

Niharika Thakuria, Graduate Student Member, IEEE, Daniel Schulman, Member, IEEE, Saptarshi Das, Member, IEEE, and Sumeet Kumar Gupta, Member, IEEE

2D Strain FET (2D-SFET) Based SRAMs - Part I: Device-Circuit Interactions

 IEEE TED, vol. 67, no. 11, pp. 4866-4874, Nov. 2020

DOI: 10.1109/TED.2020.3022344.

Abstrat: In this article, we analyze the characteristics of a recently conceived steep switching device 2-D Strain FET (2D-SFET) and present its circuit implications in the context of 6T-SRAM. We discuss the dependence of 2D-SFET characteristics on key design parameters, showing up to 2.7× larger ON-current and 35% decrease in subthreshold swing when compared to 2D-FET. We analyze the performance of 2D-SFET (as drop-in replacement for standard 2D-FET) in 6T-SRAM for a range of design parameters and compare those to 2D-FET 6T-SRAM. 2D-SFET 6T-SRAM achieves up to 5.7% lower access time, 63% higher write margin, and comparable hold margin, but at the cost of comparable to 11% lower read stability and 16% increase in write time. In Part II of this article, we mitigate the read stability issues of 2D-SFET SRAMs by proposing VB-enabled SRAM designs.

Fig: 2D-SFET model with bandgap reduction and 2-D-electrostatics [18]. COX, CGS/D,F, CIT, and CGB are oxide, gate (G) to source (S)/drain (D) fringe, trap, and PE capacitance, respectively. VFB, and VFBS are flat-band voltage of G and back contact. VQFL(VS,VD) is S/D quasiFermi level. ΔEG(VG'B) is VGB dependent bandgap change, τEG is strain transduction delay, and REG is resistance used to model τEG. ΔEG(τEG) is final bandgap reduction considering τEG, used for calculating channel charge, QCH(ΔEG(τEG)).

Aknowlegement: This work was supported in part by NSF under Grant 1640020, in part by Nanoelectronics Research Corporation (NERC), and in part by Semiconductor Research Corporation (SRC) under Grant 2699.003

[paper] Low-voltage, Non-volatile, Compound-semiconductor Memory Cell

Room-temperature Operation of Low-voltage, Non-volatile, Compound-semiconductor Memory Cell

Ofogh Tizno, Andrew R. J. Marshall, Natalia Fernández-Delgado, Miriam Herrera, Sergio I. Molina
and Manus Hayne

Scientific Reports volume 9, Article number: 8950 (2019) 

DOI: 10.1038/s41598-019-45370-1

Abstract: Whilst the different forms of conventional (charge-based) memories are well suited to their individual roles in computers and other electronic devices, flaws in their properties mean that intensive research into alternative, or emerging, memories continues. In particular, the goal of simultaneously achieving the contradictory requirements of non-volatility and fast, low-voltage (low-energy) switching has proved challenging. Here, we report an oxide-free, floating-gate memory cell based on III-V semiconductor heterostructures with a junctionless channel and non-destructive read of the stored data. Non-volatile data retention of at least 10000s in combination with switching at ≤2.6 V is achieved by use of the extraordinary 2.1 eV conduction band offsets of InAs/AlSb and a triple-barrier resonant tunnelling structure. The combination of low-voltage operation and small capacitance implies intrinsic switching energy per unit area that is 100 and 1000 times smaller than dynamic random access memory and Flash respectively. The device may thus be considered as a new emerging memory with considerable potential.

FIG: Device structure a) Schematic of the processed device with control gate (CG), source (S) and drain (D) contacts (gold). The red spheres represent stored charge in the floating gate (FG). b) Cross-sectional scanning transmission electron microscopy image showing the high quality of the epitaxial material, the individual layers and their heterointerfaces.

Simulation Methods: The nextnano software package was utilised for mathematically modelling the energy band diagram of the memory device structure reported here, taking into account strain and piezoelectricity. Within this work, a self-consistent Schrödinger solver was used along with the Poisson and drift–diffusion equations to calculate the electron densities at equilibrium and under bias.

[paper] SPICE Model for Bipolar Resistive Switching Devices

Miranda, Enrique, and Jordi Suñé

Departament d’Enginyeria Electrònica,

UAB, 08193 Barcelona, Spain

Fundamentals and SPICE Implementation of the Dynamic Memdiode Model

for Bipolar Resistive Switching Devices

(2020 - techrxiv.org)

Abstract: This paper reports the fundamentals and SPICE  implementation of the dynamic memdiode model (DMM) for the  conduction characteristics of bipolar resistive switching (RS)  devices. Following Chua’s memristive devices theory, the  memdiode model comprises two equations, one for the electron  transport based on a heuristic extension of the quantum pointcontact model for filamentary conduction in dielectrics and a  second equation for the internal memory effect related to the  reversible displacement of atomic species within the oxide film.  The DMM represents a breakthrough with respect to the previous  quasi-static memdiode model (QMM) since it describes the  memory state of the device as a rate balance equation  incorporating both the snapback and snapforward effects,  features of utmost importance for the accurate and realistic  simulation of the RS phenomenon. The DMM allows simple setting  of the memory state initial condition as well as separate modeling  of the set and reset transitions. The model equations are  implemented in the LTSpice simulator using an equivalent  circuital approach with behavioral components and sources. The  practical details of the model implementation and its use are  thoroughly discussed.   

Fig: Hysteretic behavior of the filamentary-type I-V characteristic.

Filament stages: A) formation, high resistance state (HRS), B) completion, C) expansion,

D,F) complete expansion, low resistance state (LRS), G) dissolution, I) rupture.

Supplementary information: The memdiode model script for LTSpice XVII reported in this Appendix includes not only the DMM but also the QMM. It is important to activate one of the options at a time (DMM or QMM) by inserting asterisks (*) in the corresponding lines. The parameter list, I-V, and Auxiliary functions sections are common to both approaches. This does not mean that the obtained curves will be identical. The meaning of the parameters is discussed in the text and in previous papers.

LTSPICE script

.subckt memdiode + - H

*created by E.Miranda & J.Suñé, June 2020

.params

+ H0=0 ri=50

+ etas=50 vs=1.4

+ etar=100 vr=-0.4

+ imax=1E-2 amax=2 rsmax=10

+ imin=1E-7 amin=2 rsmin=10

+ vt=0.4 isb=200E-6 gam=1 gam0=0 ;isb=1/gam=0 no SB/SF

+ CH0=1E-3 RPP=1E10 I00=1E-10

*Dynamic model

BV A 0 V=if(V(+,-)>=0,1,0)

RH H A R=if(V(+,-)>=0,TS(V(C,-)),TR(V(C,-)))

CH H 0 1 ic={H0}

*Quasi-static model

*BH 0 H I=min(R(V(C,-)),max(S(V(C,-)),V(H))) Rpar=1

*CH H 0 {CH0} ic={H0}

*I-V

RE + C {ri}

RS C B R=RS(V(H))

BD B - I=I0(V(H))*sinh(A(V(H))*V(B,-))+I00

RB + - {RPP}

*Auxiliary functions

.func I0(x)=imin+(imax-imin)*limit(0,1,x)

.func A(x)=amin+(amax-amin)*limit(0,1,x)

.func RS(x)=rsmin+(rsmax-rsmin)*limit(0,1,x)

.func VSB(x)=if(x>isb,vt,vs)

.func ISF(x)=if(gam==0,1,pow(limit(0,1,x),gam)-gam0)

.func TS(x)=exp(-etas*(x-VSB(I(BD))))

.func TR(x)= exp(etar*ISF(V(H))*(x-vr))

.func S(x)=1/(1+exp(-etas*(x-VSB(I(BD)))))

.func R(x)=1/(1+exp(-etar*ISF(V(H))*(x-vr)))

.ends

Acknowledgements: This work was funded by the WAKeMeUP 783176 project, co‐ funded by grants from the Spanish Ministerio de Ciencia, Innovación y Universidades (PCI2018‐093107 grant) and the ECSEL EU Joint Undertaking and by project TEC2017-84321- C4-4-R funded by the Spanish Ministerio de Ciencia, Innovación y Universidades. Dr. G. Patterson and Dr. A. Rodriguez are greatly acknowledged for their contributions to the development of the ideas reported in this work