[ICTA2026 ] Special OpenPDK Session

IEEE International Conference on Integrated Circuits, Technologies & Applications

ICTA 2026 Special Session “OpenPDK - Global FOSS Scholar Platform"

21st - 24th (Wed - Sat) October 2026

Grand Copthorne Waterfront Hotel, Singapore

The OpenPDK initiative delivers a global FOSS Scholar Platform supporting analog/RF, mixed‑signal, and digital IC design. Central to this effort are accurate SPICE models for low‑power sensing MOSFETs, RF HBTs, and emerging RRAM devices, validated across cryogenic temperatures for space and quantum‑computing applications. The initiative also advances Verilog‑A compact‑model standardization, ensuring result reproducibility and seamless integration into open‑source design flows. Supported by the EU Chips JU, OpenPDK fosters collaboration among academia, startups, and industry, while providing FOSS IC‑design tools covering schematic capture, simulation, layout, and verification up to tape‑out. Similar to the EU Chips JU program, Zhejiang CoreXin in China offers an open‑source PDK together with tape‑out services for its 55nm CMOS process. To accelerate the semiconductor‑industry development across the Asia‑Pacific and Southeast‑Asia regions, semiconductor model development and parameter extraction techniques should be pursued in a more focused manner. This special session brings together experts to present and discuss advances in device characterization, compact modeling, simulation methodologies, and validation techniques for a broad range of solid‑state devices, including Si, III/V semiconductors, power devices, nanoscale structures, and emerging 2.5D/3D advanced packaging technologies [ read more...]

ICTA 2026 Special OpenPDK Session Presenters

• SPICE/Verilog-A standard models and OpenPDK practice
  Wladek Grabinski, GMC Consulting, Switzerland
• Open-Source Ecosystem Updates and Semiconductor Design Development Programs in Japan
  Jun-ichi Okamura, AIST Solutions, OpenSUSI, Japan
• Open-Source EDA Meets Industrial IC Design
  Ehrenfried Seebacher, ams-OSRAM AG, Austria
• Building an Open-Source Process Platform, Empowering VLSI Innovation and Development
  Da Zhang, Zhejiang University/CTO, Zhejiang Chuangxin Integrated Process Platform, China
• From Silicon to Design: Intelligent Measurement and Modeling for DTCO
  Yutao Ma, VP of R&D, Primarius Technologies. Ltd. China
• Beyond Moore, Application-Driven IC Innovation International Cooperation Opportunities at NICE
  Alex Gu, National Innovation Center Par Excellence (NICE), China
• 2.5D/3D IC: AI+EDA Reshaping the System-Design-Technology Co0ptimization (STCO) Paradigm for Advanced Packaging
  Alex Zhao, Founder/CEO Zhuhai SiChip Technology Co., Ltd., China
• Modelling of semiconductor devices: the heart of innovation bridging academia and industrial applications
  Fujiang Lin, University of Science and Technology of China (USTC), China

Special OpenPDK Session progeam include the panel discussion: 

How to have a close loop for PDK, EDA, PDA and ICS simulation?

[ read more...]

[paper] 130-nm CMOS tunnel p-bit cell

Ju-Young Yoon, Nuno Caçoilo, Advait Madhavan, Jabez J. McClelland, Shun Kanai, Hideo Ohno, Shunsuke Fukami, and William A. Borders, 

"130-nm CMOS-integrated superparamagnetic tunnel junction-based p-bit," 

in IEEE Electron Device Letters, 

DOI: 10.1109/LED.2026.3696800

Abstract: Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ’s resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications. 

FIG: (a) Circuit diagram of the spintronic p-bit; b) Schematic cross-sectional structure of the spintronic p-bit. Transistors and lower interconnect layers were fabricated at SkyWater, followed by fabrication of the spintronic devices at Uni. Tohoku. (c,d) Cross-sectional and plan-view electron microscope images of the spintronic device designed to exhibit stochastic fluctuations.

Acknowledgements: This work was made possible by the NIST-led Nanotechnology Xccelerator program that distributes open-source circuit designs for integration of novel technologies on CMOS.

James D. Meindl, master of integrated circuits, dies at 87

Meindl was a visionary engineer who saw the potential of integrated circuits and was an early proponent of an interdisciplinary approach to engineering research [read more by Andrew Myers]

In 1984, electrical engineering professors James D. Meindl (right) and John Hennessy (center) brainstorm with research engineer John Shott about the MIPS project, which simplified computers with RISC architecture. (Image credit: Chuck Painter / Stanford News Service)

[ESSCIRC 2015] Low-power analog RF circuit design based on the inversion coefficient

[ref] Enz, Christian; Chalkiadaki, Maria-Anna; Mangla, Anurag, "Low-power analog/RF circuit design based on the inversion coefficient," in ESSCIRC 2015 - 41st , vol., no., pp.202-208, 14-18 Sept. 2015

Abstract: This paper discusses the concept of the inversion coefficient as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including velocity saturation. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design. The use of the inversion coefficient and the derived figures-of-merit for optimization and design is demonstrated through simple examples. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of a commercial 40-nm bulk CMOS process as well as with simulations using the BSIM6 model.

Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6

URL / doi: 10.1109/ESSCIRC.2015.7313863