[FSiC2026] Open EDA · Open Silicon · Sovereign by Design

FSiC2026

Free Silicon Conference 2026

Open EDA · Open Silicon · Sovereign by Design

What is FSiC? The annual gathering of the free and open-source silicon community building open EDA tools, open PDKs, and free hardware. Three days of talks and tutorials about designing chips with software you can read, share, and modify.

Who should come? Chip designers, EDA developers, researchers, students, and anyone curious about building silicon without proprietary lock-in. All experience levels welcome.

When? 6–8 July 2026

Where? University of Ljubljana, 

Faculty of Electrical Engineering

Tržaška cesta 25

SI-1000 Ljubljana

Registration closes 22 June: https://pretix.eu/FSiC/2026/

FSiC2026 Program: https://wiki.f-si.org/index.php/FSiC2026

[DATE2026] Open Source Related Talks

DATE 2026 Verona, Italy

Open Source Related Talks

Monday, 20 April - Wednesday, 22 April 2026

<https://date26.date-conference.com/programme>

Label	Title	Authors
TS02.8	ML-DSA-OSH: An Efficient, Open-Source Hardware Implementation of ML-DSA	Quinten Norga; Suparna Kundu; Ingrid Verbauwhede
LK03	Democratizing Silicon: The Rise of Open-Source EDA and Europe’s Strategic Roadmap	Luca Benini
TS10.1	PICOSNN: Partially Incoherent Configurable Optical Computing Architecture for SNN Acceleration	Bowen Duan; Zhenhua Zhu; Zhengyang Duan; Huazhong Yang; Yuan Xie; Yu Wang
TS16.1	Non-Volatile Spintronic Flip-Flops with Checkpoint Preservation Supported in RISC-V Platform	Jiongzhe Su; Mingtao Chen; Zhanpeng Qiu; Bo Liu; Hao Cai
LBR01.4	Float Fight - Verifying Floating-Point Behavior In Risc-V Simulators	Katharina Ruep, Manfred Schlaegl and Daniel Grosse
LBR01.7	Hybrid Virtual Platform + FPGA Co-Emulation Framework	Lorenzo Ruotolo; Giovanni Pollo; Mohamed Amine Hamdi; Matteo Risso; Yukai Chen; Enrico Macii; Massimo Poncino; Sara Vinco; Alessio Burrello; Daniele Jahier Pagliari
TS20.1	Fault-Tolerance Mapping of Spiking Neural Networks to RRAM-Based Neuromorphic Hardware	Yuqing Xiong; Chao Xiao; Zhijie Yang; Lei Wang; Mengying Zhao
TS21.4	Substrate: A Statically Typed Framework for Designing Highly Configurable Analog and Mixed-Signal Circuit Generators	Rahul Kumar; Rohan Kumar; Borivoje Nikolic
SD03	Open-Source Hardware Landscape
SD03.1	Open Silicon Fabrication – Made in Europe	Gerhard Kahmen, IHP GmbH, DE
SD03.2	From Schematic To Silicon: Mixed Signal Ic Design In Open Source Flows	Harald Pretl, JKU Linz, AT
SD03.3	Bringing Software Design Thinking To Chip Design	Tomi Rantakari, ChipFlow, GB

26th Workshop Analog Circuits

26th Workshop Analog Circuits 

12.03.2026 and 13.03.2026

at Leibniz University Hannover

The workshop series offers a platform to present one's own ideas and discuss results with science and industry. The focus is on integrated analog and mixed-signal circuits.

The workshop will take place on 12.03.2026 and 13.03.2026 in the Royal Horse Stable of the University of Hannover.  Registration - Participation in the workshop is free of charge.

The programme will be compiled after the call for papers has been completed and is avalable online 

In the run-up to the 26th Workshop on Analog Circuits, the DE:Sign cooperation event on the topic of "Open Source Tools for Analog Design" will take place on the morning of 12.03.2026. In this event, the funded projects will present their current status on open design tools and methods for analogue design. Participants will receive an overview of the contribution of the respective projects to the development of technology open, accessible, and sustainable design chains in the sense of the DE:Sign guideline.

If you have any questions, please contact the organizers by e-mail at: analog2026@ims.uni-hannover.de

Aalto Microelectronics Fair

Aalto Microelectronics Fair

March 20, 2026, 9.00-15.30

Aalto Yliopisto, Kandidaattikeskus, H304, Otakaari 1, 02150 Espoo

Time	Session
8:30–9:00	Morning coffee
9:00–9:15	Opening Aleksi Korsman
	Keynotes
9:15–10:00	Keynote 1: “OpenPDK - Global Scholar Platform”, Wladek Grabinski, Open PDK Initiative
10:05–10:50	Keynote 2: “Open Source Design Tools in SME IC Design Companies”, Ari Paasio, Kovilta
	Research overviews
11:00–11:15	Research overview: Kari Stadius
11:15–11:30	Research overview: Prof. Marko Kosunen
11:30–11:45	Research overview: Prof. Kwantae Kim
11:45–12:45	Lunch (and posters)
12:45–13:15	Student talk: “Five years of RISC‑V processor design at Aalto”, Aleksi Korsman
13:15–13:45	Student talk: “Beyond Neural Networks: Overcoming the Symbolic Bottleneck via Approximate Logarithm Acceleration”, Lingyun Yao
	Posters
13:45–14:00	Poster intro
14:00–15:00	Posters with coffee and snacks
15:00–15:30	Feedback and closing

Should you have any questions, please email Marko Kosunen

[chapter] Compact/SPICE Modeling

Wladek Grabinski and Daniel Tomaszewski

Compact/SPICE Modeling

In: Rudan, M., Brunetti, R., Reggiani, S. (eds) 

Springer Handbook of Semiconductor Devices

DOI 10.1007/978-3-030-79827-7_34

Abstract: The microelectronics and nano-electronics industry strongly relies on compact models to reduce a new microelectronic product development costs. The goals of this review are to highlight critical issues for the development of compact models for microelectronics and nano-electronics. In this chapter, we’ve covered the main principles of the compact device modeling. Also discussed are the possibilities of integrating compact models into circuit simulation and design tools, with an emphasis on the Verilog-A standardization, which simplify model implementation into EDA tool.

 

[open source hardware] selected examples

 SemiCoLab - Multi-project platform on ASIC

SemiCoLab is an educational project that seeks to democratize the complete integrated circuit design process. It allows students, teachers, and enthusiasts to design digital logic with open-source tools and fabricate it on a multiproject wafer, sharing costs and accelerating hands-on learning.

VSDSquadron Mini - RISC-V Development Kit

The VSDSquadron Mini, a versatile powerhouse within the RISC-V landscape that elevates your development to new heights. Whether you’re a newcomer delving into the realm of embedded systems or an experienced developer crafting an intricate device, the VSDSquadron Mini is your ideal companion. It seamlessly bridges the gap between theory and practical application, offering an on-board flash programmer with single-wire programming protocol to jumpstart your projects in education and development with proficiency and ease.

Watchy - A fully open source & customizable E-Ink watch

Watchy is an E-Ink watch with open source hardware and software. It has a barebones design utilizing the PCB as the watch body, allowing it to be worn as-is, or further customized with different 3D printed cases and watch straps. It is a unique timepiece that is also a wearable development platform, allowing users to create their own experience.

[Thesis] Verilog-A MOSFET Model for Analog IC Design

Verilog-A Based Implementation of a MOSFET Model for Analog Integrated Circuit Design

Master Thesis by Alba Gallego Velázquez

Defended: July 1, 2025

Technical University of Crete, Chania

Tutor: Prof. Matthias Bucher

Abstract: The present thesis sets out the development and implementation of a compact model of a MOSFET, based on the theoretical EKV model, and implemented using the Verilog-A language. The utilization of simulation and compilation environments, such as the open server OpenVAF and Ngspice, is instrumental in facilitating the effective execution of the work. The construction of a model that can perform the function of an nMOS or a pMOS nanometric operating in a saturated state is facilitated by these. In this model, physical dependencies and second-order effects are incorporated, ensuring the attainment of continuous expressions for all inversion regions. The model's behavior is validated against experimental data by means of simulation. This results in an accurate, compact and versatile model, which is suitable for supporting integrated analog circuits designs with a wide range of values for the inversion coefficient.

Fig: Normalized (𝐺𝑚𝑠 ·𝑈𝑡)/ID of the nMOS vs. the inversion coefficient (IC)

FOSSEE eSim Marathon – Circuit Design & Simulation with IHP SG13G2

Design, Simulate, Showcase

Unlock Open-Source VLSI Design  using eSim + IHP SG13G2 OpenPDK!!!

The eSim Marathon - Circuit Design & Simulation with IHP SG13G2 is a nationwide circuit design competition where participants use eSim, an open-source EDA tool developed by FOSSEE, IIT Bombay, to design and simulate circuits using the IHP OpenPDK for 130nm SG13G2 BiCMOS technology from IHP Microelectronics, Germany.

Key Highlights:

• Tool Used: eSim - a free and open-source alternative to commercial circuit design tools 
• OpenPDK Used: IHP SG13G2 - enables design of analog, digital, and RF circuits at 130 nm BiCMOS.
• Objective: Design, simulate, and submit functional analog/digital/mixed-signal circuits.
• Eligibility: Open to individuals - students, hobbyists, and early-career professionals.
• Learning Outcomes: Participants gain hands-on VLSI design experience using a real foundry OpenPDK, develop schematics, run simulations, and build documentation - entirely with open tools.

Register < https://esim-marathon.netlify.app/register/ >

Timeline

Date	Activity	Description
1 Sept. - 15 Sept. 2025	Registration for the Marathon	Complete the participation form
16 Sept. 2025	Marathon Inauguration Webinar	FOSSEE Team will introduce through eSim, IHP and Marathon process
16 Sept. - 23 Sept. 2025	Literature Survey	Participants need to research the topic available in papers/journals on the web
23 Sept. 2025	Report Submission	Submit one-page research conclusion and circuit implementation plan
23 Sept. - 5 Oct. 2025	Implementation	Design, characterise and simulate using eSim platform
5 Oct. - 8 Oct. 2025	Report Submission & Documentation	Upload reference and actual circuit/waveform using eSim
25 Oct. 2025	Result Declaration (Provisional)	Announcement of provisional results

[paper] Human Language to Analog Layout

Ali Hammoud, Chetanya Goyal, Sakib Pathen, Arlene Dai, Anhang Li, Gregory Kielian,
and Mehdi Saligane

Human Language to Analog Layout Using GLayout Layout Automation Framework

ACM/IEEE MLCAD 

https://doi.org/10.1145/3670474.3685971

Abstract: Current approaches to Analog Layout Automation apply ML techniques such as Graph Convolutional Neural Networks (GCN) to translate netlist to layout. While these ML approaches have proven to be effective, they lack the powerful reasoning capabilities, an intuitive human interface, and standard evaluation benchmarks that have been improving at a rapid development pace in Large Language Models (LLMs). The GLayout framework introduced in this work translates analog layout into an expressive, technology generic, compact text representation. Then, an LLM is taught to understand analog layout through fine-tuning and in-context learning using Retrieval Augmented Generation (RAG). The LLM is able to successfully layout unseen circuits based on new information provided in-context. We train 3.8, 7, and 22 Billion parameter quantized LLMs on a dataset of less than 50 unique circuits, and text documents providing layout knowledge. The 22B parameter model is tuned in 2 hours on a single NVIDIA A100 GPU. The open-source evaluation set is proposed as an automation benchmark for LLM layout automation tasks, and ranges from 2-transistor circuits to aΔΣ ADC. The 22B model completes 70% of the tasks in the evaluation set, and passes DRC and LVS verification on 44% of evaluations with verified correct blocks up to 4 transistors in size.

FIG: Full process of translating user prompt to a final layout.

Acknowledgments: The authors would like to thank the open-source community for their support.

 

[book] From Code to Chip

Jakob Ratschenberger and Harald Pretl

From Code to Chip:

Open-Source Automated Analog Layout Design

pp: XV, 120 Publisher: Springer Cham (10 January 2025)

eBook ISBN 978-3-031-68562-0

This book shows how the layout of an analog circuit can be automatically generated in a fully open-source way. Based on an exemplary design flow, it introduces and explains the necessary steps for transforming a SPICE netlist into a layout, which can be inspected by the open-source layout editor Magic VLSI. This is done by using the industry’s first open-source process design kit SKY130. Furthermore, the implementation of the design flow in the programming language Python is available as open-source on GitHub. 

Authors' Affiliations

Johannes Kepler University, Linz, Austria

Table of contents (8 chapters)

• Front Matter pp. i-xv
• Download chapter PDF 
• Introduction pp. 1-4
• Theoretical Basics pp. 5-13
• Circuit Capturing pp. 15-36
• PDK—Design Rule Capturing pp. 37-41
• Placement pp. 43-55
• Routing pp. 57-71
• Experimental Results pp. 73-99
• Outlook pp. 101-103
• Back Matter pp. 105-120

 

[paper] Strategic Thinking on Open-Source PDK

(Medium link)

Written by Jun-ichi OKAMURA

IEEE Senior member (Bio)

In 1990, NHK hailed Japan as an "lectronic powerhouse," spotlighting the semiconductor industry. Now, three decades later, the spotlight has swung back onto semiconductors - though the star this time is cutting-edge manufacturing technology. In this piece, however, The Author’d like to shift the focus to the design side of semiconductors. This article follows in the footsteps of several earlier posts: "The Tale of PDKs, Past and Present" posted Dec. 3, 2023; "A Qualitative Cost Analysis of the Semiconductor Business" posted Aug.1, 2024; and "Semiconductors We Want to Make, Semiconductors We Want to Use" posted Dec. 23, 2024. I’m grateful that these pieces still receive steady traffic, and The Author hopes they’ve helped broaden my understanding of the design aspects of semiconductors for those in the industry.

This time, under the title “Strategic Thinking on Open-Source PDK (Process Design Kit),” The Author aims to explain key points about open-source PDKs clearly. The discussion doesn’t stop at semiconductor designers — it also addresses perspectives relevant to foundries (semiconductor manufacturing service providers) and those planning semiconductor-related businesses. The Author hopes you’ll find it an engaging read and a helpful resource.

Note: The views expressed here are authors's own, based on past work experience, and do not represent any organization.

SSCS PICO Chronicle

Mirjana Videnovic-Misic, Harald Pretl, Ali Sabir, Zonghao (Chris) Li, 

and Sadayuki Yoshitomi

SSCS PICO Chronicles: news from the open source community

Date of current version: 14 November 2023

DOI: 10.1109/MSSC.2023.3315888

The Growing Activity of Open Source Chip Design in Japan

The Chipathon 2023 Team Japan consists of 12 volunteers from industry and academia. Since the team members are located in different parts of Japan, the team will be working remotely to design the project. On 4 August, they held a kickoff meeting where the members, who had been working together on Slack, gathered for the first time in person. Although many of the team members have no tape-out experience, they are all truly interested in IC design. The leader of Team Japan is Prof. Akira Tsuchiya at the University of Shiga in Japan (FIG).

Prof. Tsuchiya has been working on open source IC design and has been a volunteer member of the SSCS Chipathon since October 2022. He has promoted open source IC design and SSCS PICO activities in Japan. He held several hands-on events, for example, at the summer camp of the IE- ICE ICD in 2022. Also, he gave several talks about open source IC design and his research on analog synthesis in domestic conferences. And now, he has recruited members and applied to the latest Chipathon. Let’s look forward to the activities of the new members of “Team Japan.”

FIG: Prof. Akira Tsuchiya, an associate professor of the University of Shiga prefecture, 

Japan, and a snapshot of the kickoff meeting (hybrid) of the Chipathon 2023 Japan team

[C4P] WOSET 2024

Call for Papers

Workshop on Open Source EDA Technologies (WOSET)

https://woset-workshop.github.io/

Virtual! No registration fee! 

Submission Due Date: Sept 23 2024 

The WOSET workshop aims to galvanize the open-source EDA movement. The workshop will (virtually) bring together EDA researchers who are committed to open-source principles to share their experiences and coordinate efforts towards developing a reliable, fully open-source EDA flow. The workshop will feature presentations that overview existing or under-development open-source tools, designs and technology libraries. Break-out rooms will be utilized for discussion of works-in-progress. The workshop will feature a panel on the present status and future challenges in open-source EDA, and how to coordinate efforts and ensure quality and interoperability across open-source tools.

Topics of interest include, but are not limited to:

• Overview of an existing or under-development open-source EDA tool.
• Overview of support infrastructure (e.g. EDA databases and design benchmarks).
• Open-source cloud-based EDA tools
• Open-source hardware designs
• Position statements (e.g. critical gaps, blockers/obstacles)

Submission Information:

• All submissions must include links to open-source repositories with
•   all source code and an open-source license (BSD, GPL, Apache, etc.)
• Please reference your open-source repository!
• Review is single blind (anonymous reviewers).
• Videos will be put on the WOSET site if accepted.
• Virtual presentation for regular papers (in addition to archival video)
• Regular Paper Submissions (4 pages + 1 page references + 15 min video + virtual presentation)
• Work in Progress Submissions (2 page abstract + 1 page references + 10 min video + virtual zoom room)
• Submission site: https://openreview.net/group?id=WOSET-Workshop.github.io/2024

Important dates:

• Sept 23 2024 (end of day, anywhere in the world): submission due date.
• Oct 18 2024: notification date.
• Nov 8 2024: video due (if accepted)
• Nov 18 2024: workshop

Co-Chairs:

• Matthew Guthaus, UC Santa Cruz 
• Jose Renau, UC Santa Cruz

Program Chair:

• Dustin Richmond, UC Santa Cruz

Proceedings Chair:

• Dan Petrisko, University of Washington

Zoom Chair:

• Seeking volunteers to help run the virtual meeting

Program Committee:

• Jonathan Balkind, UC Santa Barbara
• Tim Edwards, efabless
• Steve Hoover, Redwood EDA
• Lucas Klemmer, JKU Linz
• Dirk Koch, University of Manchester
• Christian Krieg, TU Wien
• Rajit Manohar, Yale University
• Guillem Lopez Paradis, Barcelona Supercomputing Center
• Frans Skarman, Linköping University
• Matt Venn, YosysHQ, TinyTapeout

[paper] anybody can design and build a chip

Krzysztof Herman, Norbert Herfurth, Tim Henkes, Sergei Andreev, Rene Scholz, Markus Müller, Mario Krattenmacher, Harald Pretl, and Wladyslaw Grabinski

On the Versatility of the IHP BiCMOS Open Source and Manufacturable PDK: 

A step towards the future where anybody can design and build a chip

IEEE Solid-State Circuits Magazine, vol. 16, no. 2, pp. 30-38, Spring 2024

DOI: 10.1109/MSSC.2024.3372907

Abstract: In this article, we introduce the first European open source process design kit (PDK), namely IHP-Open130-G2. We provide a concise history of the PDK itself and offer a brief comparison with some alternative open source PDKs, such as SKY130 and GF180MCU. The article also includes a process description and details on deliverables, offering insights into available devices, models, supported open source tools, and workflows. As the IHP-Open130-G2 is currently under development, we present key points outlining future activities. This aims to inform and attract users to join the open source silicon community. The concluding section of the article compares measurement results for active devices with compact model results. The article concludes with a cryptographic Internet protocol (IP) core based on IHP-Open130-G2 as an exemplary use case.

FIG: Silicon Proven Application: The final layout of the HEP custom cryptographic IP core.

[REF] “130nm BiCMOS open source PDK, dedicated for analog, mixed signal and RF design.” GitHub. Online: https://github.com/IHP-GmbH/IHP-Open-PDK

[Latch-Up] IHP Open Source PDK

IHP Open Source PDK:

Announcement, Setup, Current State and Experiences, and look ahead

Frank Vater, IHP Frankfurt (Oder), Germany

Latch-Up 2024 video

Abstract: Main focus of this talk is the SG13G2 Open Source PDK for IHP 130nm BiCMOS technology. The current state of our activities will be given for the analogue as well as for the digital PDK including design flow with open source tools. Some more details on first experiences for schematic driven design, simulation, layout, DRC and LVS will be pointed out. Furthermore, already known challenges analogue and digital design flow and open issues on open source tool chain will be addressed. The talk will be closed with a road map for future work.

Latch-Up: a weekend of presentations and networking for the open source silicon community, much like its European sister conference ORConf.

Produced by NDV: @nextdayvideo
OpenHardware Sat Apr 20 16:20:00 2024 at b45r230

[Kick-off] Chipdesign Germany

Chipdesign Germany

Das Netzwerk für Chipdesign in Deutschland

https://www.chipdesign-germany.de/

OnLine Registrierung: https://eveeno.com/auftaktchipdesigngermany

Juni 6. Donnerstag

13:00 Ankunft & Registrierung
14:00 Eröffnung
14:00 Begrüßung

Holger Blume; Leibniz Universität Hannover & edacentrum e.V.

14:15 Grußworte

Apollonia Pane Bundesministerium für Bildung und Forschung 

14:30 Vorstellung Chipdesign Germany

Holger Blume; Leibniz Universität Hannover & edacentrum e.V.
Norbert Wehn; Rheinland-Pfälzische Technische Universität Kaiserslautern-Landau

14:45 Keynote-Session I

14:45 Open-Source EDA and Innovation Leadership
Andrew B. Kahng; University of California San Diego, US

15:45 Kaffeepause
16:30 Keynote-Session II

16:30 Open Source Chip Design: Europas Weg zur Wettbewerbsfähigkeit in einer geteilten Tech-Welt?

Jan-Peter Kleinhans; Stiftung Neue Verantwortung

17:30 Mikroelektronik in digitalen Hörhilfen: Chips, die hören helfen

Joachim Thiemann; Advanced Bionic

18:30 Networking-Veranstaltung mit Poster- & Demo-Session

Juni 7. Freitag

08:30 Eröffnung
08:30 Begrüßung

Holger Blume; Leibniz Universität Hannover & edacentrum e.V

08:45 Keynote-Session III
08:45 Neue Fertigungstechnik für die Chipverarbeitung

Lutz Rissing; Dr. Johannes Heidenhain GmbH

09:45 Kaffeepause
10:30 DE:Sign Präsentationen

BMBF-Förderlinie "Design-Instrumente für souveräne Chipentwicklung mit Open-Source (DE:Sign)"

10:30 DI-OCRCpro

Daniel Krupka; Gesellschaft für Informatik e.V.

10:45 DI-DEMICO

Frank Ellinger; Technische Universität Dresden

11:00 DI-DERAMSys

Matthias Jung; Julius-Maximilian-Universität Würzburg

11:15 DI-OWAS

Dirk Koch; Ruprecht-Karls-Universität Heidelberg

11:30 DI-PASSIONATE

Robert Weigel; Friedrich-Alexander Universität Erlangen-Nürnberg

11:45 Interaktive Poster-Session
13:30 Verabschiedung

Adresse: Königlicher Pferdestall - Leibniz Universität Hannover; Appelstr. 7, 30167 Hannover
OnLine Registrierung: https://eveeno.com/auftaktchipdesigngermany

[FOSSEE] Better Education

FOSSEE (Free/Libre and Open Source Software for Education) project promotes the use of free open source software (FOSS) tools in academia and research. The FOSSEE project is part of the National Mission on Education through Information and Communication Technology (ICT), Ministry of Education (MoE), Government of India. 

Below is the list of projects which are promoted by FOSSEE.

• Scilab 
  free/libre and open source software for numerical computation developed by Scilab Enterprises, France. Scilab also includes Xcos which is an open source alternative to Simulink.
• Python 
  general-purpose, high-level, remarkably powerful dynamic programming language that is used in a wide variety of application domains. It supports multiple programming paradigms.
• eSim 
  (formerly known as Oscad/FreeEDA) is an EDA tool for circuit design, simulation, analysis and PCB design. It is developed by the FOSSEE team at IIT Bombay 
• Osdag 
  free/libre and open-source software which allows the user to design steel structures using a graphical user interface. The GUI also provides 3D visualization of the designed component and images
• DWSIM 
  free/libre and open source CAPE-OPEN compliant chemical process simulator. Helps understand the behavior of Chemical Systems by using rigorous thermodynamic and unit operations models.
• OpenFOAM 
  free/libre and open source CFD toolbox useful to solve anything from complex fluid flows involving chemical reactions, turbulence and heat transfer, to solid dynamics and electromagnetics.
• OpenModelica 
  free/libre and open source environment based on the Modelica modelling language for modelling, simulating, optimising and analysing complex dynamic systems.
• OpenPLC 
  free/libre and open source Programmable Logic Controller creating opportunities for people to study its concepts, explore new technologies and share the resources.
• FLOSS-Arduino
  control of Arduino using Free/Libre Open-Source Software. The interface helps the user to perform embedded systems experiments on the Arduino Uno board.
• SBHS
  (Single Board Heater System) is a lab-in-a-box setup useful for teaching and learning control systems.
• R 
  programing language and environment for statistical computing and graphics.
• QGIS
  (Quantum GIS) is a free and open-source desktop Geographic Information System (GIS) application.
• FOCAL 
  an initiative by FOSSEE to promote Open Source Software in computer graphics.
• SOUL
  (Science OpensoUrce Software for Teaching Learning) is a collection of ICT software that can be used as teaching/learning tools by the community of educators and the learners to teach/ learn the basic as well as the advanced concepts in science subjects

[paper] Open-source design of integrated circuits

Patrick Fath, Manuel Moser, Georg Zachl. Harald Pret

Open-source design of integrated circuits

Elektrotech. Inftech. (2024)

DOI: 10.1007/s00502-023-01195-5

* Institute for Integrated Circuits, Johannes Kepler University Linz, Austria

Abstract: This paper presents the design of a self-clocked 12-bit non-binary fully differential SAR-ADC using the SKY130 open-source PDK. The entire mixed-signal circuit design and layout were created with free and open-source software. The ADC reaches a sample rate of up to 1.44MS/s at 1.8V supply while consuming 703μW of power on a small 0.175mm area. A configurable decimation filter can increase the ADC resolution up to 16 bits while using an oversampling factor of 256. A 9‑bit thermometer-coded and 3‑bit binary-coded DAC matrix using a 448 aF waffle-capacitor results in a total capacitance of 1.83pF per input. Realizations of configurable analog functions using the form factor of SKY130 high-density standard cells allow the parametrization of an analog circuit in a hardware description language and hardening of the macro in an intentionally digital workflow.

FIG: Block diagram of the proposed open-source design flow,

including the essential tools and used/generated files

Acknowledgements: The authors thank Johannes Kepler University for funding the open-access publication, Google and SkyWater Technologies for igniting this recent wave of open-source IC design, and the large crowd of enthusiasts spending their time on developing and maintaining an extensive array of exciting open-source EDA projects. Open access funding provided by Johannes Kepler University, Linz.

ISHI-kai January 2024 event

2024年1月イベント「オープンソースPDK団体」勉強会国内外のオ
ープンソースPDKやEDAの状況について、キーマンに語っていただきます

With the recent rise in the semiconductor industry, the movement of open source PDK and EDA in Japan and overseas has become active. Therefore, in this study session, key people will talk about the status of open source PDK and EDA in Japan and overseas.

Schedule

Friday, January 26, 2024, 18:00-21:00 (Reception: 18:30)

Venue (onsite)

Google Shibuya Office
3-21-3 Shibuya, Shibuya-ku, Tokyo
Shibuya Stream Google reception meeting

Online Broadcast: 

Google Meet: https://meet.google.com/ksa-tjaw-ges

Participation Fee

free

Timetable

Time	Speaker	Title	Lecture Outline
Until 18:30	ISHI-kai	reception	The entrance to the facility closes at this time, so if you are participating locally, please come by this time as much as possible.
18:00 ～ 18:30	ISHI-kai	Chat time	-
18:30 ~ 19:15 (Lecture: 30min, Q&A: 15min)	Takeshi Hamamoto Minimal Fab Propulsion Organization Device Engineer	minimal Fab open PDK	1) What is a minimal fab 2) openPDK 3) Design Contest at Semicon 2023
19:15 ~ 20:00 (Lecture: 30min., Q&A: 15min.)	Junichi Okamura IEEE Senior Member	OpenPDK and the World	-
20:00 ~ 20:45 (Lecture: 30min., Q&A: 15min.)	@noritsuna	About the upcoming open source PDK shuttle	(To be released at a later date)
21:00	ISHI-kai	closing

What is ISHI-kai?

The association was named ISHI-kai (Inter-linked Society on Homemade IC Kai). The name was conceived from the Society Community (Association) that handles open (democratized) ISHI = stone = Silicon = semiconductors (ASIC/LSI/IC) and connects various fields.

OpenMPW (Open Multi Project Wafer), which appeared as a forerunner, is a shuttle program created by Google investing in Efabless, and includes the tools necessary for making semiconductors (ASIC/LSI/IC) (EDA/PDK) to ISHI manufacturing in IC fabs). This is exactly the "openness of semiconductors (ASIC/LSI/IC) and EDA/PDK" of the open source movement (democratization of software) that started with GNU!

Therefore, this association was established as a user society community (association) that focuses not only on experts in semiconductors (ASIC/LSI/IC) in the past, but also on those who see the potential of the open source movement of semiconductors (ASIC/LSI/IC) in the future and those who want to create new semiconductors (ASIC/LSI/IC).

We/ISHI-kai will continue to work toward a world where semiconductors (ASIC/LSI/IC) and EDA/PDK can be used by everyone, just as OSs, compilers, libraries, apps, electronic boards, 3D CAD and 3D printers that we/ISHI-kaire only available to experts can now be used by everyone as open source software, open hardware, open modeling, etc.

As for the future activity plan, we/ISHI-kai have a policy of revolutionizing the semiconductor (ASIC/LSI/IC) field by involving people from other fields, and we/ISHI-kai will hold events such as hands-on seminars for ultra-beginners for other fields and in-depth study sessions for experts, form a team to challenge the OpenMPW shuttle and Chipathon from around the world, and Maker we/ISHI-kai would like to participate in events such as Faire, so thank you.

Precautions

As events move online, we/ISHI-kai ask participants to act in accordance with the spirit of the Code of Conduct. If you have any problems, please contact the organizer. If it is judged that there is no improvement in the request even if there is no abuse such as vandalism or malicious intent, we/ISHI-kai may respond on a case-by-case basis. 

https://www.contributor-covenant.org/ja/version/2/0/code_of_conduct/

Acknowledgements

Thanks to the kindness of Google for providing a real/onsite venue.

[webinar] Open Source Silicon Landscape

Unveiling the Open Source Silicon Landscape: 

a cutting-edge approach for the European semiconductor industry

5 December 2023

Who should attend and why:

• Policymakers at the regional, national, and European level who want to strengthen their respective semiconductor ecosystem while collaborating and contributing to the Union’s industry as a whole
• Research and academia representatives who are interested in deepening their knowledge or discovering the potential of the Open Source Silicon landscape
• SMEs in the semiconductor industry who aim to expand and innovate their business by using a cutting-edge approach
• Start-ups that are eager to elevate their business to the next level by embracing vanguard strategies
• Citizen scientists and the general public who would like to have a better understanding of the new horizons in the semiconductor landscape
• Experts active in industrial development who are interested in integrating potential new approaches

Registration:

The event is free of charge, but registration is mandatory. Registrants will receive the link to access the event by email.

Agenda:

11:00 - 11:05	Welcome
11:05 - 11:10	Introducing Open Source Silicon
11:10 - 11:20	BACKGROUND Open source silicon between software and hardware Background
11:20 - 11:40	POLICY BRIEF PRESENTATION Open source silicon’s position in the semiconductor value chain
11:40 - 12:35	PANEL Key opportunities and threats relevant to open source silicon strategies
12:35 - 12:45	Q&A and conclusions