Patrick Fath and Harald Pretl
A 44-GHz Logarithmic Power Detector with 62 dB Dynamic Range and –56 dBm Sensitivity
in 130-nm SiGe BiCMOS Using Open-Source EDA
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Fukuoka, Japan, October 2026
Abstract: This paper presents a 44-GHz logarithmic RF power detector implemented in the open-source IHP SG13G2 130nm SiGe BiCMOS OpenPDK using exclusively open-source EDA tools. The proposed detector is based on a six-stage successive detection logarithmic video amplifier architecture with integrated square-law detectors, followed by a transimpedance amplifier and an output buffer. To achieve both low noise and high speed, two different limiting-amplifier topologies are employed within the successive detection logarithmic video amplifier, namely a low-noise differential common-emitter input stage and high-speed Cherry-Hooper stages. A tunable proportional-to-absolute-temperature constant-gm bias generator is used to reduce the temperature dependency of the amplifier gain, while duty-cycled operation is supported to lower the average power consumption. Post-layout simulations show a passband gain of 64 dB, a frequency range from 0.15 GHz to 44.7 GHz, a sensitivity of-56 dBm, and a dynamic range of 62 dB. In addition, RF stability is verified over the investigated frequency range, and the detector achieves an estimated video bandwidth of 114 MHz. The total power consumption is 95.7 mW in continuous operation and is reduced to 48.1 mW in duty-cycled operation. The active area is 0.43 mm^2, while the die size including pads is 1.4×1.2 mm^2. These results demonstrate that competitive wideband logarithmic RF power detectors extending into the mm-wave range can be realized using open-source design infrastructure.
Fig. (a) Transient response of the detector under duty-cycled operation, showing pon (dashed gray) and Vlog, out (solid blue). (b) Layout of the detector (1.4×1.2 mm^2) with the individual building blocks outlined
