It is based on 2nm GAAFET with BSPDN. All the device models are based on 3-stack nanosheets
Standard cell layouts can also be imported using the .gds file: GT2N/gds/gt2_6t_std_cells.gdsLVS and DRC rulesets for icvalidator are present in "GT2N/icv_runset".
Libraries are composed of 3 process corners (under development), 2 nanosheet width (W) flavors, and 5 threshold voltage (VT) flavors. (In the order of decreasing VT, HVT > SVT > LVT > ULVT > ELVT)
The collaterals required for synthesis and PnR are (depending on the process corner and W/VT flavor):
The thermal-calibrated GAAFET (3-stack nanosheet) model card is (depending on the process corner and W/VT flavor):
Libraries are composed of 3 process corners (under development), 2 nanosheet width (W) flavors, and 5 threshold voltage (VT) flavors. (In the order of decreasing VT, HVT > SVT > LVT > ULVT > ELVT)
The collaterals required for synthesis and PnR are (depending on the process corner and W/VT flavor):
LIB: GT2N/lib/tt/gt2_6t_w31_lvt_tt_0p7v25c.lib
LEF: GT2N/lef/tt/gt2_6t_w31_lvt.lef
Techlef: GT2N/techlib/gt2_tech.lef
ICT: GT2N/qrc/GT2.ict
QRCTech: GT2N/qrc/GT2_qrc.tch
ITF: GT2N/nxtgrd/GT2.itf
NXTGRD: GT2N/nxtgrd/GT2.nxtgrd
The thermal-calibrated GAAFET (3-stack nanosheet) model card is (depending on the process corner and W/VT flavor):
GT2N/device/tt/gt2_w31_lvt_tt.sp
[ref] D. Jang, P. Kumar, M. N. H. Shazon, S. J. Ram, A. Svizhenko, V. Moroz, A. Ceyhan, N. A. Radhakrishn, and A. Naeemi, "GT2N: An Open-Source 2nm Nanosheet PDK Enabling Multi-Width/VT Benchmarking" in IEEE International Symposium on Circuits and Systems (ISCAS) 2026
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