[Program] MINI-COLLOQUIUM ON CAD/EDA MODELING

MINI-COLLOQUIUM ON CAD/EDA MODELING

Sala de Graus, Campus ETSE/ETSEQ

Department of Electronic, Electrical and Automatic Control Engineering, 

University Rovira i Virgili Tarragona, Catalonia, Spain

Chairperson: 

Benjamin Iñiguez, EDS BoG Member and Chair of the ED Spain Chapter

Tuesday, June 28 2022

8:20-8:30 Overview, B. Iñiguez
8:30-9:30 “Characterization and TCAD modeling based design assessment of ultra-high voltage SiC devices,” Muhammad Nawaz (Hitachi Energy, Sweden)
9:30-10:30 “Nanoscale InGaAs FinFETs: Band-to-Band Tunneling and Ballistic Transport,” Jesús del Alamo (MIT, USA)

10:30-11:00 Coffee break

11:00-12:00 “Physics-Based Parameter Extraction for Thin Film Transistors,” Arokia Nathan (Darwin College, University of Cambridge, UK)
12:00-13:00; “Characterization and modeling of organic solar cells,” Lluís F. Marsal (University Rovira I Virgili, Tarragona, Spain)

13:00-15:00 Lunch

15:00-19:00 Meeting of the EDS SRC Region 8 Executive Committee

Wednesday, June 29 2022

11:00-12:00 “Trends and challenges in Nanoelectronics for the next decade,” Elena Gnani (University of Bologna, Italy)
12:00-13:00,“SPICE and Verilog-A Modelling Using FOSS TCAD/EDA Tools: Technology - Devices – Applications” (virtual), Wladek Grabinski (GMC, Switzerland)

13:00-14:20 Lunch

Joint Session 

• MQ on CAD Modeling
• Graduate Student Meeting on Electronic Engineering

14:20-14:30 Overview, B. Iñiguez and J. Ferré-Borrull
14:30-15:30 “Compact modeling of memristive devices for neuromorphic computing,” (virtual) Enrique Miranda (Autonomous University of Barcelona, Spain)
15:30-16:30 Physical Principles to Formulate Thin Film Transistor Models for Circuit Design (virtual), Samar Saha (Prospicient Devices, USA)

16:30-16:35 Closing remarks, B. Iñiguez

ASCENT project

Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies

The Mission of the ASCENT Center is to transcend the current limitations of high-performance transistors confined to a single planar layer of integrated circuit by pioneering vertical monolithic integration of multiple interleaved layers of logic and memory, by demonstrating beyond-CMOS device concepts that combine processing and memory functions, heterogeneously integrating functionally diverse nano-components into integrated microsystems and by demonstrating in-memory compute kernels to accelerate future data-intensive at-scale cognitive workloads.

Researchers at ASCENT pursue four areas of technology including three-dimensional integration of device technologies beyond a single planar layer (vertical CMOS); spin-based device concepts that combine processing and memory functions (beyond CMOS); heterogeneous integration of functionally diverse nano-components into integrated microsystems (heterogeneous integration fabric); and hardware accelerators for data intensive cognitive workloads (merged logic-memory fabric).

ASCENT is one of six research centers funded by the SRC’s Joint University Microelectronics Program (JUMP), which represents a consortium of industrial participants and the Defense Advanced Research Projects Agency (DARPA). Information about the SRC can be found at https://www.src.org/.

ASCENT is a collaboration of the following Universities: