Congratulations to Prof. Robert W. Dutton

The 2020 IEEE EDS Celebrated Member and Esteemed EDS Alumni

Dr. Dutton received his degrees from the University of California, Berkeley, and currently instructs electrical engineering at Stanford University. Current members of EDS take pride in the Celebrated Members' accomplishments, drawing from their achievements as inspiration to advance and achieve success in various fields. The award presentation will be held virtually during the 2020 IEDM in December [read more...]

ROBERT W. DUTTON

Robert W. Dutton received the B.S., M.S., and Ph.D. in Electrical Engineering degrees from the University of California, Berkeley, in 1966, 1967, and 1970, respectively. 

He is currently Robert and Barbara Kleist Professor of Electrical Engineering at Stanford University, and Associate Chair for Undergraduate Education. He has held summer staff positions at Fairchild, Bell Telephone Laboratories, Hewlett‐Packard, IBM Research, and Matsushita during 1967, 1973, 1975, 1977, and 1988 respectively. His research interests focus on integrated circuit process, device, and circuit technologies, especially the use of computer‐aided design (CAD) and parallel computational methods. He has published more than 200 journal articles and graduated more than four dozen doctorate students. 

Dr. Dutton was Editor of the IEEE Transactions on Computer Aided Design from 1984 to 1986, the winner of the 1987 IEEE J. J. Ebers Award, 1988 Guggenheim Fellowship to study in Japan, elected to the National Academy of Engineering in 1991, 1996 Jack A. Morton Award, 2000 C&C Prize Japan, University Researcher Award, Semiconductor Industry Association (2000), Phil Kaufman Award, Electronic Design Automation Consortium (2006), and 2014 Bass University Fellow in Undergraduate Education Program, Stanford University.

[C4P] IEDM 2017

2017 IEDM CALL FOR PAPERS

The Annual International Electron Devices Meeting will be held at the Hilton San Francisco Union Square San Francisco, CA December 2-6, 2017

Abstract Deadline (four page final paper): August 2nd, 2017

To provide faster dissemination of the conference’s cutting-edge results, the abstract submission deadline has been moved to August 2nd for submission of four-page, camera-ready abstracts. Accepted papers will be published as-is in the proceedings

A Call for Papers flyer is available here: IEDM 2017 Call For Papers.

Customized Call for Papers for each of the technical subcommittee areas are also available:

• Circuit and Device Interaction (CDI)
• Characterization, Reliability, and Yield (CRY)
• Compound Semiconductor and High Speed Devices (CHS)
• Memory Technology (MT)
• Modeling and Simulation (MS)
• Material and interface modeling 
• Compact models
• Kinetic Monte Carlo and Molecular Dynamics
• Reliability and variability modeling
• Technology benchmarking
  New or trending areas include:
• First principle based quantum transport
• Process simulation with atomistic methods
• Self heating, interconnect and packaging
• Nano Device Technology (NDT)
• Optoelectronics, Displays, and Imagers (ODI)
• Power Devices (PD)
• Process and Manufacturing Technology (PMT)
• Sensors, MEMS, and BioMEMS (SMB)

2016 IEDM Tutorials

2016 International Electron Devices Meeting Tutorials

The tutorials are in their sixth year and are 90 minute stand-alone presentations on specialized topics taught by world-class experts. These tutorials provide a brief introduction to their respective fields, and facilitate understanding of the technical sessions. The tutorial sessions will take place on Saturday, Dec.3, 2016. Three tutorials are given in parallel in two time slots, at 2:45 p.m.and 4:30 p.m. respectively.

Topics presented at 2:45pm - 4:15pm:

• The Struggle to Keep Scaling BEOL, and What We Can Do Next
  Rod Augur, Distinguished Member of the Technical Staff, GlobalFoundries
• Physical Characterization of Advanced Devices
  Robert Wallace, Univ. Texas at Dallas
• Spinelectronics: From Basic Phenomena to Magnetoresistive Memory (MRAM) Applications
  Bernard Dieny, Chief Scientist, Spintec CEA

Topics presented at 4:30pm - 6:00pm:

• Electronic Circuits and Architectures for Neuromorphic Computing Platforms
  Giacomo Indiveri, Univ. of Zurich and ETH Zurich
• Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation
  Ben Kaczer, Principal Scientist, IMEC
• Embedded Systems and Innovative Technologies for IoT Applications
  Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor

Register for the IEDM tutorials here: http://ieee-iedm.org/onsite-registration-center/online-registration/

IEDM 2016 Session 7: Modeling and Simulation Advanced Numerical and Compact Models

IEDM 2016 Session 7

Modeling and Simulation Advanced Numerical and Compact Models

Monday, December 5, 1:30 p.m. Continental Ballroom 7-9 

Co-Chairs: Denis Rideau, STMicroelectronics 

Xing Zhou, Nanyang Technological University

1:35 PM 

7.1 A Novel Synthesis of Rent's Rule and Effective-Media Theory Predicts FEOL and BEOL Reliability of Self-Heated ICs, W. Ahn, H. Jiang, S.H. Shin and M. Alam, Purdue University

2:00 PM 

7.2 New Approach for Understanding "Random Device Physics" from Channel Percolation Perspectives: Statistical Simulations, Key Factors and Experimental Results, Z. Zhang, Z. Zhang, R. Wang, X. Jiang, S. Guo, Y. Wang, X. Wang*, B. Cheng*, A. Asenov* and R. Huang, Peking University, *Synopsys

2:25 PM 

7.3 Oxide-Based Analog Synapse: Physical Modeling, Experimental Characterization, and Optimization, B. Gao, H. Wu, J. Kang*, H, Yu**, H. Qian, Tsinghua University, *Peking University, **Southern University of Science and Technology

2:50 PM 

7.4 Extending the Bounds of Performance in E-mode p-channel GaN MOSHFETs, A. Kumar and M. De Souza, The University of Sheffield

3:15 PM 

7.5 NSP: Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs, O. Rozeau, S. Martinie, T. Poiroux, F. Triozon, S. Barraud, J. Lacord, Y.-M. Niquet*, C. Tabone, R. Coquand, E. Augendre, M. Vinet, O. Faynot, and J.-C. Barb, CEA-Leti, *CEA-INAC

3:40 PM 

7.6 A Physics-Based Compact Model for Material- and Operation-Oriented Switching Behaviors of CBRAM, Y. Zhao, J. Hu, P. Huang, F. Yuan*, Y. Chai*, X. Liu and J. Kang, Peking University, *The Hong Kong Polytechnic University

4:05 PM 

7.7 Multi-Domain Compact Modeling for GeSbTe-based Memory and Selector Devices and Simulation for Large-scale 3-D Cross-Point Memory Arrays, N. Xu, J. Wang, Y. Deng, Y. Lu, B. Fu, W. Choi, U. Monga*, J. Jeon*, J. Kim*, K.-H. Lee* and E. S. Jung*, Samsung Semiconductor Inc., *Samsung Electronics

[read more...]

IEDM: Modeling and Simulation – Compact Modeling

 IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. This year IEDM technical program also includes a series of the compact modeling papers:

[9.6] GaNFET Compact Model for Linking Device Physics, High Voltage Circuit Design and Technology Optimization, U. Radhakrishna, S. Lim, P. Choi, T. Palacios, and D.A Antoniadis, Massachusetts Institute of Technology
[28.1] Transport Mechanism in sub 100C Processed High Mobility Polycrystalline ZnO Transparent Thin Film Transistors, P.B. Pillai, and M.M. De Souza, University of Sheffield
[28.2] Physical-based Analytical Model of flexible a-IGZO TFTs Accounting for Both Charge Injection and Transport, M. Ghittorelli, F. Torricelli, J.L. Van Der Steen*, C. Garripoli**, A. Tripathi*, G. Gelinck*, E. Cantatore**, Z. Kovacs-Vajna, University of Brescia, *Holst Centre, TNO, **Eindhoven University of Technology
[28.3] Predictive Compact Modeling of Random Variations in FinFET Technology for 16/14nm Node and Beyond, X. Jiang, X. Wang*, R. Wang, B. Cheng**, A. Asenov*, and R. Huang, Peking University, *University of Glasgow, **Gold Standard Simulations (GSS) Ltd.
[28.4] A New Surface Potential Based Physical Compact Model for GFET in RF Applications, L. Wang, S. Peng, Z. Zong, L. Li, W. Wang, G. Xu, N. Lu, Z. Ji, and M. Liu, Chinese Academy of Sciences
[28.5] Physics-based Compact Modeling Framework for State-of-the-Art and Emerging STT-MRAM Technology, N. Xu, J. Wang, Y. Lu, H.-H. Park, B. Fu, R. Chen, W. Choi, D. Apalkov, S. Lee*, S. Ahn*, Y. Kim*, Y. Nishizawa**, K.-H. Lee, Y. Park, Samsung Semiconductor Inc, *Samsung Electronics, **Samsung R&D Institute Japan
[28.6] Physics-based Compact Modeling of Charge Transport in Nanoscale Electronic Devices (Invited), S. Rakheja, and D. Antoniadis*, New York University, *Massachusetts Institute of Technology

The compact/SPICE modeling and its Verilog-A standardization will be also discussed at two following engineering events organized by MOS-AK Group and the CMC which are collocated with the IEDM in Washington DC in December, later this year.

[online MOS-AK and CMC registration]

• MOS-AK Workshop in Washington DC (Dec.9) 
• http://www.mos-ak.org/washington_dc_2015/
• CMC Meeting at Sheraton Suites Old Town Alexandria (Dec.10-11)
• https://www.si2.org/openeda.si2.org/4Q_2015_CMC_Meeting.php

55th IEEE IEDM conference

The 55th annual IEEE IEDM conference will be held at the Hilton Baltimore on December 7-9, 2009 preceded by a day of Short Courses on Sunday, Dec. 6. The world¹s best scientists and engineers in the field of electronics will showcase their work in a program of papers, panels, special sessions, Short Courses and other events that will spotlight more leading work in more areas of the field than any other conference.

The advance registration deadline is November 16 and the deadline for hotel reservations is November 6. For registration and other information, visit the IEDM 2009 home page at http://www.ieee-iedm.org

As a novelty, IEDM can be followed in twitter and facebook... which I think is a good move.