[paper] Editorial Special Section on ESSDERC

IEEE TED, Vol. 67, No. 11, November 2020

Mid-September 2020, we were supposed to celebrate in Grenoble the 50th anniversary of the European SolidState Device Research Conference and European Solid-State Circuits Conference (ESSDERC-ESSCIRC), which is the most important European conference dedicated to solid-state devices and circuits. However, in April 2020, more than one-third of the global population was under severe lock-down as a result of the protective public health measures imposed by the different governments, states, or provinces. Because of the COVID-19 pandemic, the ESSDERC-ESSCIRC organizing and steering committees, together with the sponsoring SSCS and EDS IEEE societies, decided to reschedule the in-person conference to September 6–9, 2021, in Grenoble, to add new virtual “Educational Events” held on September 14 and 15, 2020 (presentations available till October 16, 2020, at https://www.esscirc-essderc2020.org/) as well as to invite the ESSDERC-ESSCIRC research community to submit publications to the IEEE TRANSACTIONS ON ELECTRON DEVICES (TED) and to the IEEE SOLID-STATE CIRCUITS LETTERS (SSC-L), respectively, in a brief format. All of these initiatives met great success. Especially, more than 47 TED submissions were received and reviewed, and 32 papers were accepted and have been included in this dedicated section of the November TED issue.

We would like to thank all the authors for taking this opportunity to keep the ESSDERC-ESSCIRC momentum, all the IEEE reviewers for their reactivity, and all the ESSDERC-ESSCIRC sponsors for their trust in this difficult time. Let us think with a positive mind, and acknowledge that this experience opens a new and fruitful collaboration between ESSDERC and TED.

We hope you will enjoy reading these high-quality papers. Stay safe

FRANCOIS ANDRIEU, TPC Chair
CEA-Leti
Université Grenoble Alpes
38054 Grenoble, France

GIOVANNI GHIONE, Editor-in-Chief
Dipartimento di Elettronica e Telecomunicazioni
Politecnico di Torino
10129 Torino, Italy

Editorial Special Section on ESSDERC

 IEEE TED, Vol. 67, No. 11, November 2020

1. Generalized Constant Current Method for Determining MOSFET Threshold Voltage M. Bucher, N. Makris, and L. Chevas pp.4559
2. Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications (Invited Paper) B. Cardoso Paz, M. Cassé, C. Theodorou, G. Ghibaudo, T. Kammler, L. Pirro, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4563
3. A Method for Series-Resistance-Immune Extraction of Low-Frequency Noise Parameters in Nanoscale MOSFETs A. Tataridou, G. Ghibaudo, and C. Theodorou pp.4568
4. Analytical Model for Interface Traps-Dependent Back Bias Capability and Variability in Ultrathin Body and Box FDSOI MOSFETs W. Chen, L. Cai, X. Liu, and G. Du pp.4573
5. Polarization Independent Band Gaps in CMOS Back-End-of-Line for Monolithic High-Q MEMS Resonator Confinement R. Hudeczek and P. Baumgartner pp.4578
6. Out-of-Equilibrium Body Potential Measurement on Silicon-on-Insulator With Deposited Metal Contacts M. Alepidis, A. Bouchard, C. Delacour, M. Bawedin, and I. Ionica pp.4582
7. Evaluation of High-Temperature High-Frequency GaN-Based LC-Oscillator Components A. Ottaviani, P. Palacios, T. Zweipfennig, M. Alomari, C. Beckmann, D. Bierbüsse, J. Wieben, J. Ehrler, H. Kalisch, R. Negra, A. Vescan, and J. N. Burghartz pp.4587
8. Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs R. Y. ElKashlan, R. Rodriguez, S. Yadav, A. Khaled, U. Peralagu, A. Alian, N. Waldron, M. Zhao, P. Wambacq, B. Parvais, and N. Collaert pp.4592
9. Characterization and TCAD Modeling of Mixed-Mode Stress Induced by Impact Ionization in Scaled SiGe HBTs N. Zagni, F. M. Puglisi, G. Verzellesi, and P. Pavan pp.4597
10. Hot-Electron Effects in AlGaN/GaN HEMTs Under Semi-ON DC Stress A. Minetto, B. Deutschmann, N. Modolo, A. Nardo, M. Meneghini, E. Zanoni, L. Sayadi, G. Prechtl, S. Sicre, and O. Häberlen pp.4602
11. Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology S. Sugatani, N. Chujo, K. Sakui, H. Ryoson, T. Nakamura, and T. Ohba pp.4606
12. Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays T. Zanotti, C. Zambelli, F. M. Puglisi, V. Milo, E. Pérez, M. K. Mahadevaiah, O. G. Ossorio, C. Wenger, P. Pavan, P. Olivo, and D. Ielmini pp.4611
13. IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge D. Saito, J. Doevenspeck, S. Cosemans, H. Oh, M. Perumkunnil, I. A. Papistas, A. Belmonte, N. Rassoul, R. Delhougne, G. Kar, P. Debacker, A. Mallik, D. Verkest, and M. H. Na pp.4616
14. Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference Y. Luo, X. Han, Z. Ye, H. Barnaby, J.-s. Seo, and S. Yu pp.4621
15. Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications M. Ezzadeen, D. Bosch, B. Giraud, S. Barraud, J.-P. Noël, D. Lattard, J. Lacord, J. M. Portal, and F. Andrieu pp.4626
16. Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology S. M. Salahuddin, E. Dentoni Litta, A. Gupta, R. Ritzenthaler, M. Schaekers, J.-L. Everaert, H. Yu, A. Vandooren, J. Ryckaert, M.-H. Na, and A. Spessot pp.4631
17. Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: The Effect of Back Bias on Drain Current and Transconductance M. Cassé, B. Cardoso Paz, G. Ghibaudo, T. Poiroux, S. Barraud, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4636
18. Enhanced Ultraviolet Avalanche Photodiode With 640-nm-Thin Silicon Body Based on SOI Technology I. Sabri Alirezaei, N. Andre, and D. Flandre pp.4641
19. TCAD Study of VLD Termination in Large-Area Power Devices Featuring a DLC Passivation L. Balestra, S. Reggiani, A. Gnudi, E. Gnani, J. Dobrzynska, and J. Vobecký pp.4645
20. Analysis of MIS-HEMT Device Edge Behavior for GaN Technology Using New Differential Method R. Kom Kammeugne, C. Leroux, J. Cluzel, L. Vauche, C. Le Royer, R. Gwoziecki, J. Biscarrat, F. Gaillard, M. Charles, E. Bano, and G. Ghibaudo pp.4649
21. Influence of Substrate Resistivity on Porous Silicon Small-Signal RF Properties G. Godet, E. Augendre, J. Lugo-Alvarez, H. Jacquinot, F. X. Gaillard, T. Lorne, E. Rolland, T. Taris, and F. Servant pp.4654
22. Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs N. Makris, M. Bucher, L. Chevas, F. Jazaeri, and J.-M. Sallese pp.4658
23. Local Variability Evaluation on Effective Channel Length Extracted With Shift-and-Ratio Method J. P. Martinez Brito and S. Bampi pp.4662
24. Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors Due to Carrier-Number and Correlated-Mobility Fluctuation A. Nikolaou, G. Darbandy, J. Leise, J. Pruefer, J. W. Borchert, M. Geiger, H. Klauk, B. Iniguez, and A. Kloes pp.4667
25. Macromodel for AC and Transient Simulations of Organic Thin-Film Transistor Circuits Including Nonquasistatic Effects J. Leise, J. Pruefer, A. Nikolaou, G. Darbandy, H. Klauk, B. Iniguez, and A. Kloes pp.4672
26. Compact Modeling and Behavioral Simulation of an Optomechanical Sensor in Verilog-A H. Elmi Dawale, L. Sibeud, S. Regord, G. Jourdan, S. Hentz, and F. Badets pp.4677
27. TCAD Simulation Framework of Gas Desorption in CNT FET NO2 Sensors S. Carapezzi, S. Reggiani, E. Gnani, and A. Gnudi pp.4682
28. Conductance in a Nanoribbon of Topologically Insulating MoS2 in the 1T Phase V. Sverdlov, A.-M. B. El-Sayed, H. Kosina, and S. Selberherr pp.4687
29. Vt Extraction Methodologies Influence Process Induced Vt Variability: Does This Fact Still Hold for Advanced Technology Nodes? M. S. Bhoir, T. Chiarella, J. Mitard, N. Horiguchi, and N. R. Mohapatra pp.4691
30. Multidomain Negative Capacitance Effect in P(VDF-TrFE) Ferroelectric Capacitor and Passive Voltage Amplification K. J. Singh, A. Bulusu, and S. Dasgupta pp.4696
31. Monte Carlo Comparison of n-Type and p-Type Nanosheets With FinFETs: Effect of the Number of Sheets F. M. Bufler, D. Jang, G. Hellings, G. Eneman, P. Matagne, A. Spessot, and M. H. Na pp.4701
32. Impact of Width Scaling and Parasitic Series Resistance on the Performance of Silicene Nanoribbon MOSFETs M. Poljak pp.4705