[paper] Organic Electrochemical Transistor Arrays

Jaehyun Kim, Robert M. Pankow, Yongjoon Cho, Isaiah D. Duplessis, Fei Qin, Dilara Meli, Rachel Daso, Ding Zheng, Wei Huang, Jonathan Rivnay, Tobin J. Marks and Antonio Facchetti

Monolithically integrated high-density vertical organic electrochemical transistor arrays
and complementary circuits.

Nat Electron 7, 234–243 (2024)

DOI: 10.1038/s41928-024-01127-x

1 Department of Chemistry and Materials Research Center, Northwestern University, Evanston, IL, USA
2 Department of Semiconductor Science, Dongguk University, Seoul, Republic of Korea
3 Department of Materials Science and Engineering, Northwestern University, Evanston, IL, USA
4 Department of Biomedical Engineering, Northwestern University, Evanston, IL, USA
5 Laboratory of Organic Electronics, Department of Science and Technology, Linköping University, Sweden
6 School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, GA, USA

Abstract Organic electrochemical transistors (OECTs) can be used to create biosensors, wearable devices and neuromorphic systems. However, restrictions in the micro- and nanopatterning of organic semiconductors, as well as topological irregularities, often limit their use in monolithically integrated circuits. Here we show that the micropatterning of organic semiconductors by electron-beam exposure can be used to create high-density (up to around 7.2 million OECTs per cm2) and mechanically flexible vertical OECT arrays and circuits. The energetic electrons convert the semiconductor exposed area to an electronic insulator while retaining ionic conductivity and topological continuity with the redox-active unexposed areas essential for monolithic integration. The resulting p- and n-type vertical OECT active-matrix arrays exhibit transconductances of 0.08–1.7 S, transient times of less than 100 μs and stable switching properties of more than 100,000 cycles. We also fabricate vertically stacked complementary logic circuits, including NOT, NAND and NOR gates.

FIG: High-density monolithically integrated vOECT arrays fabricated by e-beam exposure.

 a.) Photograph  vOECT arrays comprising bgDPP-g2T OECTs
b.) Transconductance map of the wafer-scale vOECTs; 

c.) Transfer IVs of 100 bgDPP-g2T vOECTs (W = d = 10 µm) 

Acknowledgements: This work was supported by the AFOSR (contract no. FA9550-22-1-0423), the US Office of Naval Research Contract no. N00014-20-1-2116, by the US Department of Commerce, National Institute of Standards and Technology as part of the Centre for Hierarchical Materials Design Award no. 70NANB10H005, BSF (award no. 2020384), NSF (DMR-2223922) and the Northwestern University Materials Research Science and Engineering Center Awards NSF DMR-1720139 and DMR-2308691. J.R. gratefully acknowledges support from the Alfred P. Sloan Foundation (FG-2019-12046). This work acknowledges the US Department of Energy under contract no. DE-AC02-05CH11231 at beamline 8-ID-E of the Advanced Photon Source, a US Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. This work made use of the NUFAB facility of Northwestern University’s NUANCE Center, which has received support from the SHyNE Resource (NSF ECCS-2025633), the IIN and Northwestern’s MRSEC programme (NSF DMR-1720139).

[chapter] Extraction for a 65nm FG Transistor.

[chapter] Cong, T.D., Hoang, T. (2023). A Methodology of Extraction DC Model for a 65 nm Floating-Gate Transistor. 

In: Dao, NN., Thinh, T.N., Nguyen, N.T. (eds) Intelligence of Things: Technologies and Applications. ICIT 2023. Lecture Notes on Data Engineering and Communications Technologies, vol 187. Springer, Cham. https://doi.org/10.1007/978-3-031-46573-4_19

Abstract: Floating-gate Metal-Oxide Semiconductor (MOS) has been investigated and applied in many applications such as artificial intelligence, analog mixed-signal, neural networks, and memory fields. This study aims to propose a methodology for extracting a DC model for a 65 nm floating-gate MOS transistor. The method in this work uses the combination architecture of MOS transistor, capacitance, and voltage-controlled voltage source which can archive a high accuracy result. Moreover, the advantage of the method is that the MOS transistor was a completed model which enhances the flexibility and accuracy between a fabricated device and modeled architecture. In our work, the industrial standard model Berkeley Short-channel IGFET Model (BSIM) 3v3.1, level 49 was deployed, and the DC simulation was obtained with the use of LTspice tool.

[video] Semiconductor industry in Switzerland

75th Anniversary of the Transistor

Semiconductor Industry in Switzerland

A commemorative and networking event was organized by the IEEE Solid-State Circuits Chapter of Switzerland at the EPFL Microcity building in Neuchâtel, Switzerland. In the first part of the afternoon, we had the honor to host three Distinguished Lecturers:

• Prof. Tom Lee presentation “From Rocks to Chips: Stories of the Transistor” covered the early history of the transistor.
• Dr. Chris Mangelsdorf described circuit design techniques using the bipolar junction transistor (BJT) in his talk “Don’t Try This With CMOS!”.
• Prof. Christian Enz concluded this session, describing the development of low power CMOS using the EKV MOSFET model.

This video covers the second part of the event, “From transistor manufacturing in the late 1950’s until today”. It hosted five speakers who were key actors or are still active in the semiconductor sector of Switzerland.

[paper] Bionic Neural Probe

Yu Zhou, Huiran Yang, Xueying Wang, Heng Yang, Ke Sun, Zhitao Zhou, Liuyang Sun, Jianlong Zhao, Tiger H. Tao and Xiaoling Wei

A mosquito mouthpart-like bionic neural probe

Microsystems & Nanoengineering volume 9, Article number: 88 (2023)

DOI: 10.1038/s41378-023-00565-5

Abstract: Organic electronics can be biocompatible and conformable, enhancing the ability to interface with tissue. However, the limitations of speed and integration have, thus far, necessitated reliance on silicon-based technologies for advanced processing, data transmission and device powering. Here we create a stand-alone, conformable, fully organic bioelectronic device capable of realizing these functions. This device, vertical internal ion-gated organic electrochemical transistor (vIGT), is based on a transistor architecture that incorporates a vertical channel and a miniaturized hydration access conduit to enable megahertz-signal-range operation within densely packed integrated arrays in the absence of crosstalk. These transistors demonstrated long-term stability in physiologic media, and were used to generate high-performance integrated circuits. We leveraged the high-speed and low-voltage operation of vertical internal ion-gated organic electrochemical transistors to develop alternating-current-powered conformable circuitry to acquire and wirelessly communicate signals. The resultant stand-alone device was implanted in freely moving rodents to acquire, process and transmit neurophysiologic brain signals. Such fully organic devices have the potential to expand the utility and accessibility of bioelectronics to a wide range of clinical and societal applications.

FIG: Multifunctional biomimetic neural probe system, with multichannel flexible electrode array and high sensitivity sensor array. 

[book] 75th Anniversary of the Transistor

75th Anniversary of the Transistor 

Arokia Nathan (Editor), Samar K. Saha (Editor), Ravi M. Todi (Editor)

ISBN: 978-1-394-20244-7 August 2023 Wiley-IEEE Press 464 Pages

Description: 75th Anniversary of the Transistor is a commemorative anniversary volume to celebrate the invention of the transistor. The anniversary volume was conceived by the IEEE Electron Devices Society (EDS) to provide comprehensive yet compact coverage of the historical perspectives underlying the invention of the transistor and its subsequent evolution into a multitude of integration and manufacturing technologies and applications.

The book reflects the transistor’s development since inception to the current state of the art that continues to enable scaling to very large-scale integrated circuits of higher functionality and speed. The stages in this evolution covered are in chronological order to reflect historical developments.

Narratives and experiences are provided by a select number of venerated industry and academic leaders, and retired veterans, of the semiconductor industry. 75th Anniversary of the Transistor highlights:

• Historical perspectives of the state-of-the-art pre-solid-state-transistor world (pre-1947) leading to the invention of the transistor
• Invention of the bipolar junction transistor (BJT) and analytical formulations by Shockley (1948) and their impact on the semiconductor industry
• Large scale integration, Moore’s Law (1965) and transistor scaling (1974), and MOS/LSI, including flash memories — SRAMs, DRAMs (1963), and the Toshiba NAND flash memory (1989)
• Image sensors (1986), including charge-coupled devices, and related microsensor applications

With comprehensive yet succinct and accessible coverage of one of the cornerstones of modern technology, 75th Anniversary of the Transistor is an essential reference for engineers, researchers, and undergraduate students looking for historical perspective from leaders in the field.

TABLE OF CONTENTS

Editor Biography xiii

Preface xv

1 The First Quantum Electron Device 1

Leo Esaki

2 IEEE Electron Devices Society: A Brief History 3

Samar K. Saha

3 Did Sir J.C. Bose Anticipate the Existence of p- and n-Type Semiconductors in His Coherer/Detector Experiments? 17

Prasanta Kumar Basu

4 The Point-Contact Transistor: A Revolution Begins 29

John M. Dallesasse and Robert B. Kaufman

5 On the Shockley Diode Equation and Analytic Models for Modern Bipolar Transistors 43

T. H. Ning

6 Junction-Less Field Effect Transistors: The First Transistor to be Conceptualized 51

Mamidala Jagadesh Kumar and Shubham Sahay

7 The First MOSFET Design by J. Lilienfeld and a Long Journey to Its Implementation 65

Hiroshi Iwai

8 The Invention of the Self-Aligned Silicon Gate Process 89

Robert E. Kerwin

9 The Application of Ion Implantation to Device Fabrication: The Early Days 95

Alfred U. MacRae

10 Evolution of the MOSFET: From Microns to Nanometers 101

Yuan Taur

11 The SOI Transistor 115

Sorin Cristoloveanu

12 FinFET: The 3D Thin-Body Transistor 135

Chenming Hu

13 Historical Perspective of the Development of the FinFET and Process Architecture 145

Digh Hisamoto

14 The Origin of the Tunnel FET 155

Gehan A. J. Amaratunga

15 Floating-Gate Memory: A Prime Technology Driver of the Digital Age 163

S. M. Sze

16 Development of ETOX NOR Flash Memory 179

Stefan K. Lai

17 History of MOS Memory Evolution on DRAM and SRAM 187

Mitsumasa Koyanagi

18 Silicon-Germanium Heterojunction Bipolar Transistors: A Retrospective 215

Subramanian S. Iyer and John D. Cressler

18.9 Some Parting Words (SSI) 235

19 The 25-Year Disruptive Path of InP/GaAsSb Double Heterojunction Bipolar Transistors 239

Colombo R. Bolognesi

20 The High Electron Mobility Transistor: 40 Years of Excitement and Surprises 253

Jesús A. del Alamo

21 The Thin Film Transistor and Emergence of Large Area, Flexible Electronics and Beyond 263

Yue Kuo, Jin Jang, and Arokia Nathan

22 Imaging Inventions: Charge-Coupled Devices 273

Michael F. Tompsett

23 The Invention and Development of CMOS Image Sensors: A Camera in Every Pocket 281

Eric R. Fossum

25 Creation of the Insulated Gate Bipolar Transistor 299

B. Jayant Baliga

26 The History of Noise in Metal-Oxide-Semiconductor Field-Effect Transistors 309

Renuka P. Jindal

27 A Miraculously Reliable Transistor: A Short History 323

Muhammad Ashraful Alam and Ahmed Ehteshamul Islam

28 Technology Computer-Aided Design: A Key Component of Microelectronics' Development 337

Siegfried Selberherr and Viktor Sverdlov

29 Early Integrated Circuits 349

Willy Sansen

30 A Path to the One-Chip Mixed-Signal SoC for Digital Video Systems 355

Akira Matsuzawa

31 Historical Perspective of the Nonvolatile Memory and Emerging Computing Paradigms 369

Ming Liu

32 CMOS Enabling Quantum Computing 379

Edoardo Charbon

33 Materials and Interfaces: How They Contributed to Transistor Development 387

Bruce Gnade

34 The Magic of MOSFET Manufacturing 393

Kelin J. Kuhn

35 Materials Innovation: Key to Past and Future Transistor Scaling 403

Tsu-Jae King Liu and Lars P. Tatum

36 Germanium: Back to the Future 415

Krishna C. Saraswat

References 428

Index 431

[Commemorative] History of Junction Technologies

Hiroshi Iwai

History of Junction Technologies

Commemorative talk for the 75th anniversary of the transistor

IWJT 2023; T-Cosponsored by IEEE EDS; 

Kyoto (J) June 8-9, 2023

1 International College of Semiconductor Technology, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2 Tokyo Institute of Technology, Japan

Abstract: In this paper, I describe the history of junction technologies for ICT (Information and Communication Technology) devices. Junctions serve as functional interfaces between materials in these devices. Over the past 200 years, since the inception of electrical engineering, a wide range of junction technologies have been developed as key components for device operation, playing a significant role in advancing intelligence in human society.

FIG: The first idea of FET (MISFET) by J. Lilienfeld "Method and apparatus for controlling electric current", Canadian Patent CA272437TA, filed October 22, 1925

Acknowledgements: I [author: Hiroshi Iwai] would like to express my sincere appreciation to the Tokyo Institute of Technology Library for granting me access to historically significant documents. The information available on the Computer History Museum (CHM) website was instrumental in understanding the timeline of device development. I am deeply grateful to Prof. Kazuo Tsutsui of Tokyo Institute of Technology for providing me with a conducive environment to concentrate on writing this manuscript. I would also like to extend my gratitude to the IWJT committee members for granting me the valuable opportunity to document the history of junction technologies, logic and memory device technologies, as well as reviewing the lengthy manuscript. In particular, I am grateful to Dr. Michael Current for his meticulous review of the manuscript. Finally, I would like to thank my colleagues in both industry and academia who have dedicated their time and expertise to the advancement of integrated circuit technology over the years.

[EDS MQ/DL] The Transistor Turns 75

The Transistor Turns 75

A Forward Look to Challenges and Opportunities

A series of IEEE EDS Distinguished Lecturer talks on topics in current transistor and electron device research, reflecting on the challenges ahead and the rewards inherrent in overcomming them.

DATE AND TIME	LOCATION	HOSTS	REGISTRATION
Date: 02 Jun 2023 Time: 08:30 AM to 05:30 PM All times are (UTC+00:00) Edinburgh	Moller Institute Cambridge, England UK CB3 ODE Click here for Map	UK and Ireland Section Chapter, ED15 Contact Host	Starts 19 April 2023 06:00 AM Ends 30 May 2023 06:30 PM All times are (UTC+00:00) Edinburgh No Admission Charge Register Now

EDS DL SPEAKERS

• Benjamin Iniguez: Modeling 2D Semiconductor Devices
• Lluis Marsal: Organic Photovoltaics: Opportunities and Challenges
• Arokia Nathan: 
• Fernando Guarin: 75th Anniversary of the Transistor Semiconductor Industry Perspective
• Edmundo A. Gutierrez-D.: DC and RF reliability of advanced bulk and SOI CMOS technologies
• Merlyne De Souza: Challenges to Edge computing: an era beyond silicon CMOS
• Samar Saha: 
• MK Radhakrishnan: Birth and Evolution of Transistor and Its Impact on Humanity
• Xiaojun Guo: Transistor Technologies for Hybrid Integration at Micro- and Macro-scales
• Hiroshi Iwai: Present status and future of the nanoelectronics technology

Commemorative and Networking Event: 75th anniversary of the transistor

IEEE Switzerland Solid State Circuits Chapter

invites you to join the networking event to celebrate

the 75th anniversary of the transistor

Three IEEE Distinguished Lecturers will talk about the transistor history and its properties. It will be followed by short presentations about semiconductor industry activities in Switzerland, with the following networking apéro.

Attendance is free and open to all: mention it and forward to your friends and colleagues.

Please register for logistics reasons. 

Date and Time	Location
Date: 30 Mar 2023 Time: 01:00 PM to 07:30 PM All times are (UTC+01:00) Bern Add Event to Calendar iCal Google Calendar	EPFL Microcity Rue de la Maladière 71C CH-2020 Neuchâtel Room Number: MC A1 272 Click here for Map

Agenda

13:00 – 13:30 Welcome Coffee 

13:30 – 14:15 Tom Lee: From Rocks to Chips: Stories of the Transistor

14:15 – 15:15 Chris Mangelsdorf: Don't try this with CMOS

15:15 – 15:45 Coffee break 

15:45 – 16:30 Christian Enz: The Design of Low-power Analog CMOS Circuits Using the Inversion Coefficient

16:30 – 17:30 Semiconductor industry in Switzerland, sharing experiences 
                        (W.Grabinski, Panel Moderator):

• Bipolar transistor manufacturing in Switzerland – Hugo Wyss
• Integrated Circuits – Eric Vittoz
• Semiconductor design in the 21st century – Alain-Serge Poret
• Micro-electronics for Swiss made products – Evert Dijkstra
• Semiconductor manufacturing equipment – André Gerde

17:30 – 19:00 Apéro riche

Hosts

Switzerland Section Chapter, SSC37 : https://sscs.ieee.ch
Switzerland Section : https://ieee.ch/

[paper] 50 Two-Transistor MOSFET Circuits

Harald Pretl* and Matthias Eberlein**

Fifty Nifty Variations of Two-Transistor Circuits: A tribute to the versatility of MOSFETs

IEEE Solid-State Circuits Magazine 13(3):38-46, August 2021

DOI: 10.1109/MSSC.2021.3088968  

  

* Institute for Integrated Circuits, JKU, Linz, Austria
** Semiconductor electronics, TU, Darmstadt, Germany

Abstract: We present a compendium of two-MOS-transistor circuits, spanning the range from simple standard configurations to ingenious arrangements. Using these building blocks, circuit designers can assemble a vast array of complex analog functions. This (incomplete) collection shall serve as a reference and inspiration to junior circuit designers and hopefully contains at least one unexpected example for the professional engineer.

Part 1/2 #thisismagic #circuit #mosfet

Part 2/2 #thisismagic #circuit #mosfet

Acknowledgments: We thank the reviewers for their many mindful suggestions. We want to thank our colleagues at the Institute for Integrated Circuits, Johannes Kepler University Linz, for their support in preparing this manuscript and for their many enlightening discussions.

[paper] Analytical Compact Model Of Cylindrical Junctionless Nanowire FETs

Adelcio M. de Souza, Daniel R. Celino, Regiane Ragi, Murilo A. Romero

Fully analytical compact model for the Q–V and C–V characteristics 

of cylindrical junctionless nanowire FETs

Microelectronics Journal (2021): 105324

DOI: 10.1016/j.mejo.2021.105324

   

University of Sao Paulo (EESC/USP), Sao Carlos (BR)

Abstract: This paper develops a new compact model for the Q–V and C–V characteristics of cylindrical junctionless nanowire FETs in which the nanowire radius is large enough, in such a way that quantum confinement effects can be neglected. Our model is fully analytical and valid for all bias regimes, i.e., subthreshold, partial depletion, and accumulation. The obtained Q-V and C–V characteristics, as well as their derivatives, are continuous across the full range of bias voltages. The model is fully physics-based, with no fitting parameters, and it is very intuitive, since it relies on the understanding of the device as a gated resistor. Model validation is performed against previous results in the literature, demonstrating very good agreement.

Fig.  Validation of our C–V model (solid lines) in comparison to numerical results, highlighting the effect of parasitic capacitance. The free-carrier capacitance component from new model is shown in dashed lines. Simulation parameters: tox = 4.5nm, Nd = 1.6E18 cm−3, L = 200nm, VFB = 1.09V and Vds = 0.05V.

Acknowledgments: The authors would like to thank the Brazilian funding agencies CAPES, CNPq, and Fapesp for their financial support: Conselho Nacional de Desenvolvimento Científico e Tecnologico. Grant Number: 303708/2017-4; Coordenaçao de Aperfeiçoamento de Pessoal de Nível Superior; Fundaçao de Amparo a Pesquisa do Estado de Sao Paulo. Grant Number: 18/13537-6.

[papers] Aging and Device Reliability Compact Modeling

IEEE International Reliability Physics Symposium

(IRPS 2021)

[1] N. Chatterjee, J. Ortega, I. Meric, P. Xiao and I. Tsameret, "Machine Learning On Transistor Aging Data: Test Time Reduction and Modeling for Novel Devices," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-9, doi: 10.1109/IRPS46558.2021.9405188.

Abstract: Accurately modeling the I-V characteristics and current degradation for transistors is central to predicting circuit end-of-life behavior. In this work, we propose a machine learning model to accurately model current degradation at various stress conditions and extend that to make nominal use-bias predictions. The model can be extended to track and predict any parametric change. We show an excellent agreement of the model with experimental results. Furthermore, we use a deep neural network to model the I-V characteristics of aged transistors over a wide drain and gate playback bias range and show an excellent agreement with experimental results. We show that the model is reliably able to interpolate and extrapolate demonstrating that it learns the underlying functional form of the data.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405188&isnumber=9405088

[2] P. B. Vyas et al., "Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-4, doi: 10.1109/IRPS46558.2021.9405197.

Abstract: Accurate prediction of device aging plays a vital role in the circuit design of advanced-node CMOS technologies. In particular, hot-carrier induced aging is so complicated that its modeling is often significantly simplified, with focus limited to digital circuits. We present here a novel reliability-aware compact modeling method that can accurately capture the full post-stress I-V characteristics of the MOSFET, taking into account the impact of drain depletion region on induced defects.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405197&isnumber=9405088

[3] Z. Wu et al., "Physics-based device aging modelling framework for accurate circuit reliability assessment," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-6, doi: 10.1109/IRPS46558.2021.9405106.

Abstract: An analytical device aging modelling framework, ranging from microscopic degradation physics up to the aged I-V characteristics, is demonstrated. We first expand our reliability oriented I-V compact model, now including temperature and body-bias effects; second, we propose an analytical solution for channel carrier profiling which-compared to our previous work-circumvents the need of TCAD aid; third, through Poisson's equation, we convert the extracted carrier density profile into channel lateral and oxide electric fields; fourth, we represent the device as an equivalent ballistic MOSFETs chain to enable channel “slicing” and propagate local degradation into the aged I-V characteristics, without requiring computationally-intensive self-consistent calculations. The local degradation in each channel “slice” is calculated with physics-based reliability models (2-state NMP, SVE/MVE). The demonstrated aging modelling framework is verified against TCAD and validated across a broad range of VG/VD/T stress conditions in a scaled finFET technology.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405106&isnumber=9405088

Virtual Si Museum /2107/ TG4 and TG50

The TG1-TG5 series transistor are the first industrially mass-produced BJT transistors in Poland. The serial production was started by the TEWA Semiconductor Factory, Warsaw, in early1960s. Then, the TG50-TG55 series, was also manufactured by the TEWA in 1961–1962. 

The TG4 (see Pic: below) is low power, low frequency, pnp germanium (Ge) alloy transistor (with 75 mW max collector power) [1].

The TG50 (below) is medium power, low frequency,  pnp germanium (Ge) alloy transistor (with 175 mW max collector power) [2].

An initial stage of Polish semiconductor microelectronics research activities has been reviewed by Prof. Jerzy Pułtorak. In his paper [3], he has reviewed activities of leading Polish R&D groups starting from Department of Electronics, Polish Academy of Sciences (PAN) founded on July 4, 1952 till foundation of the Instytut Technologii Elektronowej (ITE, Warsaw) early 1960 (now Sieć Badawcza Łukasiewicz - Instytut Mikroelektroniki i Fotoniki).  The first, in Poland, experimental germanium point-contact transistor TP-1 [4] has been developed by Prof. Rosinski just after John Bardeen, Walter Brattain and William Shockley have invented a semi-conductor triode (transistor) [5] on December 23, 1947.

Pic: TG4 and two TG50 by the TEWA Semiconductor Factory, Warsaw (PL)

References: 

[1] TG1-5 / PL Wikipedia/ https://pl.wikipedia.org/wiki/TG1-5

[2] TG50-5  / PL Wikipedia/ https://pl.wikipedia.org/wiki/TG50-55

[3] J. Pułtorak, "60 years of polish transistors," 2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Lublin, Poland, 2014, pp. 15-21, doi: 10.1109/MIXDES.2014.6872144.

[4] W.Rosinski, J.Groszkowski, “Doswiadczalne tranzystory punktowe model TP” (“Experimental point-cotact transistors model TP”), Arch. Elektrot. 4, 1955, p. 381

[5] J.Bardeen, H.W.Brattain, “The transistor, a semi-conductor triode”, Phys.Rev.74, 7, 1954, p.230

[paper] Analysis of 2D Transistors

Guoli Li, Zizheng Fan, Nicolas André, Member, IEEE, Yongye Xu, Ying Xia, Benjamín Iñíguez, Fellow, IEEE, Lei Liao, Senior Member, IEEE, and Denis Flandre, Senior Member, IEEE

Non-Linear Output-Conductance Function for Robust Analysis of Two-Dimensional Transistors

IEEE Electron Device Letters, 42(1), pp.94-97

DOI: 10.1109/LED.2020.3042212

Abstract: In this work, we explore the outputconductance function (G-function) to interpret the device characteristics of two-dimensional (2D) semiconductor transistors. Based on analysis of the device output conductance, the carrier mobility, and the channel as well as contact resistance are extracted. Thereafter the currentvoltage (IV) characteristics of black phosphorous (BP) and MoS2 transistors from room to low temperature are modeled and compared to experiments. The G-function model proves its reliability and accuracy in parameter extraction and IV modeling of 2D transistors, regardless of the n- or p- type, the short- or long-channel and the Schottky or Ohmic contact. Moreover, this works shows its high potential in the device modeling and further circuit design of the 2D transistors, requiring only few parameters and simulating precise IV characteristics.

G-Function Model (for Linear and Non-Linear Cases), the Rch and Rc can be calculated for both the Ohmic and Schottky contacts in the 2D transistors: 

Aknowlegement: This work was supported in part by the National Key Research and Development Program of China under Grant 2018YFA0703700; in part by the National Natural Science Foundation of China under Grant 61925403, Grant 61851403, and Grant 62004065; in part by the Hunan Natural Science Foundation under Grant 2020JJ5087; and in part by the Technology Program (Major Project) of Changsha under Grant kq1902042.

Price per transistor on a chip

The price per transistor on a chip has dropped dramatically since Intel was founded in 1968. Some people estimate that the price of a transistor is now about the same as that of one printed newspaper character.

Intel has shipped over 200 million CPUs using high-k/metal-gate transistors – the kind used in 32nm processors -- since the technology was first put into production in November 2007. This translates to over 50,000,000,000,000,000 (50 quadrillion) transistors, or the equivalent of over 7 million transistors for every man, woman and child on earth. [more]

Ballot of May 28, 1948

more at flickr by johngineer