[paper] Editorial Special Section on ESSDERC

IEEE TED, Vol. 67, No. 11, November 2020

Mid-September 2020, we were supposed to celebrate in Grenoble the 50th anniversary of the European SolidState Device Research Conference and European Solid-State Circuits Conference (ESSDERC-ESSCIRC), which is the most important European conference dedicated to solid-state devices and circuits. However, in April 2020, more than one-third of the global population was under severe lock-down as a result of the protective public health measures imposed by the different governments, states, or provinces. Because of the COVID-19 pandemic, the ESSDERC-ESSCIRC organizing and steering committees, together with the sponsoring SSCS and EDS IEEE societies, decided to reschedule the in-person conference to September 6–9, 2021, in Grenoble, to add new virtual “Educational Events” held on September 14 and 15, 2020 (presentations available till October 16, 2020, at https://www.esscirc-essderc2020.org/) as well as to invite the ESSDERC-ESSCIRC research community to submit publications to the IEEE TRANSACTIONS ON ELECTRON DEVICES (TED) and to the IEEE SOLID-STATE CIRCUITS LETTERS (SSC-L), respectively, in a brief format. All of these initiatives met great success. Especially, more than 47 TED submissions were received and reviewed, and 32 papers were accepted and have been included in this dedicated section of the November TED issue.

We would like to thank all the authors for taking this opportunity to keep the ESSDERC-ESSCIRC momentum, all the IEEE reviewers for their reactivity, and all the ESSDERC-ESSCIRC sponsors for their trust in this difficult time. Let us think with a positive mind, and acknowledge that this experience opens a new and fruitful collaboration between ESSDERC and TED.

We hope you will enjoy reading these high-quality papers. Stay safe

FRANCOIS ANDRIEU, TPC Chair
CEA-Leti
Université Grenoble Alpes
38054 Grenoble, France

GIOVANNI GHIONE, Editor-in-Chief
Dipartimento di Elettronica e Telecomunicazioni
Politecnico di Torino
10129 Torino, Italy

Editorial Special Section on ESSDERC

 IEEE TED, Vol. 67, No. 11, November 2020

1. Generalized Constant Current Method for Determining MOSFET Threshold Voltage M. Bucher, N. Makris, and L. Chevas pp.4559
2. Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications (Invited Paper) B. Cardoso Paz, M. Cassé, C. Theodorou, G. Ghibaudo, T. Kammler, L. Pirro, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4563
3. A Method for Series-Resistance-Immune Extraction of Low-Frequency Noise Parameters in Nanoscale MOSFETs A. Tataridou, G. Ghibaudo, and C. Theodorou pp.4568
4. Analytical Model for Interface Traps-Dependent Back Bias Capability and Variability in Ultrathin Body and Box FDSOI MOSFETs W. Chen, L. Cai, X. Liu, and G. Du pp.4573
5. Polarization Independent Band Gaps in CMOS Back-End-of-Line for Monolithic High-Q MEMS Resonator Confinement R. Hudeczek and P. Baumgartner pp.4578
6. Out-of-Equilibrium Body Potential Measurement on Silicon-on-Insulator With Deposited Metal Contacts M. Alepidis, A. Bouchard, C. Delacour, M. Bawedin, and I. Ionica pp.4582
7. Evaluation of High-Temperature High-Frequency GaN-Based LC-Oscillator Components A. Ottaviani, P. Palacios, T. Zweipfennig, M. Alomari, C. Beckmann, D. Bierbüsse, J. Wieben, J. Ehrler, H. Kalisch, R. Negra, A. Vescan, and J. N. Burghartz pp.4587
8. Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs R. Y. ElKashlan, R. Rodriguez, S. Yadav, A. Khaled, U. Peralagu, A. Alian, N. Waldron, M. Zhao, P. Wambacq, B. Parvais, and N. Collaert pp.4592
9. Characterization and TCAD Modeling of Mixed-Mode Stress Induced by Impact Ionization in Scaled SiGe HBTs N. Zagni, F. M. Puglisi, G. Verzellesi, and P. Pavan pp.4597
10. Hot-Electron Effects in AlGaN/GaN HEMTs Under Semi-ON DC Stress A. Minetto, B. Deutschmann, N. Modolo, A. Nardo, M. Meneghini, E. Zanoni, L. Sayadi, G. Prechtl, S. Sicre, and O. Häberlen pp.4602
11. Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology S. Sugatani, N. Chujo, K. Sakui, H. Ryoson, T. Nakamura, and T. Ohba pp.4606
12. Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays T. Zanotti, C. Zambelli, F. M. Puglisi, V. Milo, E. Pérez, M. K. Mahadevaiah, O. G. Ossorio, C. Wenger, P. Pavan, P. Olivo, and D. Ielmini pp.4611
13. IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge D. Saito, J. Doevenspeck, S. Cosemans, H. Oh, M. Perumkunnil, I. A. Papistas, A. Belmonte, N. Rassoul, R. Delhougne, G. Kar, P. Debacker, A. Mallik, D. Verkest, and M. H. Na pp.4616
14. Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference Y. Luo, X. Han, Z. Ye, H. Barnaby, J.-s. Seo, and S. Yu pp.4621
15. Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications M. Ezzadeen, D. Bosch, B. Giraud, S. Barraud, J.-P. Noël, D. Lattard, J. Lacord, J. M. Portal, and F. Andrieu pp.4626
16. Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology S. M. Salahuddin, E. Dentoni Litta, A. Gupta, R. Ritzenthaler, M. Schaekers, J.-L. Everaert, H. Yu, A. Vandooren, J. Ryckaert, M.-H. Na, and A. Spessot pp.4631
17. Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: The Effect of Back Bias on Drain Current and Transconductance M. Cassé, B. Cardoso Paz, G. Ghibaudo, T. Poiroux, S. Barraud, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4636
18. Enhanced Ultraviolet Avalanche Photodiode With 640-nm-Thin Silicon Body Based on SOI Technology I. Sabri Alirezaei, N. Andre, and D. Flandre pp.4641
19. TCAD Study of VLD Termination in Large-Area Power Devices Featuring a DLC Passivation L. Balestra, S. Reggiani, A. Gnudi, E. Gnani, J. Dobrzynska, and J. Vobecký pp.4645
20. Analysis of MIS-HEMT Device Edge Behavior for GaN Technology Using New Differential Method R. Kom Kammeugne, C. Leroux, J. Cluzel, L. Vauche, C. Le Royer, R. Gwoziecki, J. Biscarrat, F. Gaillard, M. Charles, E. Bano, and G. Ghibaudo pp.4649
21. Influence of Substrate Resistivity on Porous Silicon Small-Signal RF Properties G. Godet, E. Augendre, J. Lugo-Alvarez, H. Jacquinot, F. X. Gaillard, T. Lorne, E. Rolland, T. Taris, and F. Servant pp.4654
22. Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs N. Makris, M. Bucher, L. Chevas, F. Jazaeri, and J.-M. Sallese pp.4658
23. Local Variability Evaluation on Effective Channel Length Extracted With Shift-and-Ratio Method J. P. Martinez Brito and S. Bampi pp.4662
24. Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors Due to Carrier-Number and Correlated-Mobility Fluctuation A. Nikolaou, G. Darbandy, J. Leise, J. Pruefer, J. W. Borchert, M. Geiger, H. Klauk, B. Iniguez, and A. Kloes pp.4667
25. Macromodel for AC and Transient Simulations of Organic Thin-Film Transistor Circuits Including Nonquasistatic Effects J. Leise, J. Pruefer, A. Nikolaou, G. Darbandy, H. Klauk, B. Iniguez, and A. Kloes pp.4672
26. Compact Modeling and Behavioral Simulation of an Optomechanical Sensor in Verilog-A H. Elmi Dawale, L. Sibeud, S. Regord, G. Jourdan, S. Hentz, and F. Badets pp.4677
27. TCAD Simulation Framework of Gas Desorption in CNT FET NO2 Sensors S. Carapezzi, S. Reggiani, E. Gnani, and A. Gnudi pp.4682
28. Conductance in a Nanoribbon of Topologically Insulating MoS2 in the 1T Phase V. Sverdlov, A.-M. B. El-Sayed, H. Kosina, and S. Selberherr pp.4687
29. Vt Extraction Methodologies Influence Process Induced Vt Variability: Does This Fact Still Hold for Advanced Technology Nodes? M. S. Bhoir, T. Chiarella, J. Mitard, N. Horiguchi, and N. R. Mohapatra pp.4691
30. Multidomain Negative Capacitance Effect in P(VDF-TrFE) Ferroelectric Capacitor and Passive Voltage Amplification K. J. Singh, A. Bulusu, and S. Dasgupta pp.4696
31. Monte Carlo Comparison of n-Type and p-Type Nanosheets With FinFETs: Effect of the Number of Sheets F. M. Bufler, D. Jang, G. Hellings, G. Eneman, P. Matagne, A. Spessot, and M. H. Na pp.4701
32. Impact of Width Scaling and Parasitic Series Resistance on the Performance of Silicene Nanoribbon MOSFETs M. Poljak pp.4705

C4P: Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices

Call for Papers for a Special Issue 

of IEEE Transactions on Electron Devices

on “Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices”

Submission deadline: March 31, 2019; Publication date: October 2019

Reliability of electronic devices continues to remain as a serious issue for several technology generations. Bias Temperature Instability (BTI) continues to impact CMOS logic devices for High-K Metal Gate (HKMG) technologies, while Hot Carrier Degradation (HCD) and Self Heating Effect (SHE) have evolved as additional issues for FinFETs. The Time Dependent Dielectric Breakdown (TDDB) is still a concern and needs attention. These topics are also of interest for future devices with different channel materials (such as SiGe, Ge or III-V) and architectures (such as Gate All Around Nano Sheet FETs). The mechanisms governing degradation of program/erase window with cycling, data retention before and after cycling, etc. in conventional Vertical NAND and different emerging memories such as Resistive RAM, Phase Change RAM, Magnetic RAM and Ferroelectric RAM are of interest. Different power devices (Si and SiC FETs, IGBTs, GaN HEMTs) are becoming mainstream now and their reliability needs to be accessed. Finally, very little has been studied on the reliability of futuristic 2D channel devices.

This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the an in the field of device reliability based on both experimental results and theoretical models. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices.

Topics of interest include, but are not limited to:

• Advanced Transistors: Negative and Positive Bias Temperature Instabilities; Hot Carrier Degradation; SelfHeating Effects; De-convolution of BTI-HCI-SHE; Variability; Random Telegraph Noise; Alternative (SiGe, Ge and III-V) channels; Novel device architectures; etc.;
• Gate Dielectrics: Charge trapping and breakdown including TDDB; Reliability of novel gate dielectrics and materials for logic and memory devices; Evaluation and modeling of progressive breakdown; Gate dielectric reliability on SiGe, Ge and III-V channels; etc.;
• Reliability of Memory Devices: DRAM and NVM including 2D and 3D NAND; Novel memory devices such as Re-RAM, Phase Change RAM, MRAM; etc.;
• Power Devices: MOSFET, HEMT, IGBT on different materials (GaN, SiC, Ga203); etc.;
• RF Devices: High frequency effects; GaN HEMT; RF 801 etc.
• Novel Devices: Negative Capacitance FETs; Ferroelectric memory FETs; Tunnel FETs; Transistors with 2D semiconductors (graphene, M082); Spintronic devices; Neuromorphic devices, etc.;
• Process-Related Reliability: Reliability issues related to different fabrication processes and layout for the above devices.
• Device-Circuit Correlation: Impact of device reliability on circuit operation including any correlation between different effects; development of compact models; circuit simulation; etc.

Submission instructions: Manuscripts should be submitted in a double column format using an IEEE style file. Please visit the following link to download the templates:
http://www.ieee.org/publications_standards/pub1ications/authors/author_templates.html

In your cover letter, please indicate that your submission is for this special issue.

Submission deadline: March 31, 2019 Publication date: October 2019

Guest Editors:

1. Dr. Andreas Kerber, Globalfoundries, USA
2. Dr. Chandra Mouli, Micron Technology Inc., USA
3. Prof. Durga Misra, New Jersey Institute of Technology, USA
4. Prof. Gaudenzio Meneghesso, University of Padova, USA
5. Dr. James Stathis, IBM, USA
6. Prof. Ninoslav D. Stojadinovié, University of Nis, RS
7. Dr. Randy Koval, Intel, SG
8. Prof. Souvik Mahapatra, Indian Institute of Technology, Bombay, IN (Guest EIC)
9. Dr. Stephen Ramey, Intel, USA
10. Prof Tibor Grasser, TU, Wien, A

[Special Issue] TED on “Compact Modeling for Circuit Design"

Call for papers for 

a Special Issue of IEEE TED

on

Compact Modeling for Circuit Design

Submission deadline: April 30, 2018               Publication date: January 2019

In order to capture the full potential of semiconductor devices, compact device models and design software are critically needed. Predictive and physical device and circuit design software are required to accelerate development cycles and tackle issues of device efficiency, manufacturing yield and product stability. The performance/accuracy of the design software is dependent on the availability of accurate device models, and for circuit design, compact models.

In particular, compact device models are the vehicle that allows the design of circuits using the targeted devices. The compact model should not only accurately capture the physics of the device in all operation regimes, but at the same time should also have an analytical or semi-analytical formulation to be used in automated design tools for the simulation of circuits containing several or many devices. On the other hand, compact models can also be used as a tool to make clear estimations and predictions of the performances of future devices following technological trends. The lack of adequate compact models for a number of emerging devices is mostly due to the insufficient understanding of the physical mechanisms that govern their behaviours. Regarding many emerging non-silicon structures, devices, circuit and system designers very often rely on empirical behavioural macro-models and/or use existing silicon device compact models based on the conventional understanding of transport processes. However, for these emerging non-silicon devices, neither approach provides a fully adequate device description under all operation conditions, nor the quantitative predictive quality required for the accurate production quality design.

Therefore, the main objective of this dedicated special issue is to engage Electron Devices Community in a serious discussion with their scholarly contributions specifically focused on solving major challenges in the broad area of compact device modeling for circuit design.

Suggested topics include but not limited to:

1. Silicon MOSFET modeling: Advanced Bulk MOSFETs; SOl MOSFETs; Multi-Gate MOSFETs: Double-Gate MOSFETs, Surrounding-Gate MOSFETs, FinFETs, UTB SOI MOSFETs; Junctionless MuGFETs; Power and High Voltage MOSFETs.
2. Junction-based and compound semiconductor FET modeling: Advanced MESFETs; Advanced HEMTs; lIl-V and Ill-N; MOSFETs; Advanced IFETs.
3. Diode and bipolar transistor modeling: Advanced BJTs; HBTs; IGBTs; pn and pin diodes; Varactors.
4. Emerging transistor modeling: Tunnel FETs; Molecular transistors; Single Electron Transistors; Quantum Dot Transistors; Negative Capacitance Transistors.
5. Emerging semiconductor devices: Memories, MRAM, PCRAM etc.; Spintronic devices; Layered/2D materials
6. Thin-Film FETS (TFT): a-Si:H TFTs; Polycrystalline Si TFTs; OTFTs and OECTs; Oxide TFTs; Single-crystal TFTs.
7. Modeling of physical effects: Noise; High frequency operation; Mismatch; Strain; High energy particle interactions in ICs (Cosmic rays and energy beams); ESD events; Ballistic and quasi-ballistic transport; Layout dependent effects.
8. Photonic devices: LEDs and OLEDs; Photodiodes; Solar cells; Photodetectors; SPADs.
9. Model implementation in EDA tools and applications: Model code adaptation to EDA tools; Computational model performances in design tools; Challenges of model implementation in design tools; Compact model applications to variation and statistical analysis; Compact model applications to thermal analysis; Compact model applications to design exploration; Compact model applications to design optimization; Compact model applications to device process improvements; Compact modeling for BSD prediction; Circuit design using new compact models.

Submission instructions: Manuscripts should he submitted in a double column format using an IEEE style file Please visit the following link to download the templates:

http://www,ieeeiorg/publicationsistandards/publications/authors/author7templates,html

In your cover letter, please indicate that your submission is for this special issue. Please submit papers using the website: http://mc.manuscriDtcentral.com/ted

Guest Editors:

1. Benjamin Iniguez, URV, Tarragona (SP)
2. Yogesh Chauan, IIT Kanpur (IN) 
3. Andries Scholten, NXP Semiconductors, Eindhoven (NL)
4. Ananda Roy, Intel Corporation, Portland, OR (USA)
5. Slobodan Mijalkovic, Silvaco Europe Ltd, St. Ives (UK)
6. Sadayuki Yoshitomi, Toshiba Corporation, Tokyo (J)
7. Kejun Xia, NXP Semiconductors, Phoenix, AZ (USA) 
8. Wladek Grabinski, GMC Consulting, Commugny (CH) 
9. Kaikai Xu, UEST of China, Chengdu (CN) 

IEEE TED Call for Papers: Variation aware technology and circuit codesign

 Call for papers for a special issue of 

 IEEE Transactions on Electron Devices 

"Variation aware technology and circuit codesign" 

The special issue on "variation aware technology and circuit co design is devoted to the research and development activities on variation aware process device technology and co-optimization with circuit design. Rapid pace of new technology introduction to CMOS technology requires much more sophisticate optimization of process, device, and circuit design, in order to maximize return on investment. Careful optimization of process technology, device structure, layout and circuit design in holistic manner enables significant performance improvement while reducing overall power consumption with least amount of area penalty.

Among many challenges for this holistic optimization, higher process and device variation becomes one of most critical issues as process technology is marching into below 20nm node.

New material technology and non-planar device structure add additional variation source on top of conventional geometrical effect. Not only reducing extrinsic portion of variation is important understanding the effect of such variation in various actual circuit design is also very important In addition to addressing variation at individual process and design element, this special edition also touches on the impact of variation aware optimization to overall SOC design that requires both high performance and low power functional blocks.

This special edition includes, but not limited to, following topics:

• Variation reduction methods of advanced process technology, including patterning, deposition and etch processes
• Variation reduction methods of dvanced device technology, including FinFET, Nanowire, FDSOL etc.
• Co-optimization of technology and circuit to minimize variation and/orimpact of variation.
• ТCAD to understand the source of variation and provide practical method to improve.
• Novel process and device technology to cope with variation issue in coming nodes.
• SOC integration and design methodology to take process device variation into account.

Please submit papers by using the website: https://mc.manuscriptcentral.com/ted link here

BE SURE TO MENTION THE SPECIAL ISSUE WITHIN THE COVER LETTER

Submission Deadline: October 31, 2014
Scheduled Publication Date: June 2015

Guest Editors:
Stanley S.C. Song Qualcomm
Huiling Shang, IBM
Каustav Banerjee, University of California, Santa Barbara
Shuji Ikeda, TEI solution

If you have any questions about submitting a manuscript, please contact:
Jo Ann Marsh (j.marsh@ieee.org) T-ED Special Issues Administrative Support