[C4P] EDTM 2025 in Hong Kong, China

The 9th IEEE Electron Devices Technology and Manufacturing Hong Kong, China, March 9th – 12th, 2025 Theme: Shaping the Future with Innovations in Devices and Manufacturing Call for Papers Three-page camera-ready paper submission starts: August 15, 2024 Paper submission deadline: October 15 October 31, 2025 Notification for Acceptance: December 15, 2024 https://edtm2025.com/ Technical Areas EDTM 2025 solicits papers in all areas of electronic devices, including materials, processes, modeling, device/circuit/system design, reliability, packaging, manufacturing, testing, and yield. EDTM 2025 will include parallel technical sessions of oral and poster presentations. Publication Opportunities The accepted and presented papers will be published in the EDTM 2025 Proceedings, included in IEEE Xplore. The authors of a selected number of high-impact papers will be invited to submit extended versions for publication in the special issue of IEEE Journal of Electron Devices Society (J-EDS) or IEEE Transactions on Electron Devices, subjected to J-EDS and TED policy. Short Courses and Tutorials EDTM 2025 will start with a set of short courses and tutorials on March 9, 2025. Tutorials will cover selected topics from the basics to the state-of-the-art. The Short Courses will discuss the latest research and challenges on emerging and advanced topics. Exhibition EDTM 2025 offers vendors to showcase their newest products and technologies, allowing attendees to learn about new tools and techniques. Award Opportunities EDTM 2025 offers one Best Paper Award in each sub-technical area.

General Chair： Yang Chai (HK PolyU) General Co-Chair： Tim Cheng (HKUST) TPC Chair： Mansun Chan (HKUST) TPC Co-Chair： Yansong Yang (HKUST) Steering Committee: Shuji Ikeda (TEI Solutions) – Chair Bin Zhao (CTI) Arokia Nathan (Cambridge U.) Ravi Todi (Synopsys) Murty Polavarapu (BAE) Roger Booth (Qualcomm) Samar Saha (Prospicient Devices) Albert Wang (UC Riverside) Kazunari Ishimaru (Rapidus) Yogesh Chauhan (IIT Kanpur) Executive Committee: Yang Chai (HK PolyU) Roger Booth (Qualcomm) Mansun Chan (HKUST) Yansong Yang (HKUST) Ru Huang (Southeast) Qiming Shao (HKUST) Merlyne De Souza (U Sheffield) Pei-Wen Li (NCTU) Can Li (HKU) Masumi Saito (Kioxia) Zhongrui Wang (HKU) Meiki Ieong (Simbury) Carmen Fung (HKSTP) Man Hoi Wong (HKUST) Roger Booth (Qualcomm) Huaqiang Wu (Tsinghua) Rino Choi (Inha U.) Bernard Lim (Appscard) Shinichi Yoshida (SONY) Bill Nehrer (Atomera) Bich-Yen Nguyen (SOITEC) Benjamin Iniguez (URV) Edmundo Gutierrez (INAOE) Ming Yang (HK PolyU)

[Symposium] SFRC AIST

Advanced Semiconductor Research Center (SFRC) 

National Institute of Advanced Industrial Science and Technology (AIST)

1st Open Symposium 

https://unit.aist.go.jp/sfrc/sfrcsympo202405.html

Date: May 27, 2024

Venue: Fujisoft Akiba Plaza Akiba Hall (3 Kanda-Neribaki-cho, Chiyoda-ku, Tokyo) 

Hybrid event (on-site participation and remote streaming)

AGENDA:

Moderator: Takashi Matsukawa (Deputy Director, SFRC)
13:00-13:05 Opening Remarks Tetsuji Yasuda (AIST Electronics & Manufacturing)
13:05-13:10 Guest Greetings Mr. Tsutomu Kanashi (Director, Information Industry Division, Commerce and Information Policy Bureau, Ministry of Economy, Trade and Industry)
13:10-13:40 Keynote Speech 1 "Rapidus and Advanced Semiconductor Development" Masaharu Kobayashi (Rapidus Corporation)
13:40-14:10 Keynote Speech 2 "The Current Situation and Future of the Semiconductor Industry from a Systems Perspective" Kenji Tsuda (International Technology Journalist)
14:10-14:20 "Introduction to the Advanced Semiconductor Research Center" Akiue Masahara (Director, SFRC Research Center)
14:20-14:40 "Introduction of SCR Open Pilot Line" Fuminori Ito (Deputy Director, SFRC)
14:40-14:55 "2nm Generation GAA-FET Fundamental Technology" Hisashi Irizawa (SFRC) Head, Device Process Research Team)
14:55-15:10 "Extreme Device and Material Technology for the 2nm Generation and Beyond" Naoya Okada (Head, Extreme CMOS Materials Research Team, SFRC)
15:10-15:30 Coffee Break
15:30-16:00 Keynote Speech 3 "What is Open Source Utilized Silicon Initiatives (Open-SUSI)?" Jun-Ichi Okamura (AIST Solutions)
16:00-16:15 "Device Integration Technology by 3D Integrated Packaging Technology Katsuya Kikuchi (Director, SFRC 3D Integrated Technology Research Team)
16:15-16:30 "Advanced System-on-Chip (SoC) Design Technology"
Shinichi Ouchi (AIDL Laboratory Team Leader/SFRC Integrated Circuit Design Research Team)
16:30-16:45 Environmental Impact Assessment of Semiconductor Manufacturing and Greening Technologies" Shinji Mimida (SFRC)
16:45-17:00 "Quantum-related semiconductor integrated device technology" Takahiro Mori (Director, SFRC New Principles Silicon Device Research Team)
17:00-17:15 Q&A
17:15-17:30 Closing Remarks Takashi Nakano (Deputy Director, Research Strategy Planning Department, AIST)

On-site participation, remote participation: Participation is free. (Please register for this form) Remote streaming is scheduled for Zoom. Please register one by one if you wish to participate. Please note that there is a limit to the number of participants at the venue.

Secretariat contact <https://unit.aist.go.jp/sfrc/sfrcsympo202405.html>

National Institute of Advanced Industrial Science and Technology (AIST) Advanced Semiconductor Research Center Symposium Secretariat (M-SFRC-Sympo-ml@aist.go.jp)

Chipsalliance Technology Update - Nov. 2023

November 9, 2023

Check out the presentations below, and watch the replay here

• Project Open Se Cura (slides)
  Kenny Vassigh, Bangfei Pan, Cindy Liu, Kai Yick, Google, Michael Gielda, Antmicro, Brian Murray, Verisilicon
• Caliptra Workgroup Update (slides)
  Andres Lagar-Cavilla, Google
• Enabling UVM testbenches in Verilator (slides)
  Michael Gielda, Karol Gugala, Antmicro
• FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development (slides)
  Olof Kindgren, Qamcom
• CHIPYard: An Open Source RISC-V Design Framework (slides)
  Sagar Karandikar, U.C. Berkeley

Watch the Replay

[C4P] EDTM Conference 2024, Bangalore

8th IEEE Electron Devices Technology and Manufacturing

EDTM Conference 2024

Theme: Strengthening Globalization in Semiconductors

Hilton Bangalore, India, March 3rd- 6th, 2024

https://ewh.ieee.org/conf/edtm/2024/

Call for Paper: We cordially invite you to submit ORIGINAL 3-page Camera-Ready papers to the 2024 IEEE Electron Devices Technology and Manufacturing (IEEE EDTM 2024) Conference for possible presentations. Original papers are sought on any topic within the scope of IEEE EDTM 2024. There are 14 R&D Tracks for IEEE EDTM 2024, among them:

TRACK 9. Modeling and Simulation (MS)

Advances in modeling/simulation of devices, packages and processes; Technology CAD and benchmarking; Atomistic process and device simulation; Compact models for DTCO and STCO; AI/ML-augmented modelling; Material and interconnect modeling; Models for photonic devices.

Important Dates for Authors

• Three-page camera-ready paper submission starts: August 1,2023
• Paper submission deadline: October 15, 2023 October 30, 2023 
• Notification for Acceptance: December 15, 2023

Accepted IEEE EDTM 2024 papers will be considered for competition for the Best Paper Award, Best Student Paper Awards and Best Poster Awards.

More details on paper submission can be found at the Paper Submission webpage.

[open position] IHP Research Associate for Open PDK Development

Research Associate for Open PDK Development (m/f/d)

Developer for Open Source Process Design Kits

for SiGe-BiCMOS Technology

Job-ID: 7011/23 | Department: Technology | Salary: as per tariff TV-L | Working time: 40h/week (part-time work option) | Limitation: initially 2 years with option of extension for three more years | Entry Date: as soon as possible

IHP is an institute of the Leibniz Association and conducts research and development of silicon-based systems and ultra-high-frequency circuits and technologies, including new materials. It develops innovative solutions for application areas such as wireless and broadband communication, security, medical technology, industry 4.0, automotive industry, and aerospace. IHP employs approximately 350 people. It operates a pilot line for technological developments and the preparation of high-speed circuits with 0.13/0.25 µm-SiGe-BiCMOS technologies, located in a 1500 m² cleanroom that meets the highest industrial nanotechnology requirements.

The position:

As a member of the group Research & Prototyping Service, you will develop Process Design Kit for IHP’s BiCMOS technologies and new future technology modules with special focus on open source PDK development. Your detailed tasks will include programming of pCells and their integration into our verification process. Devices descriptions, user guides and test cases are important aspects of your work, too. Finally, managing our PDK repositories on Github with external contributions and adaption of existing tools like OpenRAM is part of the work. Implementation of new devices and investigations of new design tools and flows will give this position room for interesting development opportunities.

Your profile:

You hold a Master's degree in computer science with background in semiconductors, physics or electrical engineering. Knowledge in semiconductor devices and programming are of advantage. Your specialized knowledge preferably covers ASIC design environment like Cadence Virtuoso, Mentor/Siemens Tanner or KeySight ADS, OpenROAD/OpenLane, Linux and scripting languages (e.g. Python, Perl or TCL). You are well organized and always keep the overview even with many parallel projects. Thanks to your skillful communication, you are a binding and reliable contact person for our partners. You are also a strong team player, and you confidently handle the German and English language. You are also a strong team player. We are looking for a team member, who is able to structure his or her own work and to bring a well-organized and systematic way of working into the cooperation with creative minds. You are an ideal match for this position, when you have experimental, analytical and problem-solving skills, very strong communicative skills and the ability to quickly learn how to operate the latest technical equipment including various software. It is necessary that you confidently handle the English language. Knowledge of the German language is welcome. The consolidating of German language skills is expected and highly encouraged, for example in in-house language courses and intensive courses.

Your application:
Have we sparked your interest? Then we look forward to receiving your application via our online application form. For further information regarding the position, please contact Dr. René Scholz

UPCOMING – Winter School in III-Sb applications

UPCOMING

Winter School in III-Sb applications: non-volatile memories

A Modelling Perspective

QUANTIMONY’s Winter School in III-Sb Applications: non-volatile Memories: a Modelling Perspective will take place from February 27th to March 3rd 2023 at the premises of the Technical University of Berlin.

The 5-day event will focus on the design and scalable production of a new III-Sb patented memory device (ULTRARAM TM). There will be a combination of specialised lectures by international experts, and hands-on tutorials/lab sessions as well as live demonstrations of the latest TCAD/EDA tools organised by the Technical University of Berlin.

The event will provide with an excellent opportunity for networking with leaders in the field.

List of Confirmed Speakers Invited Speakers and Hands - on Session:

• Prof. Dr. Manus Hayne, Lancaster University Birth of the ULTRARAM TM Concept
• Prof. Dr. Dieter Bimberg, Technische Universität Berlin Quantum Dot-Based Flash Memories: The Holy Grail at Sunrise?
• Dr. Petr Klenovský, Masaryk University, Brno Modeling Electronic states of IlI-Sb guantum systems on GaP substrate
• Dr. Wladek Grabinski, MOS-AK (EU) FOSS TCAD/EDA Tools for Compact Modeling
• Prof. Vihar Georgiev, James Watt School of Engineering, Glasgow Nano-electronic Simulation Software (NESS): a flexible nano-device simulation platform
• PD Dr. Uwe Bandelow, WIAS Berlin TBA
• Prof. Claudia Dr.axl, Humboldt Universität Berlin Unsupervised learning for insight into high-throughput calculations
• Rabea Pons, Comsol, Göttingen Introduction into COMSOL and hands-on session
• Prof. Dr. Mathieu Luisier, ETH Zürich TBA
• Dr. Marc Bescond, Faculté des Sciences de Saint Jérôme, NQS group, Marseille TBA
• Dr. Chetan Gupta, Micron Technology (R&D) Industry perspective on memory technologies
• Prof. Dr. Jannik Wolters, Deutschen Zentrum für Luft- und Raumfahrt / TU Berlin Quantum Memories and Introduction into Quantum Technologie

More information 

[webinar] Power WBG Semiconductor Technology Opportunities

"Power WBG Semiconductor Technology Opportunities"

webinar hosted by 

Dr. Victor Veliadis, 

Executive Director and CTO of PowerAmerica, 

a WBG semiconductor power electronics consortium

Event by Łukasiewicz - Institute of Microelectronics and Photonics

Register now: https://lukasiewiczimif.clickmeeting.com/poweramerica/register

Silicon power devices have dominated power electronics due to their excellent starting material quality, ease of fabrication, low-cost volume production, and proven reliability. However, they’re approaching their operational limits primarily due to their relatively low bandgap and critical electric field that results in high conduction and switching losses, and poor high-temperature performance. So what can we do? Well, let’s talk about the favorable WBG material properties, their volume application opportunities, and last but not least let's highlight the respective competitive advantages of SiC and GaN.

You will additionally learn about:

• the lateral and vertical power device configurations that will be analyzed in the context of bidirectional switching
• specific applications and needs for bidirectional switches
• key topologies, enabled by bidirectional switches
• PowerAmerica’s work to accelerate WBG power electronics commercialization

About Dr. Veliadis: Dr. Victor Veliadis is Executive Director and CTO of PowerAmerica, a WBG semiconductor power electronics consortium. At PowerAmerica, he has managed a budget of $146 million that he strategically allocated to 200 industrial and University projects to accelerate WBG semiconductor clean energy manufacturing, workforce development, and job creation. His PowerAmerica educational activities have trained 410 University FTE students in applied WBG projects, and engaged 4100 attendees in tutorials, short courses, and webinars. Dr. Veliadis is an ECE Professor at NCSU and an IEEE Fellow and EDS Distinguished Lecturer. He has 27 issued U.S. patents, 6 book chapters, and over 125 peer-reviewed publications. Prior to entering academia and taking an executive position at Power America in 2016, Dr. Veliadis spent 21 years in the semiconductor industry where his work included design, fabrication, and testing of SiC devices, GaN devices for military radar amplifiers, and financial and operations management of a commercial semiconductor fab. He has a Ph.D. degree in Electrical Engineering from John Hopkins University (1995).

[App Note] Frenetic use A.I. technology to design optimal transformers

Frenetic is a power electronics company created with the goal of making magnetics simple. Frenetic is revolutionizing the world of magnetics with A.I. technology, which is replacing the need for outdated engineering methods. The A.I. technology allows designing optimal transformers and inductors, build and test samples in our laboratory and get the best manufacturing solutions for our clients in order to ensure that quality and timelines are respected.

App Note: Planar Transformer with Half Turns

New proposed solution for the transformer was based on a 4-column structure, where the flux cancellations reduce the core losses and allow keeping high power density. The solution was used in an LLC converter, obtaining a power density of 55 W/cm3.

References
[1] Y. -C. Liu et al., "Design and Implementation of a Planar Transformer With Fractional Turns for High Power Density LLC Resonant Converters," in IEEE Transactions on Power Electronics, vol. 36, no. 5, pp. 5191-5203, May 2021, doi: 10.1109/TPEL.2020.3029001.
[2] D. Huang, S. Ji and F. C. Lee, "LLC resonant converter with matrix transformer", IEEE Trans. Power Electron., vol. 29, no. 8, pp. 4339-4347, Aug. 2014.
[3] C. Fei, F. C. Lee and Q. Li, "High-efficiency high-power-density LLC converter with an integrated planar matrix transformer for high-output current applications", IEEE Trans. Ind. Electron., vol. 64, no. 11, pp. 9072-9082, Nov. 2017.

[CAS Seasonal School] How Technology is Impacting Agribusiness

How Technology is Impacting Agribusiness

A CAS seasonal school on technology and agribusiness will be held virtually from November 16th to November 20th. The program is quite interesting and we invite you to register through our web page www.asic-chile.cl. Registration is free.

The current world population of 7.6 billion is expected to reach 9.8 billion in 2050. According to the United Nations Food and Agriculture Organization (FAO) global agricultural productivity must increase by 50% – 70% to be able to feed the world population in 2050. Other researchers consider that reducing the waste of food would be enough.

Factors if not obstacles to be considered to meet global food demand by 2050 and beyond:

• Less arable land: As cities are growing, the space allowed to agriculture is shrinking.
• Climate change: Impacting dramatically agribusiness.
• Role of the agribusiness on the GHG emissions.
• Planet boundaries and the role of agribusiness.
• Availability of freshwater.
• Soil degradation.

The need has never been greater for innovative and sustainable solutions and technology should lead to significant improvement in our food and nutritional security.

In this seasonal school prestigious researchers and experts from all over the world will present the problems and challenges agribusiness is facing and how technologies such as IoT, AI, Machine Learning, sensors, electronic circuits, electronic systems, ICs, etc., can be applied to improve and solve the majority of those problems.

This is the first of a series of “Technology and Agribusiness” Seasonal Schools. It will be a meeting point for professionals working on Precision and Smart Agriculture, as well as professionals working on IoT, sensors, electronic circuits, electronic systems, ICs, etc.

We invite you to participate in this first version of the Technology and Agribusiness Seasonal School, which due to the pandemic will be 100% online and free of charge.

Join us!

[C4P] Advanced FETs: Design, Fabrication and Applications

Call for Papers: Special MDPI  Issue 

"Advanced Field Effect Transistors: Design, Fabrication and Applications"

Deadline for manuscript submissions: 31 July 2021.

Dear Colleagues,

Planar MOS Field Effect Transistors (MOSFETs) were invented by Atalla and Kahng in 1959. After a decade, the MOSFETs entered mass production, as basic building blocks of P-, N-, and CMOS integrated circuits (ICs). Until the end of the twentieth century, MOSFET performance was largely improved by the implementation of so-called scaling rules. An exponential growth in the time of the transistor number per chip (observation formulated as Moore law) was achieved. This, together with advantageous characteristics and a nice feature of the planar MOSFETs allowing one to design the ICs by defining a width/length ratio, led to the great success of the CMOS technology on Si and SOI substrates.

However, starting from the 90 nm node, it has been observed that the standard scaling does not sufficiently translate into MOSFET performance improvement. Moreover, some device characteristics become degraded, e.g. gate leakage, channel leakage, variability and reliability. This has led to the development of preventative measures (e.g. high-k dielectrics) or performance boosters (e.g. channel strain engineering and channel materials). Furthermore, 2D and 3D multi-gate FETs were introduced to improve gate control over the channel and increase the channel aspect ratio. Multi-gate FETs are the only option for the 5nm node, which is expected soon, whereas they will have to be replaced by surrounding gate FETs for the 3nm node. For the past few years, the attention of researchers has been attracted by steep-subthreshold slope devices, enabling the reduction of supply voltage. A need for devices for quantum computing has appeared. FETs and HEMTs, for very high frequency applications, GaN, SiC and FETs for high voltage, high power, high temperature applications, and many other FET types, are in use or under development as a micro- and nanoelectronics reply to electronics needs in different domains.

There are many issues regarding the design, fabrication and applications of advanced field effect transistors. It is my pleasure to invite you to share your expertise in this Special Issue. Full papers, communications and reviews are all welcome.

Dr. Daniel Tomaszewski, ITE, Warsaw (PL)
Special Issue Guest Editor

[read more...]

The ITRS, 2013 Edition is now online.

 The link below will take you to the site for the summary information
http://www.itrs.net/Links/2013ITRS/Summary2013.htm

 For the full edition details, follow this link
http://www.itrs.net/Links/2013ITRS/Home2013.htm

[read more...]