[paper] Gradient Minimization in Layout Patterns for Analog Circuits

Isaac Bruce, Michael Sekyere, Ruohan Yang, Saeid Karimpour, Colin C. McAndrew, Degang Chen

Gradient Minimization in Layout Patterns for Analog Circuits

Circuits, Systems, and Signal Processing. 1-22.

DOI: 10.1007/s00034-025-03158-x

1 Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA

 

Abstract: In this paper, we present an algorithm to generate the layout of a pair of devices A and B for a given matching ratio r and total unit cell count N that minimizes the mismatch due to systematic gradient effects. The algorithm relies on simple reflections and rotations of an initial optimized pattern across 4 quadrants. The approach cancels all odd-order systematic gradients and minimizes 2nd order systematic gradients. The method can easily be extended to cancel higher-order even gradient effects. The validity of the proposed algorithm is demonstrated via numerical simulations. Additionally, an electrothermal simulation of a set of layouts is run to further validate the proposed layout generation scheme.

FIG: Layout of circuit design with heat sources and current sources 

for the optimal transistor array pattern.

[book] From Code to Chip

Jakob Ratschenberger and Harald Pretl

From Code to Chip:

Open-Source Automated Analog Layout Design

pp: XV, 120 Publisher: Springer Cham (10 January 2025)

eBook ISBN 978-3-031-68562-0

This book shows how the layout of an analog circuit can be automatically generated in a fully open-source way. Based on an exemplary design flow, it introduces and explains the necessary steps for transforming a SPICE netlist into a layout, which can be inspected by the open-source layout editor Magic VLSI. This is done by using the industry’s first open-source process design kit SKY130. Furthermore, the implementation of the design flow in the programming language Python is available as open-source on GitHub. 

Authors' Affiliations

Johannes Kepler University, Linz, Austria

Table of contents (8 chapters)

• Front Matter pp. i-xv
• Download chapter PDF 
• Introduction pp. 1-4
• Theoretical Basics pp. 5-13
• Circuit Capturing pp. 15-36
• PDK—Design Rule Capturing pp. 37-41
• Placement pp. 43-55
• Routing pp. 57-71
• Experimental Results pp. 73-99
• Outlook pp. 101-103
• Back Matter pp. 105-120

 

[IEEE SSCS] “PICO” Open-Source Chipathon

IEEE SSCS “PICO” Open-Source Chipathon

Automating Analog Layout

https://sscs.ieee.org/about/tc-ose/sscs-pico-design-contest

– Sign-Up Deadline: May 10, 2024 –

The IEEE Solid-State Circuits Society is pleased to announce its fourth open-source integrated circuit (IC) design contest under the umbrella of its PICO Program (Platform for IC Design Outreach). While this contest is open to anyone (no restrictions), we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community. 

The goal of this year’s event is to advance the automatic generation and open sharing of analog circuit layout cells to increase our community’s design productivity and to catch up with other fields where sharing and automation is a key enabler of progress (e.g., in machine learning).

Die photo in background courtesy of IBM

Contest Outline

1. Interested individuals sign up using this form by May 10, 2024.
2. Phase 1 (~June): Through a series of weekly meet-ups and training sessions, the participants learn to create basic one- or two-transistor layout generators using Python and open-source CMOS PDKs. Using Jupyter Notebooks hosted on Google Colab allows anyone with an internet connection to participate - no downloads or installations required! Relevant circuit examples can be found in [1], [2]. We will leverage code modules available with the OpenFASoC [3] environment.
3. Phase 2 (~July): Interested participants define larger layout building blocks that they wish to automate (examples: comparator, bandgap, phase interpolator, OTA). Teaming among participants is encouraged to maximize collaboration and learning).
4. Phase 3 (~August-September): Participants implement their generators and submit sample layouts and test structures for potential tape-out to an open-source MPW (tentatively SKY130).
5. Phase 4 (~October-November): A jury evaluates the created generators/layouts and selects the test structures that will be taped out. The teams work together to assemble a shared database with all the designs and to complete the tapeout. Ideally, this phase will involve automated verification through CACE [4] or a similar tool.
6. Phase 5 (TBD): The designs will be tested using lab measurements by a subset of participants and SSCS volunteers with access to lab facilities. Some of the test setups may be available for remote characterization. The obtained measurement data will be added to the repositories containing the layout generators.

 References

[1] H. Pretl, “Fifty Nifty Variations of Two-Transistor Circuits,” MOS-AK Workshop Spring 2022, URL: https://www.mos-ak.org/spring_2022/presentations/Pretl_Spring_MOS-AK_2022.pdf.
[2] H. Pretl and M. Eberlein, "Fifty Nifty Variations of Two-Transistor Circuits: A tribute to the versatility of MOSFETs," in IEEE Solid-State Circuits Magazine, vol. 13, no. 3, pp. 38-46, Summer 2021, URL: https://ieeexplore.ieee.org/document/9523464.
[3] OpenFASoC: Fully Open-Source Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits, https://github.com/idea-fasoc/OpenFASOC/.
[4] Circuit Automatic Characterization Engine, URL: https://github.com/efabless/cace.

[paper] Compact Models for Sizing Based on ANN

Husni Habal, Dobroslav Tsonev, Matthias Schweikardt 

Compact Models for Initial MOSFET Sizing Based on Higher-order Artificial Neural Networks

ACM/IEEE Workshop on Machine Learning for CAD (MLCAD ’20)

Nov. 16–20, 2020, Virtual Event, Iceland. ACM, pp. 111-116

DOI: 10.1145/3380446.3430632

¹Infineon Technologies AG Munich, Germany
²LogiqWorks Ltd. Sofia, Bulgaria
³Reutlingen University Reutlingen, Germany

Abstract: Simple MOSFET models intended for hand analysis are inaccurate in deep sub-micrometer process technologies and in the moderate inversion region of device operation. Accurate models, such as BSIM6 model, are too complex for use in hand analysis and are intended for circuit simulators. Artificial neural networks (ANNs) are efficient at capturing both linear and non-linear multivariate relationships. In this work, a straightforward modeling technique is presented using ANNs to replace the BSIM model equations. Existing open-source libraries are used to quickly build models with error rates generally below 3%. When combined with a novel approach, such as the gm/Id systematic design method, the presented models are sufficiently accurate for use in the initial sizing of analog circuit components without simulation.

Figure: ANN Model Architecture.

On Layout Tools and others

A while ago SolvEx Group has posted a blog note on the Layout Tools, including the open source ones, too. There are also a few questions which are worth to review again:

1. How is Layout different from Placement and Route?
2. What is the difference between Synopsys Astro and Cadence Virtuoso-do they offer layout or are just placement and routing tools? (Comparing them with Magic and LASI)!
3. What is the intermediate map/snapshot/diagram - which we can use and create a complete chip out of? For example after seeing the Chip and reverse engineering the same- what is that something which I can use to create my own chip in the foundry? Reference - Chinese Mobile chips. They do the same-as they bypass the flow for design entry/verification/simulation/floor planning etc and release the chip within a few hrs of seeing the original chip(say famous case of duplicating iPhone/Nokia in the Chinese markets)
4. Are Stick Diagrams passed to the Foundry or else what is the base unit that is given to Foundry as an input to be manufactured as a chip.
5. Giving below a collection all possibly available Layout Tools (Categorized as Open Source, Cheap, Expensive)

Open source software	Description	Web site
wol	Wol is a graphical environment for IC mask layout	http://www.cs.berkeley.edu/~lazzaro/chipmunk/describe/wol.html
toped	Micron based layout editor with extensive scripting capabilities. Under active development and part of Fedora Electronic Lab.	http://www.toped.org.uk
microwind3	Lambda based layout editor especially adapted for interactive design with Spice. This used to be completely free, but now only a Lite version is.	http://www.microwind.org
magic	Lambda based layout editor with good options for writing CIF and/or GDS files. Supports scripting. Large user base. Part of Fedora Electronic Lab. Used for extraction and CIF/GDS creation by the pharosc libraries	http://opencircuitdesign.com/magic
lasi	LASI stands for LAyout Software for Individuals. It is designed to run on Windows, though it also runs on Linux under Crossover Office. Actively used software with frequent updates.	http://lasihomesite.com
kic	Part of open source packages released by Whiteley Research.	http://wrcad.com/freestuff.html
graal	Lambda based layout editor allowing conversion to CIF and GDS with appropriate technology files. Dreal is the companion software to view CIF and GDS. Part of a tool set from Alliance which is probably the best open-source software for IC design. Comes with own standard cell library. Part of Fedora Electronic Lab. The pharosc standard cells are drawn with graal.	http://www-asim.lip6.fr/recherche/alliance
electric	Comprehensive set of software programs designed around the concept of silicon compilation. Version 6 crashed a lot, and stored all design data in a single file which exposed one to the risk of file corruption and loss of all data (I speak from experience). New version written in Java. Extensive documentation.	http://www.staticfreesoft.com/productsSoftware.html
dreal	Simple layout editor which uses CIF or GDS as its native format. Companion software is Graal.	http://www-asim.lip6.fr/recherche/alliance
Cheap software
xic	Whiteley Research Inc. Layout editor with linked Spice simulator. List price is $1195.	http://www.wrcad.com/xic.html
slam-edit	Stabie-Soft Inc. Unix/Linux based layout editor. It seems a licence cannot be purchsed, only leased for one year periods (bad if the company folds). List price on web site is $2,000 per year.	http://www.stabie-soft.com/sledit.html
ledit	Tanner Research Inc. Windows only layout editor popular with mixed signal designers. Ledit sed to cost $1,000, but this price could not be verified (which is surprising since low price is a key selling point of the software).	http://www.tanner.com/EDA/product/Tools_PhysicalLayout.html
layedpro	Mycad Inc. Windows only layout editor designed in Korea but supported for English language users from California. No new product since 2005 on US site, but Korean site seems active. No price could be confirmed.	http://www.mycad.com/02pro/01.html http://www.mycad.co.kr
layed	Catena Software GmbH. Demo versions for Linux and Windows can be downloaded. List price of the basic editor might be €1,585 (could not be recently verified).	http://www.catena-ffo.de/laytools.htm
iced	IC Editors Inc. Windows only editor that used to cost $2,750. Now it is free but with a restrictive licence. Work is on-going to open source it which might make it available under Linux (although the Windows drawing primitives would need to be replaced with GTK).	http://www.iceditors.com
Expensive software
virtuoso	Cadence Design Systems, Inc. The market leader. The price might be $40,000 to lease for one year.	http://www.cadence.com/products/custom_ic/veditor/index.aspx
max	Micro Magic Inc. Looks like a commercial version of Magic. Price is $30,000 for a one year licence. Despite the fancy price tag, something was freely downloadable from the web in the 2004 timeframe.	http://www.micromagic.com
laker	Silicon Canvas Inc. Linux and Unix based editor. Top of the line laker-ddl is $70,000 for a one year licence. Regular Laker 3 is $35,000 for a one year licence.	http://www.sicanvas.com
icstation	Mentor Graphics Corp. No public pricing information could be found.	http://www.mentor.com/cicd/icstation.html